cy82c693.c revision 25985edcedea6396277003854657b5f3cb31a628
1/* 2 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer 3 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator 4 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz 5 * 6 * CYPRESS CY82C693 chipset IDE controller 7 * 8 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards. 9 */ 10 11#include <linux/module.h> 12#include <linux/types.h> 13#include <linux/pci.h> 14#include <linux/ide.h> 15#include <linux/init.h> 16 17#include <asm/io.h> 18 19#define DRV_NAME "cy82c693" 20 21/* 22 * NOTE: the value for busmaster timeout is tricky and I got it by 23 * trial and error! By using a to low value will cause DMA timeouts 24 * and drop IDE performance, and by using a to high value will cause 25 * audio playback to scatter. 26 * If you know a better value or how to calc it, please let me know. 27 */ 28 29/* twice the value written in cy82c693ub datasheet */ 30#define BUSMASTER_TIMEOUT 0x50 31/* 32 * the value above was tested on my machine and it seems to work okay 33 */ 34 35/* here are the offset definitions for the registers */ 36#define CY82_IDE_CMDREG 0x04 37#define CY82_IDE_ADDRSETUP 0x48 38#define CY82_IDE_MASTER_IOR 0x4C 39#define CY82_IDE_MASTER_IOW 0x4D 40#define CY82_IDE_SLAVE_IOR 0x4E 41#define CY82_IDE_SLAVE_IOW 0x4F 42#define CY82_IDE_MASTER_8BIT 0x50 43#define CY82_IDE_SLAVE_8BIT 0x51 44 45#define CY82_INDEX_PORT 0x22 46#define CY82_DATA_PORT 0x23 47 48#define CY82_INDEX_CHANNEL0 0x30 49#define CY82_INDEX_CHANNEL1 0x31 50#define CY82_INDEX_TIMEOUT 0x32 51 52/* 53 * set DMA mode a specific channel for CY82C693 54 */ 55 56static void cy82c693_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) 57{ 58 const u8 mode = drive->dma_mode; 59 u8 single = (mode & 0x10) >> 4, index = 0, data = 0; 60 61 index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0; 62 63 data = (mode & 3) | (single << 2); 64 65 outb(index, CY82_INDEX_PORT); 66 outb(data, CY82_DATA_PORT); 67 68 /* 69 * note: below we set the value for Bus Master IDE TimeOut Register 70 * I'm not absolutely sure what this does, but it solved my problem 71 * with IDE DMA and sound, so I now can play sound and work with 72 * my IDE driver at the same time :-) 73 * 74 * If you know the correct (best) value for this register please 75 * let me know - ASK 76 */ 77 78 data = BUSMASTER_TIMEOUT; 79 outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT); 80 outb(data, CY82_DATA_PORT); 81} 82 83static void cy82c693_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 84{ 85 struct pci_dev *dev = to_pci_dev(hwif->dev); 86 int bus_speed = ide_pci_clk ? ide_pci_clk : 33; 87 const unsigned long T = 1000000 / bus_speed; 88 unsigned int addrCtrl; 89 struct ide_timing t; 90 u8 time_16, time_8; 91 92 /* select primary or secondary channel */ 93 if (hwif->index > 0) { /* drive is on the secondary channel */ 94 dev = pci_get_slot(dev->bus, dev->devfn+1); 95 if (!dev) { 96 printk(KERN_ERR "%s: tune_drive: " 97 "Cannot find secondary interface!\n", 98 drive->name); 99 return; 100 } 101 } 102 103 ide_timing_compute(drive, drive->pio_mode, &t, T, 1); 104 105 time_16 = clamp_val(t.recover - 1, 0, 15) | 106 (clamp_val(t.active - 1, 0, 15) << 4); 107 time_8 = clamp_val(t.act8b - 1, 0, 15) | 108 (clamp_val(t.rec8b - 1, 0, 15) << 4); 109 110 /* now let's write the clocks registers */ 111 if ((drive->dn & 1) == 0) { 112 /* 113 * set master drive 114 * address setup control register 115 * is 32 bit !!! 116 */ 117 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); 118 119 addrCtrl &= (~0xF); 120 addrCtrl |= clamp_val(t.setup - 1, 0, 15); 121 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); 122 123 /* now let's set the remaining registers */ 124 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16); 125 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16); 126 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8); 127 } else { 128 /* 129 * set slave drive 130 * address setup control register 131 * is 32 bit !!! 132 */ 133 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); 134 135 addrCtrl &= (~0xF0); 136 addrCtrl |= (clamp_val(t.setup - 1, 0, 15) << 4); 137 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); 138 139 /* now let's set the remaining registers */ 140 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16); 141 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16); 142 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8); 143 } 144} 145 146static void __devinit init_iops_cy82c693(ide_hwif_t *hwif) 147{ 148 static ide_hwif_t *primary; 149 struct pci_dev *dev = to_pci_dev(hwif->dev); 150 151 if (PCI_FUNC(dev->devfn) == 1) 152 primary = hwif; 153 else { 154 hwif->mate = primary; 155 hwif->channel = 1; 156 } 157} 158 159static const struct ide_port_ops cy82c693_port_ops = { 160 .set_pio_mode = cy82c693_set_pio_mode, 161 .set_dma_mode = cy82c693_set_dma_mode, 162}; 163 164static const struct ide_port_info cy82c693_chipset __devinitdata = { 165 .name = DRV_NAME, 166 .init_iops = init_iops_cy82c693, 167 .port_ops = &cy82c693_port_ops, 168 .host_flags = IDE_HFLAG_SINGLE, 169 .pio_mask = ATA_PIO4, 170 .swdma_mask = ATA_SWDMA2, 171 .mwdma_mask = ATA_MWDMA2, 172}; 173 174static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id) 175{ 176 struct pci_dev *dev2; 177 int ret = -ENODEV; 178 179 /* CY82C693 is more than only a IDE controller. 180 Function 1 is primary IDE channel, function 2 - secondary. */ 181 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && 182 PCI_FUNC(dev->devfn) == 1) { 183 dev2 = pci_get_slot(dev->bus, dev->devfn + 1); 184 ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL); 185 if (ret) 186 pci_dev_put(dev2); 187 } 188 return ret; 189} 190 191static void __devexit cy82c693_remove(struct pci_dev *dev) 192{ 193 struct ide_host *host = pci_get_drvdata(dev); 194 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL; 195 196 ide_pci_remove(dev); 197 pci_dev_put(dev2); 198} 199 200static const struct pci_device_id cy82c693_pci_tbl[] = { 201 { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 }, 202 { 0, }, 203}; 204MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl); 205 206static struct pci_driver cy82c693_pci_driver = { 207 .name = "Cypress_IDE", 208 .id_table = cy82c693_pci_tbl, 209 .probe = cy82c693_init_one, 210 .remove = __devexit_p(cy82c693_remove), 211 .suspend = ide_pci_suspend, 212 .resume = ide_pci_resume, 213}; 214 215static int __init cy82c693_ide_init(void) 216{ 217 return ide_pci_register_driver(&cy82c693_pci_driver); 218} 219 220static void __exit cy82c693_ide_exit(void) 221{ 222 pci_unregister_driver(&cy82c693_pci_driver); 223} 224 225module_init(cy82c693_ide_init); 226module_exit(cy82c693_ide_exit); 227 228MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz"); 229MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE"); 230MODULE_LICENSE("GPL"); 231