hpt366.c revision 35c9b4daf4c94b30e5cede597d98016ebf31b5ad
1/* 2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 3 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 4 * Portions Copyright (C) 2003 Red Hat Inc 5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz 6 * Portions Copyright (C) 2005-2008 MontaVista Software, Inc. 7 * 8 * Thanks to HighPoint Technologies for their assistance, and hardware. 9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his 10 * donation of an ABit BP6 mainboard, processor, and memory acellerated 11 * development and support. 12 * 13 * 14 * HighPoint has its own drivers (open source except for the RAID part) 15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/. 16 * This may be useful to anyone wanting to work on this driver, however do not 17 * trust them too much since the code tends to become less and less meaningful 18 * as the time passes... :-/ 19 * 20 * Note that final HPT370 support was done by force extraction of GPL. 21 * 22 * - add function for getting/setting power status of drive 23 * - the HPT370's state machine can get confused. reset it before each dma 24 * xfer to prevent that from happening. 25 * - reset state engine whenever we get an error. 26 * - check for busmaster state at end of dma. 27 * - use new highpoint timings. 28 * - detect bus speed using highpoint register. 29 * - use pll if we don't have a clock table. added a 66MHz table that's 30 * just 2x the 33MHz table. 31 * - removed turnaround. NOTE: we never want to switch between pll and 32 * pci clocks as the chip can glitch in those cases. the highpoint 33 * approved workaround slows everything down too much to be useful. in 34 * addition, we would have to serialize access to each chip. 35 * Adrian Sun <a.sun@sun.com> 36 * 37 * add drive timings for 66MHz PCI bus, 38 * fix ATA Cable signal detection, fix incorrect /proc info 39 * add /proc display for per-drive PIO/DMA/UDMA mode and 40 * per-channel ATA-33/66 Cable detect. 41 * Duncan Laurie <void@sun.com> 42 * 43 * fixup /proc output for multiple controllers 44 * Tim Hockin <thockin@sun.com> 45 * 46 * On hpt366: 47 * Reset the hpt366 on error, reset on dma 48 * Fix disabling Fast Interrupt hpt366. 49 * Mike Waychison <crlf@sun.com> 50 * 51 * Added support for 372N clocking and clock switching. The 372N needs 52 * different clocks on read/write. This requires overloading rw_disk and 53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for 54 * keeping me sane. 55 * Alan Cox <alan@lxorguk.ukuu.org.uk> 56 * 57 * - fix the clock turnaround code: it was writing to the wrong ports when 58 * called for the secondary channel, caching the current clock mode per- 59 * channel caused the cached register value to get out of sync with the 60 * actual one, the channels weren't serialized, the turnaround shouldn't 61 * be done on 66 MHz PCI bus 62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used 63 * does not allow for this speed anyway 64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips, 65 * their primary channel is kind of virtual, it isn't tied to any pins) 66 * - fix/remove bad/unused timing tables and use one set of tables for the whole 67 * HPT37x chip family; save space by introducing the separate transfer mode 68 * table in which the mode lookup is done 69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives 70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS; 71 * read it only from the function 0 of HPT374 chips 72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus, 73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead 74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as 75 * they tamper with its fields 76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure 77 * since they may tamper with its fields 78 * - prefix the driver startup messages with the real chip name 79 * - claim the extra 240 bytes of I/O space for all chips 80 * - optimize the UltraDMA filtering and the drive list lookup code 81 * - use pci_get_slot() to get to the function 1 of HPT36x/374 82 * - cache offset of the channel's misc. control registers (MCRs) being used 83 * throughout the driver 84 * - only touch the relevant MCR when detecting the cable type on HPT374's 85 * function 1 86 * - rename all the register related variables consistently 87 * - move all the interrupt twiddling code from the speedproc handlers into 88 * init_hwif_hpt366(), also grouping all the DMA related code together there 89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and 90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings 91 * when setting an UltraDMA mode 92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select 93 * the best possible one 94 * - clean up DMA timeout handling for HPT370 95 * - switch to using the enumeration type to differ between the numerous chip 96 * variants, matching PCI device/revision ID with the chip type early, at the 97 * init_setup stage 98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies, 99 * stop duplicating it for each channel by storing the pointer in the pci_dev 100 * structure: first, at the init_setup stage, point it to a static "template" 101 * with only the chip type and its specific base DPLL frequency, the highest 102 * UltraDMA mode, and the chip settings table pointer filled, then, at the 103 * init_chipset stage, allocate per-chip instance and fill it with the rest 104 * of the necessary information 105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code, 106 * switch to calculating PCI clock frequency based on the chip's base DPLL 107 * frequency 108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on 109 * anything newer than HPT370/A (except HPT374 that is not capable of this 110 * mode according to the manual) 111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(), 112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips; 113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining 114 * the register setting lists into the table indexed by the clock selected 115 * - set the correct hwif->ultra_mask for each individual chip 116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards 117 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com> 118 */ 119 120#include <linux/types.h> 121#include <linux/module.h> 122#include <linux/kernel.h> 123#include <linux/delay.h> 124#include <linux/blkdev.h> 125#include <linux/interrupt.h> 126#include <linux/pci.h> 127#include <linux/init.h> 128#include <linux/ide.h> 129 130#include <asm/uaccess.h> 131#include <asm/io.h> 132 133#define DRV_NAME "hpt366" 134 135/* various tuning parameters */ 136#define HPT_RESET_STATE_ENGINE 137#undef HPT_DELAY_INTERRUPT 138 139static const char *quirk_drives[] = { 140 "QUANTUM FIREBALLlct08 08", 141 "QUANTUM FIREBALLP KA6.4", 142 "QUANTUM FIREBALLP LM20.4", 143 "QUANTUM FIREBALLP LM20.5", 144 NULL 145}; 146 147static const char *bad_ata100_5[] = { 148 "IBM-DTLA-307075", 149 "IBM-DTLA-307060", 150 "IBM-DTLA-307045", 151 "IBM-DTLA-307030", 152 "IBM-DTLA-307020", 153 "IBM-DTLA-307015", 154 "IBM-DTLA-305040", 155 "IBM-DTLA-305030", 156 "IBM-DTLA-305020", 157 "IC35L010AVER07-0", 158 "IC35L020AVER07-0", 159 "IC35L030AVER07-0", 160 "IC35L040AVER07-0", 161 "IC35L060AVER07-0", 162 "WDC AC310200R", 163 NULL 164}; 165 166static const char *bad_ata66_4[] = { 167 "IBM-DTLA-307075", 168 "IBM-DTLA-307060", 169 "IBM-DTLA-307045", 170 "IBM-DTLA-307030", 171 "IBM-DTLA-307020", 172 "IBM-DTLA-307015", 173 "IBM-DTLA-305040", 174 "IBM-DTLA-305030", 175 "IBM-DTLA-305020", 176 "IC35L010AVER07-0", 177 "IC35L020AVER07-0", 178 "IC35L030AVER07-0", 179 "IC35L040AVER07-0", 180 "IC35L060AVER07-0", 181 "WDC AC310200R", 182 "MAXTOR STM3320620A", 183 NULL 184}; 185 186static const char *bad_ata66_3[] = { 187 "WDC AC310200R", 188 NULL 189}; 190 191static const char *bad_ata33[] = { 192 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", 193 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 194 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 195 "Maxtor 90510D4", 196 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 197 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 198 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 199 NULL 200}; 201 202static u8 xfer_speeds[] = { 203 XFER_UDMA_6, 204 XFER_UDMA_5, 205 XFER_UDMA_4, 206 XFER_UDMA_3, 207 XFER_UDMA_2, 208 XFER_UDMA_1, 209 XFER_UDMA_0, 210 211 XFER_MW_DMA_2, 212 XFER_MW_DMA_1, 213 XFER_MW_DMA_0, 214 215 XFER_PIO_4, 216 XFER_PIO_3, 217 XFER_PIO_2, 218 XFER_PIO_1, 219 XFER_PIO_0 220}; 221 222/* Key for bus clock timings 223 * 36x 37x 224 * bits bits 225 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 226 * cycles = value + 1 227 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 228 * cycles = value + 1 229 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 230 * register access. 231 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 232 * register access. 233 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 234 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock. 235 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and 236 * MW DMA xfer. 237 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for 238 * task file register access. 239 * 28 28 UDMA enable. 240 * 29 29 DMA enable. 241 * 30 30 PIO MST enable. If set, the chip is in bus master mode during 242 * PIO xfer. 243 * 31 31 FIFO enable. 244 */ 245 246static u32 forty_base_hpt36x[] = { 247 /* XFER_UDMA_6 */ 0x900fd943, 248 /* XFER_UDMA_5 */ 0x900fd943, 249 /* XFER_UDMA_4 */ 0x900fd943, 250 /* XFER_UDMA_3 */ 0x900ad943, 251 /* XFER_UDMA_2 */ 0x900bd943, 252 /* XFER_UDMA_1 */ 0x9008d943, 253 /* XFER_UDMA_0 */ 0x9008d943, 254 255 /* XFER_MW_DMA_2 */ 0xa008d943, 256 /* XFER_MW_DMA_1 */ 0xa010d955, 257 /* XFER_MW_DMA_0 */ 0xa010d9fc, 258 259 /* XFER_PIO_4 */ 0xc008d963, 260 /* XFER_PIO_3 */ 0xc010d974, 261 /* XFER_PIO_2 */ 0xc010d997, 262 /* XFER_PIO_1 */ 0xc010d9c7, 263 /* XFER_PIO_0 */ 0xc018d9d9 264}; 265 266static u32 thirty_three_base_hpt36x[] = { 267 /* XFER_UDMA_6 */ 0x90c9a731, 268 /* XFER_UDMA_5 */ 0x90c9a731, 269 /* XFER_UDMA_4 */ 0x90c9a731, 270 /* XFER_UDMA_3 */ 0x90cfa731, 271 /* XFER_UDMA_2 */ 0x90caa731, 272 /* XFER_UDMA_1 */ 0x90cba731, 273 /* XFER_UDMA_0 */ 0x90c8a731, 274 275 /* XFER_MW_DMA_2 */ 0xa0c8a731, 276 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */ 277 /* XFER_MW_DMA_0 */ 0xa0c8a797, 278 279 /* XFER_PIO_4 */ 0xc0c8a731, 280 /* XFER_PIO_3 */ 0xc0c8a742, 281 /* XFER_PIO_2 */ 0xc0d0a753, 282 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */ 283 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */ 284}; 285 286static u32 twenty_five_base_hpt36x[] = { 287 /* XFER_UDMA_6 */ 0x90c98521, 288 /* XFER_UDMA_5 */ 0x90c98521, 289 /* XFER_UDMA_4 */ 0x90c98521, 290 /* XFER_UDMA_3 */ 0x90cf8521, 291 /* XFER_UDMA_2 */ 0x90cf8521, 292 /* XFER_UDMA_1 */ 0x90cb8521, 293 /* XFER_UDMA_0 */ 0x90cb8521, 294 295 /* XFER_MW_DMA_2 */ 0xa0ca8521, 296 /* XFER_MW_DMA_1 */ 0xa0ca8532, 297 /* XFER_MW_DMA_0 */ 0xa0ca8575, 298 299 /* XFER_PIO_4 */ 0xc0ca8521, 300 /* XFER_PIO_3 */ 0xc0ca8532, 301 /* XFER_PIO_2 */ 0xc0ca8542, 302 /* XFER_PIO_1 */ 0xc0d08572, 303 /* XFER_PIO_0 */ 0xc0d08585 304}; 305 306#if 0 307/* These are the timing tables from the HighPoint open source drivers... */ 308static u32 thirty_three_base_hpt37x[] = { 309 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */ 310 /* XFER_UDMA_5 */ 0x12446231, 311 /* XFER_UDMA_4 */ 0x12446231, 312 /* XFER_UDMA_3 */ 0x126c6231, 313 /* XFER_UDMA_2 */ 0x12486231, 314 /* XFER_UDMA_1 */ 0x124c6233, 315 /* XFER_UDMA_0 */ 0x12506297, 316 317 /* XFER_MW_DMA_2 */ 0x22406c31, 318 /* XFER_MW_DMA_1 */ 0x22406c33, 319 /* XFER_MW_DMA_0 */ 0x22406c97, 320 321 /* XFER_PIO_4 */ 0x06414e31, 322 /* XFER_PIO_3 */ 0x06414e42, 323 /* XFER_PIO_2 */ 0x06414e53, 324 /* XFER_PIO_1 */ 0x06814e93, 325 /* XFER_PIO_0 */ 0x06814ea7 326}; 327 328static u32 fifty_base_hpt37x[] = { 329 /* XFER_UDMA_6 */ 0x12848242, 330 /* XFER_UDMA_5 */ 0x12848242, 331 /* XFER_UDMA_4 */ 0x12ac8242, 332 /* XFER_UDMA_3 */ 0x128c8242, 333 /* XFER_UDMA_2 */ 0x120c8242, 334 /* XFER_UDMA_1 */ 0x12148254, 335 /* XFER_UDMA_0 */ 0x121882ea, 336 337 /* XFER_MW_DMA_2 */ 0x22808242, 338 /* XFER_MW_DMA_1 */ 0x22808254, 339 /* XFER_MW_DMA_0 */ 0x228082ea, 340 341 /* XFER_PIO_4 */ 0x0a81f442, 342 /* XFER_PIO_3 */ 0x0a81f443, 343 /* XFER_PIO_2 */ 0x0a81f454, 344 /* XFER_PIO_1 */ 0x0ac1f465, 345 /* XFER_PIO_0 */ 0x0ac1f48a 346}; 347 348static u32 sixty_six_base_hpt37x[] = { 349 /* XFER_UDMA_6 */ 0x1c869c62, 350 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */ 351 /* XFER_UDMA_4 */ 0x1c8a9c62, 352 /* XFER_UDMA_3 */ 0x1c8e9c62, 353 /* XFER_UDMA_2 */ 0x1c929c62, 354 /* XFER_UDMA_1 */ 0x1c9a9c62, 355 /* XFER_UDMA_0 */ 0x1c829c62, 356 357 /* XFER_MW_DMA_2 */ 0x2c829c62, 358 /* XFER_MW_DMA_1 */ 0x2c829c66, 359 /* XFER_MW_DMA_0 */ 0x2c829d2e, 360 361 /* XFER_PIO_4 */ 0x0c829c62, 362 /* XFER_PIO_3 */ 0x0c829c84, 363 /* XFER_PIO_2 */ 0x0c829ca6, 364 /* XFER_PIO_1 */ 0x0d029d26, 365 /* XFER_PIO_0 */ 0x0d029d5e 366}; 367#else 368/* 369 * The following are the new timing tables with PIO mode data/taskfile transfer 370 * overclocking fixed... 371 */ 372 373/* This table is taken from the HPT370 data manual rev. 1.02 */ 374static u32 thirty_three_base_hpt37x[] = { 375 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */ 376 /* XFER_UDMA_5 */ 0x16455031, 377 /* XFER_UDMA_4 */ 0x16455031, 378 /* XFER_UDMA_3 */ 0x166d5031, 379 /* XFER_UDMA_2 */ 0x16495031, 380 /* XFER_UDMA_1 */ 0x164d5033, 381 /* XFER_UDMA_0 */ 0x16515097, 382 383 /* XFER_MW_DMA_2 */ 0x26515031, 384 /* XFER_MW_DMA_1 */ 0x26515033, 385 /* XFER_MW_DMA_0 */ 0x26515097, 386 387 /* XFER_PIO_4 */ 0x06515021, 388 /* XFER_PIO_3 */ 0x06515022, 389 /* XFER_PIO_2 */ 0x06515033, 390 /* XFER_PIO_1 */ 0x06915065, 391 /* XFER_PIO_0 */ 0x06d1508a 392}; 393 394static u32 fifty_base_hpt37x[] = { 395 /* XFER_UDMA_6 */ 0x1a861842, 396 /* XFER_UDMA_5 */ 0x1a861842, 397 /* XFER_UDMA_4 */ 0x1aae1842, 398 /* XFER_UDMA_3 */ 0x1a8e1842, 399 /* XFER_UDMA_2 */ 0x1a0e1842, 400 /* XFER_UDMA_1 */ 0x1a161854, 401 /* XFER_UDMA_0 */ 0x1a1a18ea, 402 403 /* XFER_MW_DMA_2 */ 0x2a821842, 404 /* XFER_MW_DMA_1 */ 0x2a821854, 405 /* XFER_MW_DMA_0 */ 0x2a8218ea, 406 407 /* XFER_PIO_4 */ 0x0a821842, 408 /* XFER_PIO_3 */ 0x0a821843, 409 /* XFER_PIO_2 */ 0x0a821855, 410 /* XFER_PIO_1 */ 0x0ac218a8, 411 /* XFER_PIO_0 */ 0x0b02190c 412}; 413 414static u32 sixty_six_base_hpt37x[] = { 415 /* XFER_UDMA_6 */ 0x1c86fe62, 416 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */ 417 /* XFER_UDMA_4 */ 0x1c8afe62, 418 /* XFER_UDMA_3 */ 0x1c8efe62, 419 /* XFER_UDMA_2 */ 0x1c92fe62, 420 /* XFER_UDMA_1 */ 0x1c9afe62, 421 /* XFER_UDMA_0 */ 0x1c82fe62, 422 423 /* XFER_MW_DMA_2 */ 0x2c82fe62, 424 /* XFER_MW_DMA_1 */ 0x2c82fe66, 425 /* XFER_MW_DMA_0 */ 0x2c82ff2e, 426 427 /* XFER_PIO_4 */ 0x0c82fe62, 428 /* XFER_PIO_3 */ 0x0c82fe84, 429 /* XFER_PIO_2 */ 0x0c82fea6, 430 /* XFER_PIO_1 */ 0x0d02ff26, 431 /* XFER_PIO_0 */ 0x0d42ff7f 432}; 433#endif 434 435#define HPT366_DEBUG_DRIVE_INFO 0 436#define HPT371_ALLOW_ATA133_6 1 437#define HPT302_ALLOW_ATA133_6 1 438#define HPT372_ALLOW_ATA133_6 1 439#define HPT370_ALLOW_ATA100_5 0 440#define HPT366_ALLOW_ATA66_4 1 441#define HPT366_ALLOW_ATA66_3 1 442#define HPT366_MAX_DEVS 8 443 444/* Supported ATA clock frequencies */ 445enum ata_clock { 446 ATA_CLOCK_25MHZ, 447 ATA_CLOCK_33MHZ, 448 ATA_CLOCK_40MHZ, 449 ATA_CLOCK_50MHZ, 450 ATA_CLOCK_66MHZ, 451 NUM_ATA_CLOCKS 452}; 453 454struct hpt_timings { 455 u32 pio_mask; 456 u32 dma_mask; 457 u32 ultra_mask; 458 u32 *clock_table[NUM_ATA_CLOCKS]; 459}; 460 461/* 462 * Hold all the HighPoint chip information in one place. 463 */ 464 465struct hpt_info { 466 char *chip_name; /* Chip name */ 467 u8 chip_type; /* Chip type */ 468 u8 udma_mask; /* Allowed UltraDMA modes mask. */ 469 u8 dpll_clk; /* DPLL clock in MHz */ 470 u8 pci_clk; /* PCI clock in MHz */ 471 struct hpt_timings *timings; /* Chipset timing data */ 472 u8 clock; /* ATA clock selected */ 473}; 474 475/* Supported HighPoint chips */ 476enum { 477 HPT36x, 478 HPT370, 479 HPT370A, 480 HPT374, 481 HPT372, 482 HPT372A, 483 HPT302, 484 HPT371, 485 HPT372N, 486 HPT302N, 487 HPT371N 488}; 489 490static struct hpt_timings hpt36x_timings = { 491 .pio_mask = 0xc1f8ffff, 492 .dma_mask = 0x303800ff, 493 .ultra_mask = 0x30070000, 494 .clock_table = { 495 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x, 496 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x, 497 [ATA_CLOCK_40MHZ] = forty_base_hpt36x, 498 [ATA_CLOCK_50MHZ] = NULL, 499 [ATA_CLOCK_66MHZ] = NULL 500 } 501}; 502 503static struct hpt_timings hpt37x_timings = { 504 .pio_mask = 0xcfc3ffff, 505 .dma_mask = 0x31c001ff, 506 .ultra_mask = 0x303c0000, 507 .clock_table = { 508 [ATA_CLOCK_25MHZ] = NULL, 509 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x, 510 [ATA_CLOCK_40MHZ] = NULL, 511 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x, 512 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x 513 } 514}; 515 516static const struct hpt_info hpt36x __devinitdata = { 517 .chip_name = "HPT36x", 518 .chip_type = HPT36x, 519 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2, 520 .dpll_clk = 0, /* no DPLL */ 521 .timings = &hpt36x_timings 522}; 523 524static const struct hpt_info hpt370 __devinitdata = { 525 .chip_name = "HPT370", 526 .chip_type = HPT370, 527 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, 528 .dpll_clk = 48, 529 .timings = &hpt37x_timings 530}; 531 532static const struct hpt_info hpt370a __devinitdata = { 533 .chip_name = "HPT370A", 534 .chip_type = HPT370A, 535 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, 536 .dpll_clk = 48, 537 .timings = &hpt37x_timings 538}; 539 540static const struct hpt_info hpt374 __devinitdata = { 541 .chip_name = "HPT374", 542 .chip_type = HPT374, 543 .udma_mask = ATA_UDMA5, 544 .dpll_clk = 48, 545 .timings = &hpt37x_timings 546}; 547 548static const struct hpt_info hpt372 __devinitdata = { 549 .chip_name = "HPT372", 550 .chip_type = HPT372, 551 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 552 .dpll_clk = 55, 553 .timings = &hpt37x_timings 554}; 555 556static const struct hpt_info hpt372a __devinitdata = { 557 .chip_name = "HPT372A", 558 .chip_type = HPT372A, 559 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 560 .dpll_clk = 66, 561 .timings = &hpt37x_timings 562}; 563 564static const struct hpt_info hpt302 __devinitdata = { 565 .chip_name = "HPT302", 566 .chip_type = HPT302, 567 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 568 .dpll_clk = 66, 569 .timings = &hpt37x_timings 570}; 571 572static const struct hpt_info hpt371 __devinitdata = { 573 .chip_name = "HPT371", 574 .chip_type = HPT371, 575 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 576 .dpll_clk = 66, 577 .timings = &hpt37x_timings 578}; 579 580static const struct hpt_info hpt372n __devinitdata = { 581 .chip_name = "HPT372N", 582 .chip_type = HPT372N, 583 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 584 .dpll_clk = 77, 585 .timings = &hpt37x_timings 586}; 587 588static const struct hpt_info hpt302n __devinitdata = { 589 .chip_name = "HPT302N", 590 .chip_type = HPT302N, 591 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 592 .dpll_clk = 77, 593 .timings = &hpt37x_timings 594}; 595 596static const struct hpt_info hpt371n __devinitdata = { 597 .chip_name = "HPT371N", 598 .chip_type = HPT371N, 599 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 600 .dpll_clk = 77, 601 .timings = &hpt37x_timings 602}; 603 604static int check_in_drive_list(ide_drive_t *drive, const char **list) 605{ 606 char *m = (char *)&drive->id[ATA_ID_PROD]; 607 608 while (*list) 609 if (!strcmp(*list++, m)) 610 return 1; 611 return 0; 612} 613 614static struct hpt_info *hpt3xx_get_info(struct device *dev) 615{ 616 struct ide_host *host = dev_get_drvdata(dev); 617 struct hpt_info *info = (struct hpt_info *)host->host_priv; 618 619 return dev == host->dev[1] ? info + 1 : info; 620} 621 622/* 623 * The Marvell bridge chips used on the HighPoint SATA cards do not seem 624 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... 625 */ 626 627static u8 hpt3xx_udma_filter(ide_drive_t *drive) 628{ 629 ide_hwif_t *hwif = drive->hwif; 630 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 631 u8 mask = hwif->ultra_mask; 632 633 switch (info->chip_type) { 634 case HPT36x: 635 if (!HPT366_ALLOW_ATA66_4 || 636 check_in_drive_list(drive, bad_ata66_4)) 637 mask = ATA_UDMA3; 638 639 if (!HPT366_ALLOW_ATA66_3 || 640 check_in_drive_list(drive, bad_ata66_3)) 641 mask = ATA_UDMA2; 642 break; 643 case HPT370: 644 if (!HPT370_ALLOW_ATA100_5 || 645 check_in_drive_list(drive, bad_ata100_5)) 646 mask = ATA_UDMA4; 647 break; 648 case HPT370A: 649 if (!HPT370_ALLOW_ATA100_5 || 650 check_in_drive_list(drive, bad_ata100_5)) 651 return ATA_UDMA4; 652 case HPT372 : 653 case HPT372A: 654 case HPT372N: 655 case HPT374 : 656 if (ata_id_is_sata(drive->id)) 657 mask &= ~0x0e; 658 /* Fall thru */ 659 default: 660 return mask; 661 } 662 663 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask; 664} 665 666static u8 hpt3xx_mdma_filter(ide_drive_t *drive) 667{ 668 ide_hwif_t *hwif = drive->hwif; 669 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 670 671 switch (info->chip_type) { 672 case HPT372 : 673 case HPT372A: 674 case HPT372N: 675 case HPT374 : 676 if (ata_id_is_sata(drive->id)) 677 return 0x00; 678 /* Fall thru */ 679 default: 680 return 0x07; 681 } 682} 683 684static u32 get_speed_setting(u8 speed, struct hpt_info *info) 685{ 686 int i; 687 688 /* 689 * Lookup the transfer mode table to get the index into 690 * the timing table. 691 * 692 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used. 693 */ 694 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) 695 if (xfer_speeds[i] == speed) 696 break; 697 698 return info->timings->clock_table[info->clock][i]; 699} 700 701static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed) 702{ 703 ide_hwif_t *hwif = drive->hwif; 704 struct pci_dev *dev = to_pci_dev(hwif->dev); 705 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 706 struct hpt_timings *t = info->timings; 707 u8 itr_addr = 0x40 + (drive->dn * 4); 708 u32 old_itr = 0; 709 u32 new_itr = get_speed_setting(speed, info); 710 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask : 711 (speed < XFER_UDMA_0 ? t->dma_mask : 712 t->ultra_mask); 713 714 pci_read_config_dword(dev, itr_addr, &old_itr); 715 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask); 716 /* 717 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) 718 * to avoid problems handling I/O errors later 719 */ 720 new_itr &= ~0xc0000000; 721 722 pci_write_config_dword(dev, itr_addr, new_itr); 723} 724 725static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio) 726{ 727 hpt3xx_set_mode(drive, XFER_PIO_0 + pio); 728} 729 730static void hpt3xx_quirkproc(ide_drive_t *drive) 731{ 732 char *m = (char *)&drive->id[ATA_ID_PROD]; 733 const char **list = quirk_drives; 734 735 while (*list) 736 if (strstr(m, *list++)) { 737 drive->quirk_list = 1; 738 return; 739 } 740 741 drive->quirk_list = 0; 742} 743 744static void hpt3xx_maskproc(ide_drive_t *drive, int mask) 745{ 746 ide_hwif_t *hwif = drive->hwif; 747 struct pci_dev *dev = to_pci_dev(hwif->dev); 748 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 749 750 if (drive->quirk_list == 0) 751 return; 752 753 if (info->chip_type >= HPT370) { 754 u8 scr1 = 0; 755 756 pci_read_config_byte(dev, 0x5a, &scr1); 757 if (((scr1 & 0x10) >> 4) != mask) { 758 if (mask) 759 scr1 |= 0x10; 760 else 761 scr1 &= ~0x10; 762 pci_write_config_byte(dev, 0x5a, scr1); 763 } 764 } else if (mask) 765 disable_irq(hwif->irq); 766 else 767 enable_irq(hwif->irq); 768} 769 770/* 771 * This is specific to the HPT366 UDMA chipset 772 * by HighPoint|Triones Technologies, Inc. 773 */ 774static void hpt366_dma_lost_irq(ide_drive_t *drive) 775{ 776 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 777 u8 mcr1 = 0, mcr3 = 0, scr1 = 0; 778 779 pci_read_config_byte(dev, 0x50, &mcr1); 780 pci_read_config_byte(dev, 0x52, &mcr3); 781 pci_read_config_byte(dev, 0x5a, &scr1); 782 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", 783 drive->name, __func__, mcr1, mcr3, scr1); 784 if (scr1 & 0x10) 785 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); 786 ide_dma_lost_irq(drive); 787} 788 789static void hpt370_clear_engine(ide_drive_t *drive) 790{ 791 ide_hwif_t *hwif = drive->hwif; 792 struct pci_dev *dev = to_pci_dev(hwif->dev); 793 794 pci_write_config_byte(dev, hwif->select_data, 0x37); 795 udelay(10); 796} 797 798static void hpt370_irq_timeout(ide_drive_t *drive) 799{ 800 ide_hwif_t *hwif = drive->hwif; 801 struct pci_dev *dev = to_pci_dev(hwif->dev); 802 u16 bfifo = 0; 803 u8 dma_cmd; 804 805 pci_read_config_word(dev, hwif->select_data + 2, &bfifo); 806 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); 807 808 /* get DMA command mode */ 809 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 810 /* stop DMA */ 811 outb(dma_cmd & ~0x1, hwif->dma_base + ATA_DMA_CMD); 812 hpt370_clear_engine(drive); 813} 814 815static void hpt370_dma_start(ide_drive_t *drive) 816{ 817#ifdef HPT_RESET_STATE_ENGINE 818 hpt370_clear_engine(drive); 819#endif 820 ide_dma_start(drive); 821} 822 823static int hpt370_dma_end(ide_drive_t *drive) 824{ 825 ide_hwif_t *hwif = drive->hwif; 826 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 827 828 if (dma_stat & 0x01) { 829 /* wait a little */ 830 udelay(20); 831 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 832 if (dma_stat & 0x01) 833 hpt370_irq_timeout(drive); 834 } 835 return ide_dma_end(drive); 836} 837 838/* returns 1 if DMA IRQ issued, 0 otherwise */ 839static int hpt374_dma_test_irq(ide_drive_t *drive) 840{ 841 ide_hwif_t *hwif = drive->hwif; 842 struct pci_dev *dev = to_pci_dev(hwif->dev); 843 u16 bfifo = 0; 844 u8 dma_stat; 845 846 pci_read_config_word(dev, hwif->select_data + 2, &bfifo); 847 if (bfifo & 0x1FF) { 848// printk("%s: %d bytes in FIFO\n", drive->name, bfifo); 849 return 0; 850 } 851 852 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 853 /* return 1 if INTR asserted */ 854 if (dma_stat & 4) 855 return 1; 856 857 return 0; 858} 859 860static int hpt374_dma_end(ide_drive_t *drive) 861{ 862 ide_hwif_t *hwif = drive->hwif; 863 struct pci_dev *dev = to_pci_dev(hwif->dev); 864 u8 mcr = 0, mcr_addr = hwif->select_data; 865 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; 866 867 pci_read_config_byte(dev, 0x6a, &bwsr); 868 pci_read_config_byte(dev, mcr_addr, &mcr); 869 if (bwsr & mask) 870 pci_write_config_byte(dev, mcr_addr, mcr | 0x30); 871 return ide_dma_end(drive); 872} 873 874/** 875 * hpt3xxn_set_clock - perform clock switching dance 876 * @hwif: hwif to switch 877 * @mode: clocking mode (0x21 for write, 0x23 otherwise) 878 * 879 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. 880 */ 881 882static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) 883{ 884 unsigned long base = hwif->extra_base; 885 u8 scr2 = inb(base + 0x6b); 886 887 if ((scr2 & 0x7f) == mode) 888 return; 889 890 /* Tristate the bus */ 891 outb(0x80, base + 0x63); 892 outb(0x80, base + 0x67); 893 894 /* Switch clock and reset channels */ 895 outb(mode, base + 0x6b); 896 outb(0xc0, base + 0x69); 897 898 /* 899 * Reset the state machines. 900 * NOTE: avoid accidentally enabling the disabled channels. 901 */ 902 outb(inb(base + 0x60) | 0x32, base + 0x60); 903 outb(inb(base + 0x64) | 0x32, base + 0x64); 904 905 /* Complete reset */ 906 outb(0x00, base + 0x69); 907 908 /* Reconnect channels to bus */ 909 outb(0x00, base + 0x63); 910 outb(0x00, base + 0x67); 911} 912 913/** 914 * hpt3xxn_rw_disk - prepare for I/O 915 * @drive: drive for command 916 * @rq: block request structure 917 * 918 * This is called when a disk I/O is issued to HPT3xxN. 919 * We need it because of the clock switching. 920 */ 921 922static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) 923{ 924 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21); 925} 926 927/** 928 * hpt37x_calibrate_dpll - calibrate the DPLL 929 * @dev: PCI device 930 * 931 * Perform a calibration cycle on the DPLL. 932 * Returns 1 if this succeeds 933 */ 934static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high) 935{ 936 u32 dpll = (f_high << 16) | f_low | 0x100; 937 u8 scr2; 938 int i; 939 940 pci_write_config_dword(dev, 0x5c, dpll); 941 942 /* Wait for oscillator ready */ 943 for(i = 0; i < 0x5000; ++i) { 944 udelay(50); 945 pci_read_config_byte(dev, 0x5b, &scr2); 946 if (scr2 & 0x80) 947 break; 948 } 949 /* See if it stays ready (we'll just bail out if it's not yet) */ 950 for(i = 0; i < 0x1000; ++i) { 951 pci_read_config_byte(dev, 0x5b, &scr2); 952 /* DPLL destabilized? */ 953 if(!(scr2 & 0x80)) 954 return 0; 955 } 956 /* Turn off tuning, we have the DPLL set */ 957 pci_read_config_dword (dev, 0x5c, &dpll); 958 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); 959 return 1; 960} 961 962static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr) 963{ 964 struct ide_host *host = pci_get_drvdata(dev); 965 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]); 966 u8 chip_type = info->chip_type; 967 u8 new_mcr, old_mcr = 0; 968 969 /* 970 * Disable the "fast interrupt" prediction. Don't hold off 971 * on interrupts. (== 0x01 despite what the docs say) 972 */ 973 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr); 974 975 if (chip_type >= HPT374) 976 new_mcr = old_mcr & ~0x07; 977 else if (chip_type >= HPT370) { 978 new_mcr = old_mcr; 979 new_mcr &= ~0x02; 980#ifdef HPT_DELAY_INTERRUPT 981 new_mcr &= ~0x01; 982#else 983 new_mcr |= 0x01; 984#endif 985 } else /* HPT366 and HPT368 */ 986 new_mcr = old_mcr & ~0x80; 987 988 if (new_mcr != old_mcr) 989 pci_write_config_byte(dev, mcr_addr + 1, new_mcr); 990} 991 992static int init_chipset_hpt366(struct pci_dev *dev) 993{ 994 unsigned long io_base = pci_resource_start(dev, 4); 995 struct hpt_info *info = hpt3xx_get_info(&dev->dev); 996 const char *name = DRV_NAME; 997 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */ 998 u8 chip_type; 999 enum ata_clock clock; 1000 1001 chip_type = info->chip_type; 1002 1003 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 1004 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 1005 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 1006 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 1007 1008 /* 1009 * First, try to estimate the PCI clock frequency... 1010 */ 1011 if (chip_type >= HPT370) { 1012 u8 scr1 = 0; 1013 u16 f_cnt = 0; 1014 u32 temp = 0; 1015 1016 /* Interrupt force enable. */ 1017 pci_read_config_byte(dev, 0x5a, &scr1); 1018 if (scr1 & 0x10) 1019 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); 1020 1021 /* 1022 * HighPoint does this for HPT372A. 1023 * NOTE: This register is only writeable via I/O space. 1024 */ 1025 if (chip_type == HPT372A) 1026 outb(0x0e, io_base + 0x9c); 1027 1028 /* 1029 * Default to PCI clock. Make sure MA15/16 are set to output 1030 * to prevent drives having problems with 40-pin cables. 1031 */ 1032 pci_write_config_byte(dev, 0x5b, 0x23); 1033 1034 /* 1035 * We'll have to read f_CNT value in order to determine 1036 * the PCI clock frequency according to the following ratio: 1037 * 1038 * f_CNT = Fpci * 192 / Fdpll 1039 * 1040 * First try reading the register in which the HighPoint BIOS 1041 * saves f_CNT value before reprogramming the DPLL from its 1042 * default setting (which differs for the various chips). 1043 * 1044 * NOTE: This register is only accessible via I/O space; 1045 * HPT374 BIOS only saves it for the function 0, so we have to 1046 * always read it from there -- no need to check the result of 1047 * pci_get_slot() for the function 0 as the whole device has 1048 * been already "pinned" (via function 1) in init_setup_hpt374() 1049 */ 1050 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { 1051 struct pci_dev *dev1 = pci_get_slot(dev->bus, 1052 dev->devfn - 1); 1053 unsigned long io_base = pci_resource_start(dev1, 4); 1054 1055 temp = inl(io_base + 0x90); 1056 pci_dev_put(dev1); 1057 } else 1058 temp = inl(io_base + 0x90); 1059 1060 /* 1061 * In case the signature check fails, we'll have to 1062 * resort to reading the f_CNT register itself in hopes 1063 * that nobody has touched the DPLL yet... 1064 */ 1065 if ((temp & 0xFFFFF000) != 0xABCDE000) { 1066 int i; 1067 1068 printk(KERN_WARNING "%s %s: no clock data saved by " 1069 "BIOS\n", name, pci_name(dev)); 1070 1071 /* Calculate the average value of f_CNT. */ 1072 for (temp = i = 0; i < 128; i++) { 1073 pci_read_config_word(dev, 0x78, &f_cnt); 1074 temp += f_cnt & 0x1ff; 1075 mdelay(1); 1076 } 1077 f_cnt = temp / 128; 1078 } else 1079 f_cnt = temp & 0x1ff; 1080 1081 dpll_clk = info->dpll_clk; 1082 pci_clk = (f_cnt * dpll_clk) / 192; 1083 1084 /* Clamp PCI clock to bands. */ 1085 if (pci_clk < 40) 1086 pci_clk = 33; 1087 else if(pci_clk < 45) 1088 pci_clk = 40; 1089 else if(pci_clk < 55) 1090 pci_clk = 50; 1091 else 1092 pci_clk = 66; 1093 1094 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, " 1095 "assuming %d MHz PCI\n", name, pci_name(dev), 1096 dpll_clk, f_cnt, pci_clk); 1097 } else { 1098 u32 itr1 = 0; 1099 1100 pci_read_config_dword(dev, 0x40, &itr1); 1101 1102 /* Detect PCI clock by looking at cmd_high_time. */ 1103 switch((itr1 >> 8) & 0x07) { 1104 case 0x09: 1105 pci_clk = 40; 1106 break; 1107 case 0x05: 1108 pci_clk = 25; 1109 break; 1110 case 0x07: 1111 default: 1112 pci_clk = 33; 1113 break; 1114 } 1115 } 1116 1117 /* Let's assume we'll use PCI clock for the ATA clock... */ 1118 switch (pci_clk) { 1119 case 25: 1120 clock = ATA_CLOCK_25MHZ; 1121 break; 1122 case 33: 1123 default: 1124 clock = ATA_CLOCK_33MHZ; 1125 break; 1126 case 40: 1127 clock = ATA_CLOCK_40MHZ; 1128 break; 1129 case 50: 1130 clock = ATA_CLOCK_50MHZ; 1131 break; 1132 case 66: 1133 clock = ATA_CLOCK_66MHZ; 1134 break; 1135 } 1136 1137 /* 1138 * Only try the DPLL if we don't have a table for the PCI clock that 1139 * we are running at for HPT370/A, always use it for anything newer... 1140 * 1141 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI. 1142 * We also don't like using the DPLL because this causes glitches 1143 * on PRST-/SRST- when the state engine gets reset... 1144 */ 1145 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) { 1146 u16 f_low, delta = pci_clk < 50 ? 2 : 4; 1147 int adjust; 1148 1149 /* 1150 * Select 66 MHz DPLL clock only if UltraATA/133 mode is 1151 * supported/enabled, use 50 MHz DPLL clock otherwise... 1152 */ 1153 if (info->udma_mask == ATA_UDMA6) { 1154 dpll_clk = 66; 1155 clock = ATA_CLOCK_66MHZ; 1156 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ 1157 dpll_clk = 50; 1158 clock = ATA_CLOCK_50MHZ; 1159 } 1160 1161 if (info->timings->clock_table[clock] == NULL) { 1162 printk(KERN_ERR "%s %s: unknown bus timing!\n", 1163 name, pci_name(dev)); 1164 return -EIO; 1165 } 1166 1167 /* Select the DPLL clock. */ 1168 pci_write_config_byte(dev, 0x5b, 0x21); 1169 1170 /* 1171 * Adjust the DPLL based upon PCI clock, enable it, 1172 * and wait for stabilization... 1173 */ 1174 f_low = (pci_clk * 48) / dpll_clk; 1175 1176 for (adjust = 0; adjust < 8; adjust++) { 1177 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta)) 1178 break; 1179 1180 /* 1181 * See if it'll settle at a fractionally different clock 1182 */ 1183 if (adjust & 1) 1184 f_low -= adjust >> 1; 1185 else 1186 f_low += adjust >> 1; 1187 } 1188 if (adjust == 8) { 1189 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n", 1190 name, pci_name(dev)); 1191 return -EIO; 1192 } 1193 1194 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n", 1195 name, pci_name(dev), dpll_clk); 1196 } else { 1197 /* Mark the fact that we're not using the DPLL. */ 1198 dpll_clk = 0; 1199 1200 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n", 1201 name, pci_name(dev), pci_clk); 1202 } 1203 1204 /* Store the clock frequencies. */ 1205 info->dpll_clk = dpll_clk; 1206 info->pci_clk = pci_clk; 1207 info->clock = clock; 1208 1209 if (chip_type >= HPT370) { 1210 u8 mcr1, mcr4; 1211 1212 /* 1213 * Reset the state engines. 1214 * NOTE: Avoid accidentally enabling the disabled channels. 1215 */ 1216 pci_read_config_byte (dev, 0x50, &mcr1); 1217 pci_read_config_byte (dev, 0x54, &mcr4); 1218 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32)); 1219 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32)); 1220 udelay(100); 1221 } 1222 1223 /* 1224 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in 1225 * the MISC. register to stretch the UltraDMA Tss timing. 1226 * NOTE: This register is only writeable via I/O space. 1227 */ 1228 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ) 1229 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c); 1230 1231 hpt3xx_disable_fast_irq(dev, 0x50); 1232 hpt3xx_disable_fast_irq(dev, 0x54); 1233 1234 return 0; 1235} 1236 1237static u8 hpt3xx_cable_detect(ide_hwif_t *hwif) 1238{ 1239 struct pci_dev *dev = to_pci_dev(hwif->dev); 1240 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 1241 u8 chip_type = info->chip_type; 1242 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02; 1243 1244 /* 1245 * The HPT37x uses the CBLID pins as outputs for MA15/MA16 1246 * address lines to access an external EEPROM. To read valid 1247 * cable detect state the pins must be enabled as inputs. 1248 */ 1249 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { 1250 /* 1251 * HPT374 PCI function 1 1252 * - set bit 15 of reg 0x52 to enable TCBLID as input 1253 * - set bit 15 of reg 0x56 to enable FCBLID as input 1254 */ 1255 u8 mcr_addr = hwif->select_data + 2; 1256 u16 mcr; 1257 1258 pci_read_config_word(dev, mcr_addr, &mcr); 1259 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); 1260 /* now read cable id register */ 1261 pci_read_config_byte(dev, 0x5a, &scr1); 1262 pci_write_config_word(dev, mcr_addr, mcr); 1263 } else if (chip_type >= HPT370) { 1264 /* 1265 * HPT370/372 and 374 pcifn 0 1266 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs 1267 */ 1268 u8 scr2 = 0; 1269 1270 pci_read_config_byte(dev, 0x5b, &scr2); 1271 pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); 1272 /* now read cable id register */ 1273 pci_read_config_byte(dev, 0x5a, &scr1); 1274 pci_write_config_byte(dev, 0x5b, scr2); 1275 } else 1276 pci_read_config_byte(dev, 0x5a, &scr1); 1277 1278 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; 1279} 1280 1281static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) 1282{ 1283 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 1284 u8 chip_type = info->chip_type; 1285 1286 /* Cache the channel's MISC. control registers' offset */ 1287 hwif->select_data = hwif->channel ? 0x54 : 0x50; 1288 1289 /* 1290 * HPT3xxN chips have some complications: 1291 * 1292 * - on 33 MHz PCI we must clock switch 1293 * - on 66 MHz PCI we must NOT use the PCI clock 1294 */ 1295 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) { 1296 /* 1297 * Clock is shared between the channels, 1298 * so we'll have to serialize them... :-( 1299 */ 1300 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE; 1301 hwif->rw_disk = &hpt3xxn_rw_disk; 1302 } 1303} 1304 1305static int __devinit init_dma_hpt366(ide_hwif_t *hwif, 1306 const struct ide_port_info *d) 1307{ 1308 struct pci_dev *dev = to_pci_dev(hwif->dev); 1309 unsigned long flags, base = ide_pci_dma_base(hwif, d); 1310 u8 dma_old, dma_new, masterdma = 0, slavedma = 0; 1311 1312 if (base == 0) 1313 return -1; 1314 1315 hwif->dma_base = base; 1316 1317 if (ide_pci_check_simplex(hwif, d) < 0) 1318 return -1; 1319 1320 if (ide_pci_set_master(dev, d->name) < 0) 1321 return -1; 1322 1323 dma_old = inb(base + 2); 1324 1325 local_irq_save(flags); 1326 1327 dma_new = dma_old; 1328 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); 1329 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); 1330 1331 if (masterdma & 0x30) dma_new |= 0x20; 1332 if ( slavedma & 0x30) dma_new |= 0x40; 1333 if (dma_new != dma_old) 1334 outb(dma_new, base + 2); 1335 1336 local_irq_restore(flags); 1337 1338 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", 1339 hwif->name, base, base + 7); 1340 1341 hwif->extra_base = base + (hwif->channel ? 8 : 16); 1342 1343 if (ide_allocate_dma_engine(hwif)) 1344 return -1; 1345 1346 return 0; 1347} 1348 1349static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2) 1350{ 1351 if (dev2->irq != dev->irq) { 1352 /* FIXME: we need a core pci_set_interrupt() */ 1353 dev2->irq = dev->irq; 1354 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt " 1355 "fixed\n", pci_name(dev2)); 1356 } 1357} 1358 1359static void __devinit hpt371_init(struct pci_dev *dev) 1360{ 1361 u8 mcr1 = 0; 1362 1363 /* 1364 * HPT371 chips physically have only one channel, the secondary one, 1365 * but the primary channel registers do exist! Go figure... 1366 * So, we manually disable the non-existing channel here 1367 * (if the BIOS hasn't done this already). 1368 */ 1369 pci_read_config_byte(dev, 0x50, &mcr1); 1370 if (mcr1 & 0x04) 1371 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); 1372} 1373 1374static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2) 1375{ 1376 u8 mcr1 = 0, pin1 = 0, pin2 = 0; 1377 1378 /* 1379 * Now we'll have to force both channels enabled if 1380 * at least one of them has been enabled by BIOS... 1381 */ 1382 pci_read_config_byte(dev, 0x50, &mcr1); 1383 if (mcr1 & 0x30) 1384 pci_write_config_byte(dev, 0x50, mcr1 | 0x30); 1385 1386 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); 1387 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); 1388 1389 if (pin1 != pin2 && dev->irq == dev2->irq) { 1390 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, " 1391 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2); 1392 return 1; 1393 } 1394 1395 return 0; 1396} 1397 1398#define IDE_HFLAGS_HPT3XX \ 1399 (IDE_HFLAG_NO_ATAPI_DMA | \ 1400 IDE_HFLAG_OFF_BOARD) 1401 1402static const struct ide_port_ops hpt3xx_port_ops = { 1403 .set_pio_mode = hpt3xx_set_pio_mode, 1404 .set_dma_mode = hpt3xx_set_mode, 1405 .quirkproc = hpt3xx_quirkproc, 1406 .maskproc = hpt3xx_maskproc, 1407 .mdma_filter = hpt3xx_mdma_filter, 1408 .udma_filter = hpt3xx_udma_filter, 1409 .cable_detect = hpt3xx_cable_detect, 1410}; 1411 1412static const struct ide_dma_ops hpt37x_dma_ops = { 1413 .dma_host_set = ide_dma_host_set, 1414 .dma_setup = ide_dma_setup, 1415 .dma_start = ide_dma_start, 1416 .dma_end = hpt374_dma_end, 1417 .dma_test_irq = hpt374_dma_test_irq, 1418 .dma_lost_irq = ide_dma_lost_irq, 1419 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1420 .dma_sff_read_status = ide_dma_sff_read_status, 1421}; 1422 1423static const struct ide_dma_ops hpt370_dma_ops = { 1424 .dma_host_set = ide_dma_host_set, 1425 .dma_setup = ide_dma_setup, 1426 .dma_start = hpt370_dma_start, 1427 .dma_end = hpt370_dma_end, 1428 .dma_test_irq = ide_dma_test_irq, 1429 .dma_lost_irq = ide_dma_lost_irq, 1430 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1431 .dma_clear = hpt370_irq_timeout, 1432 .dma_sff_read_status = ide_dma_sff_read_status, 1433}; 1434 1435static const struct ide_dma_ops hpt36x_dma_ops = { 1436 .dma_host_set = ide_dma_host_set, 1437 .dma_setup = ide_dma_setup, 1438 .dma_start = ide_dma_start, 1439 .dma_end = ide_dma_end, 1440 .dma_test_irq = ide_dma_test_irq, 1441 .dma_lost_irq = hpt366_dma_lost_irq, 1442 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1443 .dma_sff_read_status = ide_dma_sff_read_status, 1444}; 1445 1446static const struct ide_port_info hpt366_chipsets[] __devinitdata = { 1447 { /* 0: HPT36x */ 1448 .name = DRV_NAME, 1449 .init_chipset = init_chipset_hpt366, 1450 .init_hwif = init_hwif_hpt366, 1451 .init_dma = init_dma_hpt366, 1452 /* 1453 * HPT36x chips have one channel per function and have 1454 * both channel enable bits located differently and visible 1455 * to both functions -- really stupid design decision... :-( 1456 * Bit 4 is for the primary channel, bit 5 for the secondary. 1457 */ 1458 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}}, 1459 .port_ops = &hpt3xx_port_ops, 1460 .dma_ops = &hpt36x_dma_ops, 1461 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE, 1462 .pio_mask = ATA_PIO4, 1463 .mwdma_mask = ATA_MWDMA2, 1464 }, 1465 { /* 1: HPT3xx */ 1466 .name = DRV_NAME, 1467 .init_chipset = init_chipset_hpt366, 1468 .init_hwif = init_hwif_hpt366, 1469 .init_dma = init_dma_hpt366, 1470 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1471 .port_ops = &hpt3xx_port_ops, 1472 .dma_ops = &hpt37x_dma_ops, 1473 .host_flags = IDE_HFLAGS_HPT3XX, 1474 .pio_mask = ATA_PIO4, 1475 .mwdma_mask = ATA_MWDMA2, 1476 } 1477}; 1478 1479/** 1480 * hpt366_init_one - called when an HPT366 is found 1481 * @dev: the hpt366 device 1482 * @id: the matching pci id 1483 * 1484 * Called when the PCI registration layer (or the IDE initialization) 1485 * finds a device matching our IDE device tables. 1486 */ 1487static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) 1488{ 1489 const struct hpt_info *info = NULL; 1490 struct hpt_info *dyn_info; 1491 struct pci_dev *dev2 = NULL; 1492 struct ide_port_info d; 1493 u8 idx = id->driver_data; 1494 u8 rev = dev->revision; 1495 int ret; 1496 1497 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1)) 1498 return -ENODEV; 1499 1500 switch (idx) { 1501 case 0: 1502 if (rev < 3) 1503 info = &hpt36x; 1504 else { 1505 switch (min_t(u8, rev, 6)) { 1506 case 3: info = &hpt370; break; 1507 case 4: info = &hpt370a; break; 1508 case 5: info = &hpt372; break; 1509 case 6: info = &hpt372n; break; 1510 } 1511 idx++; 1512 } 1513 break; 1514 case 1: 1515 info = (rev > 1) ? &hpt372n : &hpt372a; 1516 break; 1517 case 2: 1518 info = (rev > 1) ? &hpt302n : &hpt302; 1519 break; 1520 case 3: 1521 hpt371_init(dev); 1522 info = (rev > 1) ? &hpt371n : &hpt371; 1523 break; 1524 case 4: 1525 info = &hpt374; 1526 break; 1527 case 5: 1528 info = &hpt372n; 1529 break; 1530 } 1531 1532 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name); 1533 1534 d = hpt366_chipsets[min_t(u8, idx, 1)]; 1535 1536 d.udma_mask = info->udma_mask; 1537 1538 /* fixup ->dma_ops for HPT370/HPT370A */ 1539 if (info == &hpt370 || info == &hpt370a) 1540 d.dma_ops = &hpt370_dma_ops; 1541 1542 if (info == &hpt36x || info == &hpt374) 1543 dev2 = pci_get_slot(dev->bus, dev->devfn + 1); 1544 1545 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL); 1546 if (dyn_info == NULL) { 1547 printk(KERN_ERR "%s %s: out of memory!\n", 1548 d.name, pci_name(dev)); 1549 pci_dev_put(dev2); 1550 return -ENOMEM; 1551 } 1552 1553 /* 1554 * Copy everything from a static "template" structure 1555 * to just allocated per-chip hpt_info structure. 1556 */ 1557 memcpy(dyn_info, info, sizeof(*dyn_info)); 1558 1559 if (dev2) { 1560 memcpy(dyn_info + 1, info, sizeof(*dyn_info)); 1561 1562 if (info == &hpt374) 1563 hpt374_init(dev, dev2); 1564 else { 1565 if (hpt36x_init(dev, dev2)) 1566 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE; 1567 } 1568 1569 ret = ide_pci_init_two(dev, dev2, &d, dyn_info); 1570 if (ret < 0) { 1571 pci_dev_put(dev2); 1572 kfree(dyn_info); 1573 } 1574 return ret; 1575 } 1576 1577 ret = ide_pci_init_one(dev, &d, dyn_info); 1578 if (ret < 0) 1579 kfree(dyn_info); 1580 1581 return ret; 1582} 1583 1584static void __devexit hpt366_remove(struct pci_dev *dev) 1585{ 1586 struct ide_host *host = pci_get_drvdata(dev); 1587 struct ide_info *info = host->host_priv; 1588 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL; 1589 1590 ide_pci_remove(dev); 1591 pci_dev_put(dev2); 1592 kfree(info); 1593} 1594 1595static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = { 1596 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 }, 1597 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 }, 1598 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 }, 1599 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 }, 1600 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 }, 1601 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 }, 1602 { 0, }, 1603}; 1604MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl); 1605 1606static struct pci_driver hpt366_pci_driver = { 1607 .name = "HPT366_IDE", 1608 .id_table = hpt366_pci_tbl, 1609 .probe = hpt366_init_one, 1610 .remove = __devexit_p(hpt366_remove), 1611 .suspend = ide_pci_suspend, 1612 .resume = ide_pci_resume, 1613}; 1614 1615static int __init hpt366_ide_init(void) 1616{ 1617 return ide_pci_register_driver(&hpt366_pci_driver); 1618} 1619 1620static void __exit hpt366_ide_exit(void) 1621{ 1622 pci_unregister_driver(&hpt366_pci_driver); 1623} 1624 1625module_init(hpt366_ide_init); 1626module_exit(hpt366_ide_exit); 1627 1628MODULE_AUTHOR("Andre Hedrick"); 1629MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE"); 1630MODULE_LICENSE("GPL"); 1631