hpt366.c revision 8776168ca2151850164af1de5565d01f7b8b2c53
1/* 2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 3 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 4 * Portions Copyright (C) 2003 Red Hat Inc 5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz 6 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc. 7 * 8 * Thanks to HighPoint Technologies for their assistance, and hardware. 9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his 10 * donation of an ABit BP6 mainboard, processor, and memory acellerated 11 * development and support. 12 * 13 * 14 * HighPoint has its own drivers (open source except for the RAID part) 15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/. 16 * This may be useful to anyone wanting to work on this driver, however do not 17 * trust them too much since the code tends to become less and less meaningful 18 * as the time passes... :-/ 19 * 20 * Note that final HPT370 support was done by force extraction of GPL. 21 * 22 * - add function for getting/setting power status of drive 23 * - the HPT370's state machine can get confused. reset it before each dma 24 * xfer to prevent that from happening. 25 * - reset state engine whenever we get an error. 26 * - check for busmaster state at end of dma. 27 * - use new highpoint timings. 28 * - detect bus speed using highpoint register. 29 * - use pll if we don't have a clock table. added a 66MHz table that's 30 * just 2x the 33MHz table. 31 * - removed turnaround. NOTE: we never want to switch between pll and 32 * pci clocks as the chip can glitch in those cases. the highpoint 33 * approved workaround slows everything down too much to be useful. in 34 * addition, we would have to serialize access to each chip. 35 * Adrian Sun <a.sun@sun.com> 36 * 37 * add drive timings for 66MHz PCI bus, 38 * fix ATA Cable signal detection, fix incorrect /proc info 39 * add /proc display for per-drive PIO/DMA/UDMA mode and 40 * per-channel ATA-33/66 Cable detect. 41 * Duncan Laurie <void@sun.com> 42 * 43 * fixup /proc output for multiple controllers 44 * Tim Hockin <thockin@sun.com> 45 * 46 * On hpt366: 47 * Reset the hpt366 on error, reset on dma 48 * Fix disabling Fast Interrupt hpt366. 49 * Mike Waychison <crlf@sun.com> 50 * 51 * Added support for 372N clocking and clock switching. The 372N needs 52 * different clocks on read/write. This requires overloading rw_disk and 53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for 54 * keeping me sane. 55 * Alan Cox <alan@lxorguk.ukuu.org.uk> 56 * 57 * - fix the clock turnaround code: it was writing to the wrong ports when 58 * called for the secondary channel, caching the current clock mode per- 59 * channel caused the cached register value to get out of sync with the 60 * actual one, the channels weren't serialized, the turnaround shouldn't 61 * be done on 66 MHz PCI bus 62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used 63 * does not allow for this speed anyway 64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips, 65 * their primary channel is kind of virtual, it isn't tied to any pins) 66 * - fix/remove bad/unused timing tables and use one set of tables for the whole 67 * HPT37x chip family; save space by introducing the separate transfer mode 68 * table in which the mode lookup is done 69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives 70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS; 71 * read it only from the function 0 of HPT374 chips 72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus, 73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead 74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as 75 * they tamper with its fields 76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure 77 * since they may tamper with its fields 78 * - prefix the driver startup messages with the real chip name 79 * - claim the extra 240 bytes of I/O space for all chips 80 * - optimize the UltraDMA filtering and the drive list lookup code 81 * - use pci_get_slot() to get to the function 1 of HPT36x/374 82 * - cache offset of the channel's misc. control registers (MCRs) being used 83 * throughout the driver 84 * - only touch the relevant MCR when detecting the cable type on HPT374's 85 * function 1 86 * - rename all the register related variables consistently 87 * - move all the interrupt twiddling code from the speedproc handlers into 88 * init_hwif_hpt366(), also grouping all the DMA related code together there 89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and 90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings 91 * when setting an UltraDMA mode 92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select 93 * the best possible one 94 * - clean up DMA timeout handling for HPT370 95 * - switch to using the enumeration type to differ between the numerous chip 96 * variants, matching PCI device/revision ID with the chip type early, at the 97 * init_setup stage 98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies, 99 * stop duplicating it for each channel by storing the pointer in the pci_dev 100 * structure: first, at the init_setup stage, point it to a static "template" 101 * with only the chip type and its specific base DPLL frequency, the highest 102 * UltraDMA mode, and the chip settings table pointer filled, then, at the 103 * init_chipset stage, allocate per-chip instance and fill it with the rest 104 * of the necessary information 105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code, 106 * switch to calculating PCI clock frequency based on the chip's base DPLL 107 * frequency 108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on 109 * anything newer than HPT370/A (except HPT374 that is not capable of this 110 * mode according to the manual) 111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(), 112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips; 113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining 114 * the register setting lists into the table indexed by the clock selected 115 * - set the correct hwif->ultra_mask for each individual chip 116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards 117 * - stop resetting HPT370's state machine before each DMA transfer as that has 118 * caused more harm than good 119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com> 120 */ 121 122#include <linux/types.h> 123#include <linux/module.h> 124#include <linux/kernel.h> 125#include <linux/delay.h> 126#include <linux/blkdev.h> 127#include <linux/interrupt.h> 128#include <linux/pci.h> 129#include <linux/init.h> 130#include <linux/ide.h> 131 132#include <asm/uaccess.h> 133#include <asm/io.h> 134 135#define DRV_NAME "hpt366" 136 137/* various tuning parameters */ 138#undef HPT_RESET_STATE_ENGINE 139#undef HPT_DELAY_INTERRUPT 140 141static const char *bad_ata100_5[] = { 142 "IBM-DTLA-307075", 143 "IBM-DTLA-307060", 144 "IBM-DTLA-307045", 145 "IBM-DTLA-307030", 146 "IBM-DTLA-307020", 147 "IBM-DTLA-307015", 148 "IBM-DTLA-305040", 149 "IBM-DTLA-305030", 150 "IBM-DTLA-305020", 151 "IC35L010AVER07-0", 152 "IC35L020AVER07-0", 153 "IC35L030AVER07-0", 154 "IC35L040AVER07-0", 155 "IC35L060AVER07-0", 156 "WDC AC310200R", 157 NULL 158}; 159 160static const char *bad_ata66_4[] = { 161 "IBM-DTLA-307075", 162 "IBM-DTLA-307060", 163 "IBM-DTLA-307045", 164 "IBM-DTLA-307030", 165 "IBM-DTLA-307020", 166 "IBM-DTLA-307015", 167 "IBM-DTLA-305040", 168 "IBM-DTLA-305030", 169 "IBM-DTLA-305020", 170 "IC35L010AVER07-0", 171 "IC35L020AVER07-0", 172 "IC35L030AVER07-0", 173 "IC35L040AVER07-0", 174 "IC35L060AVER07-0", 175 "WDC AC310200R", 176 "MAXTOR STM3320620A", 177 NULL 178}; 179 180static const char *bad_ata66_3[] = { 181 "WDC AC310200R", 182 NULL 183}; 184 185static const char *bad_ata33[] = { 186 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", 187 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 188 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 189 "Maxtor 90510D4", 190 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 191 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 192 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 193 NULL 194}; 195 196static u8 xfer_speeds[] = { 197 XFER_UDMA_6, 198 XFER_UDMA_5, 199 XFER_UDMA_4, 200 XFER_UDMA_3, 201 XFER_UDMA_2, 202 XFER_UDMA_1, 203 XFER_UDMA_0, 204 205 XFER_MW_DMA_2, 206 XFER_MW_DMA_1, 207 XFER_MW_DMA_0, 208 209 XFER_PIO_4, 210 XFER_PIO_3, 211 XFER_PIO_2, 212 XFER_PIO_1, 213 XFER_PIO_0 214}; 215 216/* Key for bus clock timings 217 * 36x 37x 218 * bits bits 219 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 220 * cycles = value + 1 221 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 222 * cycles = value + 1 223 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 224 * register access. 225 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 226 * register access. 227 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 228 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock. 229 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and 230 * MW DMA xfer. 231 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for 232 * task file register access. 233 * 28 28 UDMA enable. 234 * 29 29 DMA enable. 235 * 30 30 PIO MST enable. If set, the chip is in bus master mode during 236 * PIO xfer. 237 * 31 31 FIFO enable. 238 */ 239 240static u32 forty_base_hpt36x[] = { 241 /* XFER_UDMA_6 */ 0x900fd943, 242 /* XFER_UDMA_5 */ 0x900fd943, 243 /* XFER_UDMA_4 */ 0x900fd943, 244 /* XFER_UDMA_3 */ 0x900ad943, 245 /* XFER_UDMA_2 */ 0x900bd943, 246 /* XFER_UDMA_1 */ 0x9008d943, 247 /* XFER_UDMA_0 */ 0x9008d943, 248 249 /* XFER_MW_DMA_2 */ 0xa008d943, 250 /* XFER_MW_DMA_1 */ 0xa010d955, 251 /* XFER_MW_DMA_0 */ 0xa010d9fc, 252 253 /* XFER_PIO_4 */ 0xc008d963, 254 /* XFER_PIO_3 */ 0xc010d974, 255 /* XFER_PIO_2 */ 0xc010d997, 256 /* XFER_PIO_1 */ 0xc010d9c7, 257 /* XFER_PIO_0 */ 0xc018d9d9 258}; 259 260static u32 thirty_three_base_hpt36x[] = { 261 /* XFER_UDMA_6 */ 0x90c9a731, 262 /* XFER_UDMA_5 */ 0x90c9a731, 263 /* XFER_UDMA_4 */ 0x90c9a731, 264 /* XFER_UDMA_3 */ 0x90cfa731, 265 /* XFER_UDMA_2 */ 0x90caa731, 266 /* XFER_UDMA_1 */ 0x90cba731, 267 /* XFER_UDMA_0 */ 0x90c8a731, 268 269 /* XFER_MW_DMA_2 */ 0xa0c8a731, 270 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */ 271 /* XFER_MW_DMA_0 */ 0xa0c8a797, 272 273 /* XFER_PIO_4 */ 0xc0c8a731, 274 /* XFER_PIO_3 */ 0xc0c8a742, 275 /* XFER_PIO_2 */ 0xc0d0a753, 276 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */ 277 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */ 278}; 279 280static u32 twenty_five_base_hpt36x[] = { 281 /* XFER_UDMA_6 */ 0x90c98521, 282 /* XFER_UDMA_5 */ 0x90c98521, 283 /* XFER_UDMA_4 */ 0x90c98521, 284 /* XFER_UDMA_3 */ 0x90cf8521, 285 /* XFER_UDMA_2 */ 0x90cf8521, 286 /* XFER_UDMA_1 */ 0x90cb8521, 287 /* XFER_UDMA_0 */ 0x90cb8521, 288 289 /* XFER_MW_DMA_2 */ 0xa0ca8521, 290 /* XFER_MW_DMA_1 */ 0xa0ca8532, 291 /* XFER_MW_DMA_0 */ 0xa0ca8575, 292 293 /* XFER_PIO_4 */ 0xc0ca8521, 294 /* XFER_PIO_3 */ 0xc0ca8532, 295 /* XFER_PIO_2 */ 0xc0ca8542, 296 /* XFER_PIO_1 */ 0xc0d08572, 297 /* XFER_PIO_0 */ 0xc0d08585 298}; 299 300/* 301 * The following are the new timing tables with PIO mode data/taskfile transfer 302 * overclocking fixed... 303 */ 304 305/* This table is taken from the HPT370 data manual rev. 1.02 */ 306static u32 thirty_three_base_hpt37x[] = { 307 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */ 308 /* XFER_UDMA_5 */ 0x16455031, 309 /* XFER_UDMA_4 */ 0x16455031, 310 /* XFER_UDMA_3 */ 0x166d5031, 311 /* XFER_UDMA_2 */ 0x16495031, 312 /* XFER_UDMA_1 */ 0x164d5033, 313 /* XFER_UDMA_0 */ 0x16515097, 314 315 /* XFER_MW_DMA_2 */ 0x26515031, 316 /* XFER_MW_DMA_1 */ 0x26515033, 317 /* XFER_MW_DMA_0 */ 0x26515097, 318 319 /* XFER_PIO_4 */ 0x06515021, 320 /* XFER_PIO_3 */ 0x06515022, 321 /* XFER_PIO_2 */ 0x06515033, 322 /* XFER_PIO_1 */ 0x06915065, 323 /* XFER_PIO_0 */ 0x06d1508a 324}; 325 326static u32 fifty_base_hpt37x[] = { 327 /* XFER_UDMA_6 */ 0x1a861842, 328 /* XFER_UDMA_5 */ 0x1a861842, 329 /* XFER_UDMA_4 */ 0x1aae1842, 330 /* XFER_UDMA_3 */ 0x1a8e1842, 331 /* XFER_UDMA_2 */ 0x1a0e1842, 332 /* XFER_UDMA_1 */ 0x1a161854, 333 /* XFER_UDMA_0 */ 0x1a1a18ea, 334 335 /* XFER_MW_DMA_2 */ 0x2a821842, 336 /* XFER_MW_DMA_1 */ 0x2a821854, 337 /* XFER_MW_DMA_0 */ 0x2a8218ea, 338 339 /* XFER_PIO_4 */ 0x0a821842, 340 /* XFER_PIO_3 */ 0x0a821843, 341 /* XFER_PIO_2 */ 0x0a821855, 342 /* XFER_PIO_1 */ 0x0ac218a8, 343 /* XFER_PIO_0 */ 0x0b02190c 344}; 345 346static u32 sixty_six_base_hpt37x[] = { 347 /* XFER_UDMA_6 */ 0x1c86fe62, 348 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */ 349 /* XFER_UDMA_4 */ 0x1c8afe62, 350 /* XFER_UDMA_3 */ 0x1c8efe62, 351 /* XFER_UDMA_2 */ 0x1c92fe62, 352 /* XFER_UDMA_1 */ 0x1c9afe62, 353 /* XFER_UDMA_0 */ 0x1c82fe62, 354 355 /* XFER_MW_DMA_2 */ 0x2c82fe62, 356 /* XFER_MW_DMA_1 */ 0x2c82fe66, 357 /* XFER_MW_DMA_0 */ 0x2c82ff2e, 358 359 /* XFER_PIO_4 */ 0x0c82fe62, 360 /* XFER_PIO_3 */ 0x0c82fe84, 361 /* XFER_PIO_2 */ 0x0c82fea6, 362 /* XFER_PIO_1 */ 0x0d02ff26, 363 /* XFER_PIO_0 */ 0x0d42ff7f 364}; 365 366#define HPT371_ALLOW_ATA133_6 1 367#define HPT302_ALLOW_ATA133_6 1 368#define HPT372_ALLOW_ATA133_6 1 369#define HPT370_ALLOW_ATA100_5 0 370#define HPT366_ALLOW_ATA66_4 1 371#define HPT366_ALLOW_ATA66_3 1 372 373/* Supported ATA clock frequencies */ 374enum ata_clock { 375 ATA_CLOCK_25MHZ, 376 ATA_CLOCK_33MHZ, 377 ATA_CLOCK_40MHZ, 378 ATA_CLOCK_50MHZ, 379 ATA_CLOCK_66MHZ, 380 NUM_ATA_CLOCKS 381}; 382 383struct hpt_timings { 384 u32 pio_mask; 385 u32 dma_mask; 386 u32 ultra_mask; 387 u32 *clock_table[NUM_ATA_CLOCKS]; 388}; 389 390/* 391 * Hold all the HighPoint chip information in one place. 392 */ 393 394struct hpt_info { 395 char *chip_name; /* Chip name */ 396 u8 chip_type; /* Chip type */ 397 u8 udma_mask; /* Allowed UltraDMA modes mask. */ 398 u8 dpll_clk; /* DPLL clock in MHz */ 399 u8 pci_clk; /* PCI clock in MHz */ 400 struct hpt_timings *timings; /* Chipset timing data */ 401 u8 clock; /* ATA clock selected */ 402}; 403 404/* Supported HighPoint chips */ 405enum { 406 HPT36x, 407 HPT370, 408 HPT370A, 409 HPT374, 410 HPT372, 411 HPT372A, 412 HPT302, 413 HPT371, 414 HPT372N, 415 HPT302N, 416 HPT371N 417}; 418 419static struct hpt_timings hpt36x_timings = { 420 .pio_mask = 0xc1f8ffff, 421 .dma_mask = 0x303800ff, 422 .ultra_mask = 0x30070000, 423 .clock_table = { 424 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x, 425 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x, 426 [ATA_CLOCK_40MHZ] = forty_base_hpt36x, 427 [ATA_CLOCK_50MHZ] = NULL, 428 [ATA_CLOCK_66MHZ] = NULL 429 } 430}; 431 432static struct hpt_timings hpt37x_timings = { 433 .pio_mask = 0xcfc3ffff, 434 .dma_mask = 0x31c001ff, 435 .ultra_mask = 0x303c0000, 436 .clock_table = { 437 [ATA_CLOCK_25MHZ] = NULL, 438 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x, 439 [ATA_CLOCK_40MHZ] = NULL, 440 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x, 441 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x 442 } 443}; 444 445static const struct hpt_info hpt36x __devinitdata = { 446 .chip_name = "HPT36x", 447 .chip_type = HPT36x, 448 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2, 449 .dpll_clk = 0, /* no DPLL */ 450 .timings = &hpt36x_timings 451}; 452 453static const struct hpt_info hpt370 __devinitdata = { 454 .chip_name = "HPT370", 455 .chip_type = HPT370, 456 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, 457 .dpll_clk = 48, 458 .timings = &hpt37x_timings 459}; 460 461static const struct hpt_info hpt370a __devinitdata = { 462 .chip_name = "HPT370A", 463 .chip_type = HPT370A, 464 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, 465 .dpll_clk = 48, 466 .timings = &hpt37x_timings 467}; 468 469static const struct hpt_info hpt374 __devinitdata = { 470 .chip_name = "HPT374", 471 .chip_type = HPT374, 472 .udma_mask = ATA_UDMA5, 473 .dpll_clk = 48, 474 .timings = &hpt37x_timings 475}; 476 477static const struct hpt_info hpt372 __devinitdata = { 478 .chip_name = "HPT372", 479 .chip_type = HPT372, 480 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 481 .dpll_clk = 55, 482 .timings = &hpt37x_timings 483}; 484 485static const struct hpt_info hpt372a __devinitdata = { 486 .chip_name = "HPT372A", 487 .chip_type = HPT372A, 488 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 489 .dpll_clk = 66, 490 .timings = &hpt37x_timings 491}; 492 493static const struct hpt_info hpt302 __devinitdata = { 494 .chip_name = "HPT302", 495 .chip_type = HPT302, 496 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 497 .dpll_clk = 66, 498 .timings = &hpt37x_timings 499}; 500 501static const struct hpt_info hpt371 __devinitdata = { 502 .chip_name = "HPT371", 503 .chip_type = HPT371, 504 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 505 .dpll_clk = 66, 506 .timings = &hpt37x_timings 507}; 508 509static const struct hpt_info hpt372n __devinitdata = { 510 .chip_name = "HPT372N", 511 .chip_type = HPT372N, 512 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 513 .dpll_clk = 77, 514 .timings = &hpt37x_timings 515}; 516 517static const struct hpt_info hpt302n __devinitdata = { 518 .chip_name = "HPT302N", 519 .chip_type = HPT302N, 520 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 521 .dpll_clk = 77, 522 .timings = &hpt37x_timings 523}; 524 525static const struct hpt_info hpt371n __devinitdata = { 526 .chip_name = "HPT371N", 527 .chip_type = HPT371N, 528 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 529 .dpll_clk = 77, 530 .timings = &hpt37x_timings 531}; 532 533static int check_in_drive_list(ide_drive_t *drive, const char **list) 534{ 535 char *m = (char *)&drive->id[ATA_ID_PROD]; 536 537 while (*list) 538 if (!strcmp(*list++, m)) 539 return 1; 540 return 0; 541} 542 543static struct hpt_info *hpt3xx_get_info(struct device *dev) 544{ 545 struct ide_host *host = dev_get_drvdata(dev); 546 struct hpt_info *info = (struct hpt_info *)host->host_priv; 547 548 return dev == host->dev[1] ? info + 1 : info; 549} 550 551/* 552 * The Marvell bridge chips used on the HighPoint SATA cards do not seem 553 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... 554 */ 555 556static u8 hpt3xx_udma_filter(ide_drive_t *drive) 557{ 558 ide_hwif_t *hwif = drive->hwif; 559 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 560 u8 mask = hwif->ultra_mask; 561 562 switch (info->chip_type) { 563 case HPT36x: 564 if (!HPT366_ALLOW_ATA66_4 || 565 check_in_drive_list(drive, bad_ata66_4)) 566 mask = ATA_UDMA3; 567 568 if (!HPT366_ALLOW_ATA66_3 || 569 check_in_drive_list(drive, bad_ata66_3)) 570 mask = ATA_UDMA2; 571 break; 572 case HPT370: 573 if (!HPT370_ALLOW_ATA100_5 || 574 check_in_drive_list(drive, bad_ata100_5)) 575 mask = ATA_UDMA4; 576 break; 577 case HPT370A: 578 if (!HPT370_ALLOW_ATA100_5 || 579 check_in_drive_list(drive, bad_ata100_5)) 580 return ATA_UDMA4; 581 case HPT372 : 582 case HPT372A: 583 case HPT372N: 584 case HPT374 : 585 if (ata_id_is_sata(drive->id)) 586 mask &= ~0x0e; 587 /* Fall thru */ 588 default: 589 return mask; 590 } 591 592 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask; 593} 594 595static u8 hpt3xx_mdma_filter(ide_drive_t *drive) 596{ 597 ide_hwif_t *hwif = drive->hwif; 598 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 599 600 switch (info->chip_type) { 601 case HPT372 : 602 case HPT372A: 603 case HPT372N: 604 case HPT374 : 605 if (ata_id_is_sata(drive->id)) 606 return 0x00; 607 /* Fall thru */ 608 default: 609 return 0x07; 610 } 611} 612 613static u32 get_speed_setting(u8 speed, struct hpt_info *info) 614{ 615 int i; 616 617 /* 618 * Lookup the transfer mode table to get the index into 619 * the timing table. 620 * 621 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used. 622 */ 623 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) 624 if (xfer_speeds[i] == speed) 625 break; 626 627 return info->timings->clock_table[info->clock][i]; 628} 629 630static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) 631{ 632 struct pci_dev *dev = to_pci_dev(hwif->dev); 633 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 634 struct hpt_timings *t = info->timings; 635 u8 itr_addr = 0x40 + (drive->dn * 4); 636 u32 old_itr = 0; 637 const u8 speed = drive->dma_mode; 638 u32 new_itr = get_speed_setting(speed, info); 639 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask : 640 (speed < XFER_UDMA_0 ? t->dma_mask : 641 t->ultra_mask); 642 643 pci_read_config_dword(dev, itr_addr, &old_itr); 644 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask); 645 /* 646 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) 647 * to avoid problems handling I/O errors later 648 */ 649 new_itr &= ~0xc0000000; 650 651 pci_write_config_dword(dev, itr_addr, new_itr); 652} 653 654static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 655{ 656 drive->dma_mode = drive->pio_mode; 657 hpt3xx_set_mode(hwif, drive); 658} 659 660static void hpt3xx_maskproc(ide_drive_t *drive, int mask) 661{ 662 ide_hwif_t *hwif = drive->hwif; 663 struct pci_dev *dev = to_pci_dev(hwif->dev); 664 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 665 666 if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0) 667 return; 668 669 if (info->chip_type >= HPT370) { 670 u8 scr1 = 0; 671 672 pci_read_config_byte(dev, 0x5a, &scr1); 673 if (((scr1 & 0x10) >> 4) != mask) { 674 if (mask) 675 scr1 |= 0x10; 676 else 677 scr1 &= ~0x10; 678 pci_write_config_byte(dev, 0x5a, scr1); 679 } 680 } else if (mask) 681 disable_irq(hwif->irq); 682 else 683 enable_irq(hwif->irq); 684} 685 686/* 687 * This is specific to the HPT366 UDMA chipset 688 * by HighPoint|Triones Technologies, Inc. 689 */ 690static void hpt366_dma_lost_irq(ide_drive_t *drive) 691{ 692 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 693 u8 mcr1 = 0, mcr3 = 0, scr1 = 0; 694 695 pci_read_config_byte(dev, 0x50, &mcr1); 696 pci_read_config_byte(dev, 0x52, &mcr3); 697 pci_read_config_byte(dev, 0x5a, &scr1); 698 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", 699 drive->name, __func__, mcr1, mcr3, scr1); 700 if (scr1 & 0x10) 701 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); 702 ide_dma_lost_irq(drive); 703} 704 705static void hpt370_clear_engine(ide_drive_t *drive) 706{ 707 ide_hwif_t *hwif = drive->hwif; 708 struct pci_dev *dev = to_pci_dev(hwif->dev); 709 710 pci_write_config_byte(dev, hwif->select_data, 0x37); 711 udelay(10); 712} 713 714static void hpt370_irq_timeout(ide_drive_t *drive) 715{ 716 ide_hwif_t *hwif = drive->hwif; 717 struct pci_dev *dev = to_pci_dev(hwif->dev); 718 u16 bfifo = 0; 719 u8 dma_cmd; 720 721 pci_read_config_word(dev, hwif->select_data + 2, &bfifo); 722 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); 723 724 /* get DMA command mode */ 725 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 726 /* stop DMA */ 727 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD); 728 hpt370_clear_engine(drive); 729} 730 731static void hpt370_dma_start(ide_drive_t *drive) 732{ 733#ifdef HPT_RESET_STATE_ENGINE 734 hpt370_clear_engine(drive); 735#endif 736 ide_dma_start(drive); 737} 738 739static int hpt370_dma_end(ide_drive_t *drive) 740{ 741 ide_hwif_t *hwif = drive->hwif; 742 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 743 744 if (dma_stat & ATA_DMA_ACTIVE) { 745 /* wait a little */ 746 udelay(20); 747 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 748 if (dma_stat & ATA_DMA_ACTIVE) 749 hpt370_irq_timeout(drive); 750 } 751 return ide_dma_end(drive); 752} 753 754/* returns 1 if DMA IRQ issued, 0 otherwise */ 755static int hpt374_dma_test_irq(ide_drive_t *drive) 756{ 757 ide_hwif_t *hwif = drive->hwif; 758 struct pci_dev *dev = to_pci_dev(hwif->dev); 759 u16 bfifo = 0; 760 u8 dma_stat; 761 762 pci_read_config_word(dev, hwif->select_data + 2, &bfifo); 763 if (bfifo & 0x1FF) { 764// printk("%s: %d bytes in FIFO\n", drive->name, bfifo); 765 return 0; 766 } 767 768 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 769 /* return 1 if INTR asserted */ 770 if (dma_stat & ATA_DMA_INTR) 771 return 1; 772 773 return 0; 774} 775 776static int hpt374_dma_end(ide_drive_t *drive) 777{ 778 ide_hwif_t *hwif = drive->hwif; 779 struct pci_dev *dev = to_pci_dev(hwif->dev); 780 u8 mcr = 0, mcr_addr = hwif->select_data; 781 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; 782 783 pci_read_config_byte(dev, 0x6a, &bwsr); 784 pci_read_config_byte(dev, mcr_addr, &mcr); 785 if (bwsr & mask) 786 pci_write_config_byte(dev, mcr_addr, mcr | 0x30); 787 return ide_dma_end(drive); 788} 789 790/** 791 * hpt3xxn_set_clock - perform clock switching dance 792 * @hwif: hwif to switch 793 * @mode: clocking mode (0x21 for write, 0x23 otherwise) 794 * 795 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. 796 */ 797 798static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) 799{ 800 unsigned long base = hwif->extra_base; 801 u8 scr2 = inb(base + 0x6b); 802 803 if ((scr2 & 0x7f) == mode) 804 return; 805 806 /* Tristate the bus */ 807 outb(0x80, base + 0x63); 808 outb(0x80, base + 0x67); 809 810 /* Switch clock and reset channels */ 811 outb(mode, base + 0x6b); 812 outb(0xc0, base + 0x69); 813 814 /* 815 * Reset the state machines. 816 * NOTE: avoid accidentally enabling the disabled channels. 817 */ 818 outb(inb(base + 0x60) | 0x32, base + 0x60); 819 outb(inb(base + 0x64) | 0x32, base + 0x64); 820 821 /* Complete reset */ 822 outb(0x00, base + 0x69); 823 824 /* Reconnect channels to bus */ 825 outb(0x00, base + 0x63); 826 outb(0x00, base + 0x67); 827} 828 829/** 830 * hpt3xxn_rw_disk - prepare for I/O 831 * @drive: drive for command 832 * @rq: block request structure 833 * 834 * This is called when a disk I/O is issued to HPT3xxN. 835 * We need it because of the clock switching. 836 */ 837 838static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) 839{ 840 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21); 841} 842 843/** 844 * hpt37x_calibrate_dpll - calibrate the DPLL 845 * @dev: PCI device 846 * 847 * Perform a calibration cycle on the DPLL. 848 * Returns 1 if this succeeds 849 */ 850static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high) 851{ 852 u32 dpll = (f_high << 16) | f_low | 0x100; 853 u8 scr2; 854 int i; 855 856 pci_write_config_dword(dev, 0x5c, dpll); 857 858 /* Wait for oscillator ready */ 859 for(i = 0; i < 0x5000; ++i) { 860 udelay(50); 861 pci_read_config_byte(dev, 0x5b, &scr2); 862 if (scr2 & 0x80) 863 break; 864 } 865 /* See if it stays ready (we'll just bail out if it's not yet) */ 866 for(i = 0; i < 0x1000; ++i) { 867 pci_read_config_byte(dev, 0x5b, &scr2); 868 /* DPLL destabilized? */ 869 if(!(scr2 & 0x80)) 870 return 0; 871 } 872 /* Turn off tuning, we have the DPLL set */ 873 pci_read_config_dword (dev, 0x5c, &dpll); 874 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); 875 return 1; 876} 877 878static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr) 879{ 880 struct ide_host *host = pci_get_drvdata(dev); 881 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]); 882 u8 chip_type = info->chip_type; 883 u8 new_mcr, old_mcr = 0; 884 885 /* 886 * Disable the "fast interrupt" prediction. Don't hold off 887 * on interrupts. (== 0x01 despite what the docs say) 888 */ 889 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr); 890 891 if (chip_type >= HPT374) 892 new_mcr = old_mcr & ~0x07; 893 else if (chip_type >= HPT370) { 894 new_mcr = old_mcr; 895 new_mcr &= ~0x02; 896#ifdef HPT_DELAY_INTERRUPT 897 new_mcr &= ~0x01; 898#else 899 new_mcr |= 0x01; 900#endif 901 } else /* HPT366 and HPT368 */ 902 new_mcr = old_mcr & ~0x80; 903 904 if (new_mcr != old_mcr) 905 pci_write_config_byte(dev, mcr_addr + 1, new_mcr); 906} 907 908static int init_chipset_hpt366(struct pci_dev *dev) 909{ 910 unsigned long io_base = pci_resource_start(dev, 4); 911 struct hpt_info *info = hpt3xx_get_info(&dev->dev); 912 const char *name = DRV_NAME; 913 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */ 914 u8 chip_type; 915 enum ata_clock clock; 916 917 chip_type = info->chip_type; 918 919 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 920 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 921 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 922 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 923 924 /* 925 * First, try to estimate the PCI clock frequency... 926 */ 927 if (chip_type >= HPT370) { 928 u8 scr1 = 0; 929 u16 f_cnt = 0; 930 u32 temp = 0; 931 932 /* Interrupt force enable. */ 933 pci_read_config_byte(dev, 0x5a, &scr1); 934 if (scr1 & 0x10) 935 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); 936 937 /* 938 * HighPoint does this for HPT372A. 939 * NOTE: This register is only writeable via I/O space. 940 */ 941 if (chip_type == HPT372A) 942 outb(0x0e, io_base + 0x9c); 943 944 /* 945 * Default to PCI clock. Make sure MA15/16 are set to output 946 * to prevent drives having problems with 40-pin cables. 947 */ 948 pci_write_config_byte(dev, 0x5b, 0x23); 949 950 /* 951 * We'll have to read f_CNT value in order to determine 952 * the PCI clock frequency according to the following ratio: 953 * 954 * f_CNT = Fpci * 192 / Fdpll 955 * 956 * First try reading the register in which the HighPoint BIOS 957 * saves f_CNT value before reprogramming the DPLL from its 958 * default setting (which differs for the various chips). 959 * 960 * NOTE: This register is only accessible via I/O space; 961 * HPT374 BIOS only saves it for the function 0, so we have to 962 * always read it from there -- no need to check the result of 963 * pci_get_slot() for the function 0 as the whole device has 964 * been already "pinned" (via function 1) in init_setup_hpt374() 965 */ 966 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { 967 struct pci_dev *dev1 = pci_get_slot(dev->bus, 968 dev->devfn - 1); 969 unsigned long io_base = pci_resource_start(dev1, 4); 970 971 temp = inl(io_base + 0x90); 972 pci_dev_put(dev1); 973 } else 974 temp = inl(io_base + 0x90); 975 976 /* 977 * In case the signature check fails, we'll have to 978 * resort to reading the f_CNT register itself in hopes 979 * that nobody has touched the DPLL yet... 980 */ 981 if ((temp & 0xFFFFF000) != 0xABCDE000) { 982 int i; 983 984 printk(KERN_WARNING "%s %s: no clock data saved by " 985 "BIOS\n", name, pci_name(dev)); 986 987 /* Calculate the average value of f_CNT. */ 988 for (temp = i = 0; i < 128; i++) { 989 pci_read_config_word(dev, 0x78, &f_cnt); 990 temp += f_cnt & 0x1ff; 991 mdelay(1); 992 } 993 f_cnt = temp / 128; 994 } else 995 f_cnt = temp & 0x1ff; 996 997 dpll_clk = info->dpll_clk; 998 pci_clk = (f_cnt * dpll_clk) / 192; 999 1000 /* Clamp PCI clock to bands. */ 1001 if (pci_clk < 40) 1002 pci_clk = 33; 1003 else if(pci_clk < 45) 1004 pci_clk = 40; 1005 else if(pci_clk < 55) 1006 pci_clk = 50; 1007 else 1008 pci_clk = 66; 1009 1010 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, " 1011 "assuming %d MHz PCI\n", name, pci_name(dev), 1012 dpll_clk, f_cnt, pci_clk); 1013 } else { 1014 u32 itr1 = 0; 1015 1016 pci_read_config_dword(dev, 0x40, &itr1); 1017 1018 /* Detect PCI clock by looking at cmd_high_time. */ 1019 switch((itr1 >> 8) & 0x07) { 1020 case 0x09: 1021 pci_clk = 40; 1022 break; 1023 case 0x05: 1024 pci_clk = 25; 1025 break; 1026 case 0x07: 1027 default: 1028 pci_clk = 33; 1029 break; 1030 } 1031 } 1032 1033 /* Let's assume we'll use PCI clock for the ATA clock... */ 1034 switch (pci_clk) { 1035 case 25: 1036 clock = ATA_CLOCK_25MHZ; 1037 break; 1038 case 33: 1039 default: 1040 clock = ATA_CLOCK_33MHZ; 1041 break; 1042 case 40: 1043 clock = ATA_CLOCK_40MHZ; 1044 break; 1045 case 50: 1046 clock = ATA_CLOCK_50MHZ; 1047 break; 1048 case 66: 1049 clock = ATA_CLOCK_66MHZ; 1050 break; 1051 } 1052 1053 /* 1054 * Only try the DPLL if we don't have a table for the PCI clock that 1055 * we are running at for HPT370/A, always use it for anything newer... 1056 * 1057 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI. 1058 * We also don't like using the DPLL because this causes glitches 1059 * on PRST-/SRST- when the state engine gets reset... 1060 */ 1061 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) { 1062 u16 f_low, delta = pci_clk < 50 ? 2 : 4; 1063 int adjust; 1064 1065 /* 1066 * Select 66 MHz DPLL clock only if UltraATA/133 mode is 1067 * supported/enabled, use 50 MHz DPLL clock otherwise... 1068 */ 1069 if (info->udma_mask == ATA_UDMA6) { 1070 dpll_clk = 66; 1071 clock = ATA_CLOCK_66MHZ; 1072 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ 1073 dpll_clk = 50; 1074 clock = ATA_CLOCK_50MHZ; 1075 } 1076 1077 if (info->timings->clock_table[clock] == NULL) { 1078 printk(KERN_ERR "%s %s: unknown bus timing!\n", 1079 name, pci_name(dev)); 1080 return -EIO; 1081 } 1082 1083 /* Select the DPLL clock. */ 1084 pci_write_config_byte(dev, 0x5b, 0x21); 1085 1086 /* 1087 * Adjust the DPLL based upon PCI clock, enable it, 1088 * and wait for stabilization... 1089 */ 1090 f_low = (pci_clk * 48) / dpll_clk; 1091 1092 for (adjust = 0; adjust < 8; adjust++) { 1093 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta)) 1094 break; 1095 1096 /* 1097 * See if it'll settle at a fractionally different clock 1098 */ 1099 if (adjust & 1) 1100 f_low -= adjust >> 1; 1101 else 1102 f_low += adjust >> 1; 1103 } 1104 if (adjust == 8) { 1105 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n", 1106 name, pci_name(dev)); 1107 return -EIO; 1108 } 1109 1110 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n", 1111 name, pci_name(dev), dpll_clk); 1112 } else { 1113 /* Mark the fact that we're not using the DPLL. */ 1114 dpll_clk = 0; 1115 1116 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n", 1117 name, pci_name(dev), pci_clk); 1118 } 1119 1120 /* Store the clock frequencies. */ 1121 info->dpll_clk = dpll_clk; 1122 info->pci_clk = pci_clk; 1123 info->clock = clock; 1124 1125 if (chip_type >= HPT370) { 1126 u8 mcr1, mcr4; 1127 1128 /* 1129 * Reset the state engines. 1130 * NOTE: Avoid accidentally enabling the disabled channels. 1131 */ 1132 pci_read_config_byte (dev, 0x50, &mcr1); 1133 pci_read_config_byte (dev, 0x54, &mcr4); 1134 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32)); 1135 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32)); 1136 udelay(100); 1137 } 1138 1139 /* 1140 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in 1141 * the MISC. register to stretch the UltraDMA Tss timing. 1142 * NOTE: This register is only writeable via I/O space. 1143 */ 1144 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ) 1145 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c); 1146 1147 hpt3xx_disable_fast_irq(dev, 0x50); 1148 hpt3xx_disable_fast_irq(dev, 0x54); 1149 1150 return 0; 1151} 1152 1153static u8 hpt3xx_cable_detect(ide_hwif_t *hwif) 1154{ 1155 struct pci_dev *dev = to_pci_dev(hwif->dev); 1156 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 1157 u8 chip_type = info->chip_type; 1158 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02; 1159 1160 /* 1161 * The HPT37x uses the CBLID pins as outputs for MA15/MA16 1162 * address lines to access an external EEPROM. To read valid 1163 * cable detect state the pins must be enabled as inputs. 1164 */ 1165 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { 1166 /* 1167 * HPT374 PCI function 1 1168 * - set bit 15 of reg 0x52 to enable TCBLID as input 1169 * - set bit 15 of reg 0x56 to enable FCBLID as input 1170 */ 1171 u8 mcr_addr = hwif->select_data + 2; 1172 u16 mcr; 1173 1174 pci_read_config_word(dev, mcr_addr, &mcr); 1175 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); 1176 /* now read cable id register */ 1177 pci_read_config_byte(dev, 0x5a, &scr1); 1178 pci_write_config_word(dev, mcr_addr, mcr); 1179 } else if (chip_type >= HPT370) { 1180 /* 1181 * HPT370/372 and 374 pcifn 0 1182 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs 1183 */ 1184 u8 scr2 = 0; 1185 1186 pci_read_config_byte(dev, 0x5b, &scr2); 1187 pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); 1188 /* now read cable id register */ 1189 pci_read_config_byte(dev, 0x5a, &scr1); 1190 pci_write_config_byte(dev, 0x5b, scr2); 1191 } else 1192 pci_read_config_byte(dev, 0x5a, &scr1); 1193 1194 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; 1195} 1196 1197static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) 1198{ 1199 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 1200 u8 chip_type = info->chip_type; 1201 1202 /* Cache the channel's MISC. control registers' offset */ 1203 hwif->select_data = hwif->channel ? 0x54 : 0x50; 1204 1205 /* 1206 * HPT3xxN chips have some complications: 1207 * 1208 * - on 33 MHz PCI we must clock switch 1209 * - on 66 MHz PCI we must NOT use the PCI clock 1210 */ 1211 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) { 1212 /* 1213 * Clock is shared between the channels, 1214 * so we'll have to serialize them... :-( 1215 */ 1216 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE; 1217 hwif->rw_disk = &hpt3xxn_rw_disk; 1218 } 1219} 1220 1221static int __devinit init_dma_hpt366(ide_hwif_t *hwif, 1222 const struct ide_port_info *d) 1223{ 1224 struct pci_dev *dev = to_pci_dev(hwif->dev); 1225 unsigned long flags, base = ide_pci_dma_base(hwif, d); 1226 u8 dma_old, dma_new, masterdma = 0, slavedma = 0; 1227 1228 if (base == 0) 1229 return -1; 1230 1231 hwif->dma_base = base; 1232 1233 if (ide_pci_check_simplex(hwif, d) < 0) 1234 return -1; 1235 1236 if (ide_pci_set_master(dev, d->name) < 0) 1237 return -1; 1238 1239 dma_old = inb(base + 2); 1240 1241 local_irq_save(flags); 1242 1243 dma_new = dma_old; 1244 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); 1245 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); 1246 1247 if (masterdma & 0x30) dma_new |= 0x20; 1248 if ( slavedma & 0x30) dma_new |= 0x40; 1249 if (dma_new != dma_old) 1250 outb(dma_new, base + 2); 1251 1252 local_irq_restore(flags); 1253 1254 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", 1255 hwif->name, base, base + 7); 1256 1257 hwif->extra_base = base + (hwif->channel ? 8 : 16); 1258 1259 if (ide_allocate_dma_engine(hwif)) 1260 return -1; 1261 1262 return 0; 1263} 1264 1265static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2) 1266{ 1267 if (dev2->irq != dev->irq) { 1268 /* FIXME: we need a core pci_set_interrupt() */ 1269 dev2->irq = dev->irq; 1270 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt " 1271 "fixed\n", pci_name(dev2)); 1272 } 1273} 1274 1275static void __devinit hpt371_init(struct pci_dev *dev) 1276{ 1277 u8 mcr1 = 0; 1278 1279 /* 1280 * HPT371 chips physically have only one channel, the secondary one, 1281 * but the primary channel registers do exist! Go figure... 1282 * So, we manually disable the non-existing channel here 1283 * (if the BIOS hasn't done this already). 1284 */ 1285 pci_read_config_byte(dev, 0x50, &mcr1); 1286 if (mcr1 & 0x04) 1287 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); 1288} 1289 1290static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2) 1291{ 1292 u8 mcr1 = 0, pin1 = 0, pin2 = 0; 1293 1294 /* 1295 * Now we'll have to force both channels enabled if 1296 * at least one of them has been enabled by BIOS... 1297 */ 1298 pci_read_config_byte(dev, 0x50, &mcr1); 1299 if (mcr1 & 0x30) 1300 pci_write_config_byte(dev, 0x50, mcr1 | 0x30); 1301 1302 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); 1303 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); 1304 1305 if (pin1 != pin2 && dev->irq == dev2->irq) { 1306 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, " 1307 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2); 1308 return 1; 1309 } 1310 1311 return 0; 1312} 1313 1314#define IDE_HFLAGS_HPT3XX \ 1315 (IDE_HFLAG_NO_ATAPI_DMA | \ 1316 IDE_HFLAG_OFF_BOARD) 1317 1318static const struct ide_port_ops hpt3xx_port_ops = { 1319 .set_pio_mode = hpt3xx_set_pio_mode, 1320 .set_dma_mode = hpt3xx_set_mode, 1321 .maskproc = hpt3xx_maskproc, 1322 .mdma_filter = hpt3xx_mdma_filter, 1323 .udma_filter = hpt3xx_udma_filter, 1324 .cable_detect = hpt3xx_cable_detect, 1325}; 1326 1327static const struct ide_dma_ops hpt37x_dma_ops = { 1328 .dma_host_set = ide_dma_host_set, 1329 .dma_setup = ide_dma_setup, 1330 .dma_start = ide_dma_start, 1331 .dma_end = hpt374_dma_end, 1332 .dma_test_irq = hpt374_dma_test_irq, 1333 .dma_lost_irq = ide_dma_lost_irq, 1334 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1335 .dma_sff_read_status = ide_dma_sff_read_status, 1336}; 1337 1338static const struct ide_dma_ops hpt370_dma_ops = { 1339 .dma_host_set = ide_dma_host_set, 1340 .dma_setup = ide_dma_setup, 1341 .dma_start = hpt370_dma_start, 1342 .dma_end = hpt370_dma_end, 1343 .dma_test_irq = ide_dma_test_irq, 1344 .dma_lost_irq = ide_dma_lost_irq, 1345 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1346 .dma_clear = hpt370_irq_timeout, 1347 .dma_sff_read_status = ide_dma_sff_read_status, 1348}; 1349 1350static const struct ide_dma_ops hpt36x_dma_ops = { 1351 .dma_host_set = ide_dma_host_set, 1352 .dma_setup = ide_dma_setup, 1353 .dma_start = ide_dma_start, 1354 .dma_end = ide_dma_end, 1355 .dma_test_irq = ide_dma_test_irq, 1356 .dma_lost_irq = hpt366_dma_lost_irq, 1357 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1358 .dma_sff_read_status = ide_dma_sff_read_status, 1359}; 1360 1361static const struct ide_port_info hpt366_chipsets[] __devinitdata = { 1362 { /* 0: HPT36x */ 1363 .name = DRV_NAME, 1364 .init_chipset = init_chipset_hpt366, 1365 .init_hwif = init_hwif_hpt366, 1366 .init_dma = init_dma_hpt366, 1367 /* 1368 * HPT36x chips have one channel per function and have 1369 * both channel enable bits located differently and visible 1370 * to both functions -- really stupid design decision... :-( 1371 * Bit 4 is for the primary channel, bit 5 for the secondary. 1372 */ 1373 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}}, 1374 .port_ops = &hpt3xx_port_ops, 1375 .dma_ops = &hpt36x_dma_ops, 1376 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE, 1377 .pio_mask = ATA_PIO4, 1378 .mwdma_mask = ATA_MWDMA2, 1379 }, 1380 { /* 1: HPT3xx */ 1381 .name = DRV_NAME, 1382 .init_chipset = init_chipset_hpt366, 1383 .init_hwif = init_hwif_hpt366, 1384 .init_dma = init_dma_hpt366, 1385 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1386 .port_ops = &hpt3xx_port_ops, 1387 .dma_ops = &hpt37x_dma_ops, 1388 .host_flags = IDE_HFLAGS_HPT3XX, 1389 .pio_mask = ATA_PIO4, 1390 .mwdma_mask = ATA_MWDMA2, 1391 } 1392}; 1393 1394/** 1395 * hpt366_init_one - called when an HPT366 is found 1396 * @dev: the hpt366 device 1397 * @id: the matching pci id 1398 * 1399 * Called when the PCI registration layer (or the IDE initialization) 1400 * finds a device matching our IDE device tables. 1401 */ 1402static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) 1403{ 1404 const struct hpt_info *info = NULL; 1405 struct hpt_info *dyn_info; 1406 struct pci_dev *dev2 = NULL; 1407 struct ide_port_info d; 1408 u8 idx = id->driver_data; 1409 u8 rev = dev->revision; 1410 int ret; 1411 1412 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1)) 1413 return -ENODEV; 1414 1415 switch (idx) { 1416 case 0: 1417 if (rev < 3) 1418 info = &hpt36x; 1419 else { 1420 switch (min_t(u8, rev, 6)) { 1421 case 3: info = &hpt370; break; 1422 case 4: info = &hpt370a; break; 1423 case 5: info = &hpt372; break; 1424 case 6: info = &hpt372n; break; 1425 } 1426 idx++; 1427 } 1428 break; 1429 case 1: 1430 info = (rev > 1) ? &hpt372n : &hpt372a; 1431 break; 1432 case 2: 1433 info = (rev > 1) ? &hpt302n : &hpt302; 1434 break; 1435 case 3: 1436 hpt371_init(dev); 1437 info = (rev > 1) ? &hpt371n : &hpt371; 1438 break; 1439 case 4: 1440 info = &hpt374; 1441 break; 1442 case 5: 1443 info = &hpt372n; 1444 break; 1445 } 1446 1447 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name); 1448 1449 d = hpt366_chipsets[min_t(u8, idx, 1)]; 1450 1451 d.udma_mask = info->udma_mask; 1452 1453 /* fixup ->dma_ops for HPT370/HPT370A */ 1454 if (info == &hpt370 || info == &hpt370a) 1455 d.dma_ops = &hpt370_dma_ops; 1456 1457 if (info == &hpt36x || info == &hpt374) 1458 dev2 = pci_get_slot(dev->bus, dev->devfn + 1); 1459 1460 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL); 1461 if (dyn_info == NULL) { 1462 printk(KERN_ERR "%s %s: out of memory!\n", 1463 d.name, pci_name(dev)); 1464 pci_dev_put(dev2); 1465 return -ENOMEM; 1466 } 1467 1468 /* 1469 * Copy everything from a static "template" structure 1470 * to just allocated per-chip hpt_info structure. 1471 */ 1472 memcpy(dyn_info, info, sizeof(*dyn_info)); 1473 1474 if (dev2) { 1475 memcpy(dyn_info + 1, info, sizeof(*dyn_info)); 1476 1477 if (info == &hpt374) 1478 hpt374_init(dev, dev2); 1479 else { 1480 if (hpt36x_init(dev, dev2)) 1481 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE; 1482 } 1483 1484 ret = ide_pci_init_two(dev, dev2, &d, dyn_info); 1485 if (ret < 0) { 1486 pci_dev_put(dev2); 1487 kfree(dyn_info); 1488 } 1489 return ret; 1490 } 1491 1492 ret = ide_pci_init_one(dev, &d, dyn_info); 1493 if (ret < 0) 1494 kfree(dyn_info); 1495 1496 return ret; 1497} 1498 1499static void __devexit hpt366_remove(struct pci_dev *dev) 1500{ 1501 struct ide_host *host = pci_get_drvdata(dev); 1502 struct ide_info *info = host->host_priv; 1503 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL; 1504 1505 ide_pci_remove(dev); 1506 pci_dev_put(dev2); 1507 kfree(info); 1508} 1509 1510static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = { 1511 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 }, 1512 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 }, 1513 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 }, 1514 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 }, 1515 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 }, 1516 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 }, 1517 { 0, }, 1518}; 1519MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl); 1520 1521static struct pci_driver hpt366_pci_driver = { 1522 .name = "HPT366_IDE", 1523 .id_table = hpt366_pci_tbl, 1524 .probe = hpt366_init_one, 1525 .remove = __devexit_p(hpt366_remove), 1526 .suspend = ide_pci_suspend, 1527 .resume = ide_pci_resume, 1528}; 1529 1530static int __init hpt366_ide_init(void) 1531{ 1532 return ide_pci_register_driver(&hpt366_pci_driver); 1533} 1534 1535static void __exit hpt366_ide_exit(void) 1536{ 1537 pci_unregister_driver(&hpt366_pci_driver); 1538} 1539 1540module_init(hpt366_ide_init); 1541module_exit(hpt366_ide_exit); 1542 1543MODULE_AUTHOR("Andre Hedrick"); 1544MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE"); 1545MODULE_LICENSE("GPL"); 1546