hpt366.c revision 8bc1e5aa06a2a9a425c4a6795fc564cba1521487
1/* 2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 3 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 4 * Portions Copyright (C) 2003 Red Hat Inc 5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz 6 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc. 7 * 8 * Thanks to HighPoint Technologies for their assistance, and hardware. 9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his 10 * donation of an ABit BP6 mainboard, processor, and memory acellerated 11 * development and support. 12 * 13 * 14 * HighPoint has its own drivers (open source except for the RAID part) 15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/. 16 * This may be useful to anyone wanting to work on this driver, however do not 17 * trust them too much since the code tends to become less and less meaningful 18 * as the time passes... :-/ 19 * 20 * Note that final HPT370 support was done by force extraction of GPL. 21 * 22 * - add function for getting/setting power status of drive 23 * - the HPT370's state machine can get confused. reset it before each dma 24 * xfer to prevent that from happening. 25 * - reset state engine whenever we get an error. 26 * - check for busmaster state at end of dma. 27 * - use new highpoint timings. 28 * - detect bus speed using highpoint register. 29 * - use pll if we don't have a clock table. added a 66MHz table that's 30 * just 2x the 33MHz table. 31 * - removed turnaround. NOTE: we never want to switch between pll and 32 * pci clocks as the chip can glitch in those cases. the highpoint 33 * approved workaround slows everything down too much to be useful. in 34 * addition, we would have to serialize access to each chip. 35 * Adrian Sun <a.sun@sun.com> 36 * 37 * add drive timings for 66MHz PCI bus, 38 * fix ATA Cable signal detection, fix incorrect /proc info 39 * add /proc display for per-drive PIO/DMA/UDMA mode and 40 * per-channel ATA-33/66 Cable detect. 41 * Duncan Laurie <void@sun.com> 42 * 43 * fixup /proc output for multiple controllers 44 * Tim Hockin <thockin@sun.com> 45 * 46 * On hpt366: 47 * Reset the hpt366 on error, reset on dma 48 * Fix disabling Fast Interrupt hpt366. 49 * Mike Waychison <crlf@sun.com> 50 * 51 * Added support for 372N clocking and clock switching. The 372N needs 52 * different clocks on read/write. This requires overloading rw_disk and 53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for 54 * keeping me sane. 55 * Alan Cox <alan@lxorguk.ukuu.org.uk> 56 * 57 * - fix the clock turnaround code: it was writing to the wrong ports when 58 * called for the secondary channel, caching the current clock mode per- 59 * channel caused the cached register value to get out of sync with the 60 * actual one, the channels weren't serialized, the turnaround shouldn't 61 * be done on 66 MHz PCI bus 62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used 63 * does not allow for this speed anyway 64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips, 65 * their primary channel is kind of virtual, it isn't tied to any pins) 66 * - fix/remove bad/unused timing tables and use one set of tables for the whole 67 * HPT37x chip family; save space by introducing the separate transfer mode 68 * table in which the mode lookup is done 69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives 70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS; 71 * read it only from the function 0 of HPT374 chips 72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus, 73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead 74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as 75 * they tamper with its fields 76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure 77 * since they may tamper with its fields 78 * - prefix the driver startup messages with the real chip name 79 * - claim the extra 240 bytes of I/O space for all chips 80 * - optimize the UltraDMA filtering and the drive list lookup code 81 * - use pci_get_slot() to get to the function 1 of HPT36x/374 82 * - cache offset of the channel's misc. control registers (MCRs) being used 83 * throughout the driver 84 * - only touch the relevant MCR when detecting the cable type on HPT374's 85 * function 1 86 * - rename all the register related variables consistently 87 * - move all the interrupt twiddling code from the speedproc handlers into 88 * init_hwif_hpt366(), also grouping all the DMA related code together there 89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and 90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings 91 * when setting an UltraDMA mode 92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select 93 * the best possible one 94 * - clean up DMA timeout handling for HPT370 95 * - switch to using the enumeration type to differ between the numerous chip 96 * variants, matching PCI device/revision ID with the chip type early, at the 97 * init_setup stage 98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies, 99 * stop duplicating it for each channel by storing the pointer in the pci_dev 100 * structure: first, at the init_setup stage, point it to a static "template" 101 * with only the chip type and its specific base DPLL frequency, the highest 102 * UltraDMA mode, and the chip settings table pointer filled, then, at the 103 * init_chipset stage, allocate per-chip instance and fill it with the rest 104 * of the necessary information 105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code, 106 * switch to calculating PCI clock frequency based on the chip's base DPLL 107 * frequency 108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on 109 * anything newer than HPT370/A (except HPT374 that is not capable of this 110 * mode according to the manual) 111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(), 112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips; 113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining 114 * the register setting lists into the table indexed by the clock selected 115 * - set the correct hwif->ultra_mask for each individual chip 116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards 117 * - stop resetting HPT370's state machine before each DMA transfer as that has 118 * caused more harm than good 119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com> 120 */ 121 122#include <linux/types.h> 123#include <linux/module.h> 124#include <linux/kernel.h> 125#include <linux/delay.h> 126#include <linux/blkdev.h> 127#include <linux/interrupt.h> 128#include <linux/pci.h> 129#include <linux/init.h> 130#include <linux/ide.h> 131 132#include <asm/uaccess.h> 133#include <asm/io.h> 134 135#define DRV_NAME "hpt366" 136 137/* various tuning parameters */ 138#undef HPT_RESET_STATE_ENGINE 139#undef HPT_DELAY_INTERRUPT 140 141static const char *bad_ata100_5[] = { 142 "IBM-DTLA-307075", 143 "IBM-DTLA-307060", 144 "IBM-DTLA-307045", 145 "IBM-DTLA-307030", 146 "IBM-DTLA-307020", 147 "IBM-DTLA-307015", 148 "IBM-DTLA-305040", 149 "IBM-DTLA-305030", 150 "IBM-DTLA-305020", 151 "IC35L010AVER07-0", 152 "IC35L020AVER07-0", 153 "IC35L030AVER07-0", 154 "IC35L040AVER07-0", 155 "IC35L060AVER07-0", 156 "WDC AC310200R", 157 NULL 158}; 159 160static const char *bad_ata66_4[] = { 161 "IBM-DTLA-307075", 162 "IBM-DTLA-307060", 163 "IBM-DTLA-307045", 164 "IBM-DTLA-307030", 165 "IBM-DTLA-307020", 166 "IBM-DTLA-307015", 167 "IBM-DTLA-305040", 168 "IBM-DTLA-305030", 169 "IBM-DTLA-305020", 170 "IC35L010AVER07-0", 171 "IC35L020AVER07-0", 172 "IC35L030AVER07-0", 173 "IC35L040AVER07-0", 174 "IC35L060AVER07-0", 175 "WDC AC310200R", 176 "MAXTOR STM3320620A", 177 NULL 178}; 179 180static const char *bad_ata66_3[] = { 181 "WDC AC310200R", 182 NULL 183}; 184 185static const char *bad_ata33[] = { 186 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", 187 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 188 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 189 "Maxtor 90510D4", 190 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 191 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 192 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 193 NULL 194}; 195 196static u8 xfer_speeds[] = { 197 XFER_UDMA_6, 198 XFER_UDMA_5, 199 XFER_UDMA_4, 200 XFER_UDMA_3, 201 XFER_UDMA_2, 202 XFER_UDMA_1, 203 XFER_UDMA_0, 204 205 XFER_MW_DMA_2, 206 XFER_MW_DMA_1, 207 XFER_MW_DMA_0, 208 209 XFER_PIO_4, 210 XFER_PIO_3, 211 XFER_PIO_2, 212 XFER_PIO_1, 213 XFER_PIO_0 214}; 215 216/* Key for bus clock timings 217 * 36x 37x 218 * bits bits 219 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 220 * cycles = value + 1 221 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 222 * cycles = value + 1 223 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 224 * register access. 225 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 226 * register access. 227 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 228 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock. 229 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and 230 * MW DMA xfer. 231 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for 232 * task file register access. 233 * 28 28 UDMA enable. 234 * 29 29 DMA enable. 235 * 30 30 PIO MST enable. If set, the chip is in bus master mode during 236 * PIO xfer. 237 * 31 31 FIFO enable. 238 */ 239 240static u32 forty_base_hpt36x[] = { 241 /* XFER_UDMA_6 */ 0x900fd943, 242 /* XFER_UDMA_5 */ 0x900fd943, 243 /* XFER_UDMA_4 */ 0x900fd943, 244 /* XFER_UDMA_3 */ 0x900ad943, 245 /* XFER_UDMA_2 */ 0x900bd943, 246 /* XFER_UDMA_1 */ 0x9008d943, 247 /* XFER_UDMA_0 */ 0x9008d943, 248 249 /* XFER_MW_DMA_2 */ 0xa008d943, 250 /* XFER_MW_DMA_1 */ 0xa010d955, 251 /* XFER_MW_DMA_0 */ 0xa010d9fc, 252 253 /* XFER_PIO_4 */ 0xc008d963, 254 /* XFER_PIO_3 */ 0xc010d974, 255 /* XFER_PIO_2 */ 0xc010d997, 256 /* XFER_PIO_1 */ 0xc010d9c7, 257 /* XFER_PIO_0 */ 0xc018d9d9 258}; 259 260static u32 thirty_three_base_hpt36x[] = { 261 /* XFER_UDMA_6 */ 0x90c9a731, 262 /* XFER_UDMA_5 */ 0x90c9a731, 263 /* XFER_UDMA_4 */ 0x90c9a731, 264 /* XFER_UDMA_3 */ 0x90cfa731, 265 /* XFER_UDMA_2 */ 0x90caa731, 266 /* XFER_UDMA_1 */ 0x90cba731, 267 /* XFER_UDMA_0 */ 0x90c8a731, 268 269 /* XFER_MW_DMA_2 */ 0xa0c8a731, 270 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */ 271 /* XFER_MW_DMA_0 */ 0xa0c8a797, 272 273 /* XFER_PIO_4 */ 0xc0c8a731, 274 /* XFER_PIO_3 */ 0xc0c8a742, 275 /* XFER_PIO_2 */ 0xc0d0a753, 276 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */ 277 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */ 278}; 279 280static u32 twenty_five_base_hpt36x[] = { 281 /* XFER_UDMA_6 */ 0x90c98521, 282 /* XFER_UDMA_5 */ 0x90c98521, 283 /* XFER_UDMA_4 */ 0x90c98521, 284 /* XFER_UDMA_3 */ 0x90cf8521, 285 /* XFER_UDMA_2 */ 0x90cf8521, 286 /* XFER_UDMA_1 */ 0x90cb8521, 287 /* XFER_UDMA_0 */ 0x90cb8521, 288 289 /* XFER_MW_DMA_2 */ 0xa0ca8521, 290 /* XFER_MW_DMA_1 */ 0xa0ca8532, 291 /* XFER_MW_DMA_0 */ 0xa0ca8575, 292 293 /* XFER_PIO_4 */ 0xc0ca8521, 294 /* XFER_PIO_3 */ 0xc0ca8532, 295 /* XFER_PIO_2 */ 0xc0ca8542, 296 /* XFER_PIO_1 */ 0xc0d08572, 297 /* XFER_PIO_0 */ 0xc0d08585 298}; 299 300#if 0 301/* These are the timing tables from the HighPoint open source drivers... */ 302static u32 thirty_three_base_hpt37x[] = { 303 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */ 304 /* XFER_UDMA_5 */ 0x12446231, 305 /* XFER_UDMA_4 */ 0x12446231, 306 /* XFER_UDMA_3 */ 0x126c6231, 307 /* XFER_UDMA_2 */ 0x12486231, 308 /* XFER_UDMA_1 */ 0x124c6233, 309 /* XFER_UDMA_0 */ 0x12506297, 310 311 /* XFER_MW_DMA_2 */ 0x22406c31, 312 /* XFER_MW_DMA_1 */ 0x22406c33, 313 /* XFER_MW_DMA_0 */ 0x22406c97, 314 315 /* XFER_PIO_4 */ 0x06414e31, 316 /* XFER_PIO_3 */ 0x06414e42, 317 /* XFER_PIO_2 */ 0x06414e53, 318 /* XFER_PIO_1 */ 0x06814e93, 319 /* XFER_PIO_0 */ 0x06814ea7 320}; 321 322static u32 fifty_base_hpt37x[] = { 323 /* XFER_UDMA_6 */ 0x12848242, 324 /* XFER_UDMA_5 */ 0x12848242, 325 /* XFER_UDMA_4 */ 0x12ac8242, 326 /* XFER_UDMA_3 */ 0x128c8242, 327 /* XFER_UDMA_2 */ 0x120c8242, 328 /* XFER_UDMA_1 */ 0x12148254, 329 /* XFER_UDMA_0 */ 0x121882ea, 330 331 /* XFER_MW_DMA_2 */ 0x22808242, 332 /* XFER_MW_DMA_1 */ 0x22808254, 333 /* XFER_MW_DMA_0 */ 0x228082ea, 334 335 /* XFER_PIO_4 */ 0x0a81f442, 336 /* XFER_PIO_3 */ 0x0a81f443, 337 /* XFER_PIO_2 */ 0x0a81f454, 338 /* XFER_PIO_1 */ 0x0ac1f465, 339 /* XFER_PIO_0 */ 0x0ac1f48a 340}; 341 342static u32 sixty_six_base_hpt37x[] = { 343 /* XFER_UDMA_6 */ 0x1c869c62, 344 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */ 345 /* XFER_UDMA_4 */ 0x1c8a9c62, 346 /* XFER_UDMA_3 */ 0x1c8e9c62, 347 /* XFER_UDMA_2 */ 0x1c929c62, 348 /* XFER_UDMA_1 */ 0x1c9a9c62, 349 /* XFER_UDMA_0 */ 0x1c829c62, 350 351 /* XFER_MW_DMA_2 */ 0x2c829c62, 352 /* XFER_MW_DMA_1 */ 0x2c829c66, 353 /* XFER_MW_DMA_0 */ 0x2c829d2e, 354 355 /* XFER_PIO_4 */ 0x0c829c62, 356 /* XFER_PIO_3 */ 0x0c829c84, 357 /* XFER_PIO_2 */ 0x0c829ca6, 358 /* XFER_PIO_1 */ 0x0d029d26, 359 /* XFER_PIO_0 */ 0x0d029d5e 360}; 361#else 362/* 363 * The following are the new timing tables with PIO mode data/taskfile transfer 364 * overclocking fixed... 365 */ 366 367/* This table is taken from the HPT370 data manual rev. 1.02 */ 368static u32 thirty_three_base_hpt37x[] = { 369 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */ 370 /* XFER_UDMA_5 */ 0x16455031, 371 /* XFER_UDMA_4 */ 0x16455031, 372 /* XFER_UDMA_3 */ 0x166d5031, 373 /* XFER_UDMA_2 */ 0x16495031, 374 /* XFER_UDMA_1 */ 0x164d5033, 375 /* XFER_UDMA_0 */ 0x16515097, 376 377 /* XFER_MW_DMA_2 */ 0x26515031, 378 /* XFER_MW_DMA_1 */ 0x26515033, 379 /* XFER_MW_DMA_0 */ 0x26515097, 380 381 /* XFER_PIO_4 */ 0x06515021, 382 /* XFER_PIO_3 */ 0x06515022, 383 /* XFER_PIO_2 */ 0x06515033, 384 /* XFER_PIO_1 */ 0x06915065, 385 /* XFER_PIO_0 */ 0x06d1508a 386}; 387 388static u32 fifty_base_hpt37x[] = { 389 /* XFER_UDMA_6 */ 0x1a861842, 390 /* XFER_UDMA_5 */ 0x1a861842, 391 /* XFER_UDMA_4 */ 0x1aae1842, 392 /* XFER_UDMA_3 */ 0x1a8e1842, 393 /* XFER_UDMA_2 */ 0x1a0e1842, 394 /* XFER_UDMA_1 */ 0x1a161854, 395 /* XFER_UDMA_0 */ 0x1a1a18ea, 396 397 /* XFER_MW_DMA_2 */ 0x2a821842, 398 /* XFER_MW_DMA_1 */ 0x2a821854, 399 /* XFER_MW_DMA_0 */ 0x2a8218ea, 400 401 /* XFER_PIO_4 */ 0x0a821842, 402 /* XFER_PIO_3 */ 0x0a821843, 403 /* XFER_PIO_2 */ 0x0a821855, 404 /* XFER_PIO_1 */ 0x0ac218a8, 405 /* XFER_PIO_0 */ 0x0b02190c 406}; 407 408static u32 sixty_six_base_hpt37x[] = { 409 /* XFER_UDMA_6 */ 0x1c86fe62, 410 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */ 411 /* XFER_UDMA_4 */ 0x1c8afe62, 412 /* XFER_UDMA_3 */ 0x1c8efe62, 413 /* XFER_UDMA_2 */ 0x1c92fe62, 414 /* XFER_UDMA_1 */ 0x1c9afe62, 415 /* XFER_UDMA_0 */ 0x1c82fe62, 416 417 /* XFER_MW_DMA_2 */ 0x2c82fe62, 418 /* XFER_MW_DMA_1 */ 0x2c82fe66, 419 /* XFER_MW_DMA_0 */ 0x2c82ff2e, 420 421 /* XFER_PIO_4 */ 0x0c82fe62, 422 /* XFER_PIO_3 */ 0x0c82fe84, 423 /* XFER_PIO_2 */ 0x0c82fea6, 424 /* XFER_PIO_1 */ 0x0d02ff26, 425 /* XFER_PIO_0 */ 0x0d42ff7f 426}; 427#endif 428 429#define HPT366_DEBUG_DRIVE_INFO 0 430#define HPT371_ALLOW_ATA133_6 1 431#define HPT302_ALLOW_ATA133_6 1 432#define HPT372_ALLOW_ATA133_6 1 433#define HPT370_ALLOW_ATA100_5 0 434#define HPT366_ALLOW_ATA66_4 1 435#define HPT366_ALLOW_ATA66_3 1 436#define HPT366_MAX_DEVS 8 437 438/* Supported ATA clock frequencies */ 439enum ata_clock { 440 ATA_CLOCK_25MHZ, 441 ATA_CLOCK_33MHZ, 442 ATA_CLOCK_40MHZ, 443 ATA_CLOCK_50MHZ, 444 ATA_CLOCK_66MHZ, 445 NUM_ATA_CLOCKS 446}; 447 448struct hpt_timings { 449 u32 pio_mask; 450 u32 dma_mask; 451 u32 ultra_mask; 452 u32 *clock_table[NUM_ATA_CLOCKS]; 453}; 454 455/* 456 * Hold all the HighPoint chip information in one place. 457 */ 458 459struct hpt_info { 460 char *chip_name; /* Chip name */ 461 u8 chip_type; /* Chip type */ 462 u8 udma_mask; /* Allowed UltraDMA modes mask. */ 463 u8 dpll_clk; /* DPLL clock in MHz */ 464 u8 pci_clk; /* PCI clock in MHz */ 465 struct hpt_timings *timings; /* Chipset timing data */ 466 u8 clock; /* ATA clock selected */ 467}; 468 469/* Supported HighPoint chips */ 470enum { 471 HPT36x, 472 HPT370, 473 HPT370A, 474 HPT374, 475 HPT372, 476 HPT372A, 477 HPT302, 478 HPT371, 479 HPT372N, 480 HPT302N, 481 HPT371N 482}; 483 484static struct hpt_timings hpt36x_timings = { 485 .pio_mask = 0xc1f8ffff, 486 .dma_mask = 0x303800ff, 487 .ultra_mask = 0x30070000, 488 .clock_table = { 489 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x, 490 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x, 491 [ATA_CLOCK_40MHZ] = forty_base_hpt36x, 492 [ATA_CLOCK_50MHZ] = NULL, 493 [ATA_CLOCK_66MHZ] = NULL 494 } 495}; 496 497static struct hpt_timings hpt37x_timings = { 498 .pio_mask = 0xcfc3ffff, 499 .dma_mask = 0x31c001ff, 500 .ultra_mask = 0x303c0000, 501 .clock_table = { 502 [ATA_CLOCK_25MHZ] = NULL, 503 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x, 504 [ATA_CLOCK_40MHZ] = NULL, 505 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x, 506 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x 507 } 508}; 509 510static const struct hpt_info hpt36x __devinitdata = { 511 .chip_name = "HPT36x", 512 .chip_type = HPT36x, 513 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2, 514 .dpll_clk = 0, /* no DPLL */ 515 .timings = &hpt36x_timings 516}; 517 518static const struct hpt_info hpt370 __devinitdata = { 519 .chip_name = "HPT370", 520 .chip_type = HPT370, 521 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, 522 .dpll_clk = 48, 523 .timings = &hpt37x_timings 524}; 525 526static const struct hpt_info hpt370a __devinitdata = { 527 .chip_name = "HPT370A", 528 .chip_type = HPT370A, 529 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, 530 .dpll_clk = 48, 531 .timings = &hpt37x_timings 532}; 533 534static const struct hpt_info hpt374 __devinitdata = { 535 .chip_name = "HPT374", 536 .chip_type = HPT374, 537 .udma_mask = ATA_UDMA5, 538 .dpll_clk = 48, 539 .timings = &hpt37x_timings 540}; 541 542static const struct hpt_info hpt372 __devinitdata = { 543 .chip_name = "HPT372", 544 .chip_type = HPT372, 545 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 546 .dpll_clk = 55, 547 .timings = &hpt37x_timings 548}; 549 550static const struct hpt_info hpt372a __devinitdata = { 551 .chip_name = "HPT372A", 552 .chip_type = HPT372A, 553 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 554 .dpll_clk = 66, 555 .timings = &hpt37x_timings 556}; 557 558static const struct hpt_info hpt302 __devinitdata = { 559 .chip_name = "HPT302", 560 .chip_type = HPT302, 561 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 562 .dpll_clk = 66, 563 .timings = &hpt37x_timings 564}; 565 566static const struct hpt_info hpt371 __devinitdata = { 567 .chip_name = "HPT371", 568 .chip_type = HPT371, 569 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 570 .dpll_clk = 66, 571 .timings = &hpt37x_timings 572}; 573 574static const struct hpt_info hpt372n __devinitdata = { 575 .chip_name = "HPT372N", 576 .chip_type = HPT372N, 577 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 578 .dpll_clk = 77, 579 .timings = &hpt37x_timings 580}; 581 582static const struct hpt_info hpt302n __devinitdata = { 583 .chip_name = "HPT302N", 584 .chip_type = HPT302N, 585 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 586 .dpll_clk = 77, 587 .timings = &hpt37x_timings 588}; 589 590static const struct hpt_info hpt371n __devinitdata = { 591 .chip_name = "HPT371N", 592 .chip_type = HPT371N, 593 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 594 .dpll_clk = 77, 595 .timings = &hpt37x_timings 596}; 597 598static int check_in_drive_list(ide_drive_t *drive, const char **list) 599{ 600 char *m = (char *)&drive->id[ATA_ID_PROD]; 601 602 while (*list) 603 if (!strcmp(*list++, m)) 604 return 1; 605 return 0; 606} 607 608static struct hpt_info *hpt3xx_get_info(struct device *dev) 609{ 610 struct ide_host *host = dev_get_drvdata(dev); 611 struct hpt_info *info = (struct hpt_info *)host->host_priv; 612 613 return dev == host->dev[1] ? info + 1 : info; 614} 615 616/* 617 * The Marvell bridge chips used on the HighPoint SATA cards do not seem 618 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... 619 */ 620 621static u8 hpt3xx_udma_filter(ide_drive_t *drive) 622{ 623 ide_hwif_t *hwif = drive->hwif; 624 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 625 u8 mask = hwif->ultra_mask; 626 627 switch (info->chip_type) { 628 case HPT36x: 629 if (!HPT366_ALLOW_ATA66_4 || 630 check_in_drive_list(drive, bad_ata66_4)) 631 mask = ATA_UDMA3; 632 633 if (!HPT366_ALLOW_ATA66_3 || 634 check_in_drive_list(drive, bad_ata66_3)) 635 mask = ATA_UDMA2; 636 break; 637 case HPT370: 638 if (!HPT370_ALLOW_ATA100_5 || 639 check_in_drive_list(drive, bad_ata100_5)) 640 mask = ATA_UDMA4; 641 break; 642 case HPT370A: 643 if (!HPT370_ALLOW_ATA100_5 || 644 check_in_drive_list(drive, bad_ata100_5)) 645 return ATA_UDMA4; 646 case HPT372 : 647 case HPT372A: 648 case HPT372N: 649 case HPT374 : 650 if (ata_id_is_sata(drive->id)) 651 mask &= ~0x0e; 652 /* Fall thru */ 653 default: 654 return mask; 655 } 656 657 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask; 658} 659 660static u8 hpt3xx_mdma_filter(ide_drive_t *drive) 661{ 662 ide_hwif_t *hwif = drive->hwif; 663 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 664 665 switch (info->chip_type) { 666 case HPT372 : 667 case HPT372A: 668 case HPT372N: 669 case HPT374 : 670 if (ata_id_is_sata(drive->id)) 671 return 0x00; 672 /* Fall thru */ 673 default: 674 return 0x07; 675 } 676} 677 678static u32 get_speed_setting(u8 speed, struct hpt_info *info) 679{ 680 int i; 681 682 /* 683 * Lookup the transfer mode table to get the index into 684 * the timing table. 685 * 686 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used. 687 */ 688 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) 689 if (xfer_speeds[i] == speed) 690 break; 691 692 return info->timings->clock_table[info->clock][i]; 693} 694 695static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed) 696{ 697 ide_hwif_t *hwif = drive->hwif; 698 struct pci_dev *dev = to_pci_dev(hwif->dev); 699 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 700 struct hpt_timings *t = info->timings; 701 u8 itr_addr = 0x40 + (drive->dn * 4); 702 u32 old_itr = 0; 703 u32 new_itr = get_speed_setting(speed, info); 704 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask : 705 (speed < XFER_UDMA_0 ? t->dma_mask : 706 t->ultra_mask); 707 708 pci_read_config_dword(dev, itr_addr, &old_itr); 709 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask); 710 /* 711 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) 712 * to avoid problems handling I/O errors later 713 */ 714 new_itr &= ~0xc0000000; 715 716 pci_write_config_dword(dev, itr_addr, new_itr); 717} 718 719static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio) 720{ 721 hpt3xx_set_mode(drive, XFER_PIO_0 + pio); 722} 723 724static void hpt3xx_maskproc(ide_drive_t *drive, int mask) 725{ 726 ide_hwif_t *hwif = drive->hwif; 727 struct pci_dev *dev = to_pci_dev(hwif->dev); 728 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 729 730 if (drive->quirk_list == 0) 731 return; 732 733 if (info->chip_type >= HPT370) { 734 u8 scr1 = 0; 735 736 pci_read_config_byte(dev, 0x5a, &scr1); 737 if (((scr1 & 0x10) >> 4) != mask) { 738 if (mask) 739 scr1 |= 0x10; 740 else 741 scr1 &= ~0x10; 742 pci_write_config_byte(dev, 0x5a, scr1); 743 } 744 } else if (mask) 745 disable_irq(hwif->irq); 746 else 747 enable_irq(hwif->irq); 748} 749 750/* 751 * This is specific to the HPT366 UDMA chipset 752 * by HighPoint|Triones Technologies, Inc. 753 */ 754static void hpt366_dma_lost_irq(ide_drive_t *drive) 755{ 756 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 757 u8 mcr1 = 0, mcr3 = 0, scr1 = 0; 758 759 pci_read_config_byte(dev, 0x50, &mcr1); 760 pci_read_config_byte(dev, 0x52, &mcr3); 761 pci_read_config_byte(dev, 0x5a, &scr1); 762 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", 763 drive->name, __func__, mcr1, mcr3, scr1); 764 if (scr1 & 0x10) 765 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); 766 ide_dma_lost_irq(drive); 767} 768 769static void hpt370_clear_engine(ide_drive_t *drive) 770{ 771 ide_hwif_t *hwif = drive->hwif; 772 struct pci_dev *dev = to_pci_dev(hwif->dev); 773 774 pci_write_config_byte(dev, hwif->select_data, 0x37); 775 udelay(10); 776} 777 778static void hpt370_irq_timeout(ide_drive_t *drive) 779{ 780 ide_hwif_t *hwif = drive->hwif; 781 struct pci_dev *dev = to_pci_dev(hwif->dev); 782 u16 bfifo = 0; 783 u8 dma_cmd; 784 785 pci_read_config_word(dev, hwif->select_data + 2, &bfifo); 786 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); 787 788 /* get DMA command mode */ 789 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 790 /* stop DMA */ 791 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD); 792 hpt370_clear_engine(drive); 793} 794 795static void hpt370_dma_start(ide_drive_t *drive) 796{ 797#ifdef HPT_RESET_STATE_ENGINE 798 hpt370_clear_engine(drive); 799#endif 800 ide_dma_start(drive); 801} 802 803static int hpt370_dma_end(ide_drive_t *drive) 804{ 805 ide_hwif_t *hwif = drive->hwif; 806 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 807 808 if (dma_stat & ATA_DMA_ACTIVE) { 809 /* wait a little */ 810 udelay(20); 811 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 812 if (dma_stat & ATA_DMA_ACTIVE) 813 hpt370_irq_timeout(drive); 814 } 815 return ide_dma_end(drive); 816} 817 818/* returns 1 if DMA IRQ issued, 0 otherwise */ 819static int hpt374_dma_test_irq(ide_drive_t *drive) 820{ 821 ide_hwif_t *hwif = drive->hwif; 822 struct pci_dev *dev = to_pci_dev(hwif->dev); 823 u16 bfifo = 0; 824 u8 dma_stat; 825 826 pci_read_config_word(dev, hwif->select_data + 2, &bfifo); 827 if (bfifo & 0x1FF) { 828// printk("%s: %d bytes in FIFO\n", drive->name, bfifo); 829 return 0; 830 } 831 832 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 833 /* return 1 if INTR asserted */ 834 if (dma_stat & ATA_DMA_INTR) 835 return 1; 836 837 return 0; 838} 839 840static int hpt374_dma_end(ide_drive_t *drive) 841{ 842 ide_hwif_t *hwif = drive->hwif; 843 struct pci_dev *dev = to_pci_dev(hwif->dev); 844 u8 mcr = 0, mcr_addr = hwif->select_data; 845 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; 846 847 pci_read_config_byte(dev, 0x6a, &bwsr); 848 pci_read_config_byte(dev, mcr_addr, &mcr); 849 if (bwsr & mask) 850 pci_write_config_byte(dev, mcr_addr, mcr | 0x30); 851 return ide_dma_end(drive); 852} 853 854/** 855 * hpt3xxn_set_clock - perform clock switching dance 856 * @hwif: hwif to switch 857 * @mode: clocking mode (0x21 for write, 0x23 otherwise) 858 * 859 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. 860 */ 861 862static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) 863{ 864 unsigned long base = hwif->extra_base; 865 u8 scr2 = inb(base + 0x6b); 866 867 if ((scr2 & 0x7f) == mode) 868 return; 869 870 /* Tristate the bus */ 871 outb(0x80, base + 0x63); 872 outb(0x80, base + 0x67); 873 874 /* Switch clock and reset channels */ 875 outb(mode, base + 0x6b); 876 outb(0xc0, base + 0x69); 877 878 /* 879 * Reset the state machines. 880 * NOTE: avoid accidentally enabling the disabled channels. 881 */ 882 outb(inb(base + 0x60) | 0x32, base + 0x60); 883 outb(inb(base + 0x64) | 0x32, base + 0x64); 884 885 /* Complete reset */ 886 outb(0x00, base + 0x69); 887 888 /* Reconnect channels to bus */ 889 outb(0x00, base + 0x63); 890 outb(0x00, base + 0x67); 891} 892 893/** 894 * hpt3xxn_rw_disk - prepare for I/O 895 * @drive: drive for command 896 * @rq: block request structure 897 * 898 * This is called when a disk I/O is issued to HPT3xxN. 899 * We need it because of the clock switching. 900 */ 901 902static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) 903{ 904 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21); 905} 906 907/** 908 * hpt37x_calibrate_dpll - calibrate the DPLL 909 * @dev: PCI device 910 * 911 * Perform a calibration cycle on the DPLL. 912 * Returns 1 if this succeeds 913 */ 914static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high) 915{ 916 u32 dpll = (f_high << 16) | f_low | 0x100; 917 u8 scr2; 918 int i; 919 920 pci_write_config_dword(dev, 0x5c, dpll); 921 922 /* Wait for oscillator ready */ 923 for(i = 0; i < 0x5000; ++i) { 924 udelay(50); 925 pci_read_config_byte(dev, 0x5b, &scr2); 926 if (scr2 & 0x80) 927 break; 928 } 929 /* See if it stays ready (we'll just bail out if it's not yet) */ 930 for(i = 0; i < 0x1000; ++i) { 931 pci_read_config_byte(dev, 0x5b, &scr2); 932 /* DPLL destabilized? */ 933 if(!(scr2 & 0x80)) 934 return 0; 935 } 936 /* Turn off tuning, we have the DPLL set */ 937 pci_read_config_dword (dev, 0x5c, &dpll); 938 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); 939 return 1; 940} 941 942static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr) 943{ 944 struct ide_host *host = pci_get_drvdata(dev); 945 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]); 946 u8 chip_type = info->chip_type; 947 u8 new_mcr, old_mcr = 0; 948 949 /* 950 * Disable the "fast interrupt" prediction. Don't hold off 951 * on interrupts. (== 0x01 despite what the docs say) 952 */ 953 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr); 954 955 if (chip_type >= HPT374) 956 new_mcr = old_mcr & ~0x07; 957 else if (chip_type >= HPT370) { 958 new_mcr = old_mcr; 959 new_mcr &= ~0x02; 960#ifdef HPT_DELAY_INTERRUPT 961 new_mcr &= ~0x01; 962#else 963 new_mcr |= 0x01; 964#endif 965 } else /* HPT366 and HPT368 */ 966 new_mcr = old_mcr & ~0x80; 967 968 if (new_mcr != old_mcr) 969 pci_write_config_byte(dev, mcr_addr + 1, new_mcr); 970} 971 972static int init_chipset_hpt366(struct pci_dev *dev) 973{ 974 unsigned long io_base = pci_resource_start(dev, 4); 975 struct hpt_info *info = hpt3xx_get_info(&dev->dev); 976 const char *name = DRV_NAME; 977 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */ 978 u8 chip_type; 979 enum ata_clock clock; 980 981 chip_type = info->chip_type; 982 983 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 984 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 985 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 986 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 987 988 /* 989 * First, try to estimate the PCI clock frequency... 990 */ 991 if (chip_type >= HPT370) { 992 u8 scr1 = 0; 993 u16 f_cnt = 0; 994 u32 temp = 0; 995 996 /* Interrupt force enable. */ 997 pci_read_config_byte(dev, 0x5a, &scr1); 998 if (scr1 & 0x10) 999 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); 1000 1001 /* 1002 * HighPoint does this for HPT372A. 1003 * NOTE: This register is only writeable via I/O space. 1004 */ 1005 if (chip_type == HPT372A) 1006 outb(0x0e, io_base + 0x9c); 1007 1008 /* 1009 * Default to PCI clock. Make sure MA15/16 are set to output 1010 * to prevent drives having problems with 40-pin cables. 1011 */ 1012 pci_write_config_byte(dev, 0x5b, 0x23); 1013 1014 /* 1015 * We'll have to read f_CNT value in order to determine 1016 * the PCI clock frequency according to the following ratio: 1017 * 1018 * f_CNT = Fpci * 192 / Fdpll 1019 * 1020 * First try reading the register in which the HighPoint BIOS 1021 * saves f_CNT value before reprogramming the DPLL from its 1022 * default setting (which differs for the various chips). 1023 * 1024 * NOTE: This register is only accessible via I/O space; 1025 * HPT374 BIOS only saves it for the function 0, so we have to 1026 * always read it from there -- no need to check the result of 1027 * pci_get_slot() for the function 0 as the whole device has 1028 * been already "pinned" (via function 1) in init_setup_hpt374() 1029 */ 1030 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { 1031 struct pci_dev *dev1 = pci_get_slot(dev->bus, 1032 dev->devfn - 1); 1033 unsigned long io_base = pci_resource_start(dev1, 4); 1034 1035 temp = inl(io_base + 0x90); 1036 pci_dev_put(dev1); 1037 } else 1038 temp = inl(io_base + 0x90); 1039 1040 /* 1041 * In case the signature check fails, we'll have to 1042 * resort to reading the f_CNT register itself in hopes 1043 * that nobody has touched the DPLL yet... 1044 */ 1045 if ((temp & 0xFFFFF000) != 0xABCDE000) { 1046 int i; 1047 1048 printk(KERN_WARNING "%s %s: no clock data saved by " 1049 "BIOS\n", name, pci_name(dev)); 1050 1051 /* Calculate the average value of f_CNT. */ 1052 for (temp = i = 0; i < 128; i++) { 1053 pci_read_config_word(dev, 0x78, &f_cnt); 1054 temp += f_cnt & 0x1ff; 1055 mdelay(1); 1056 } 1057 f_cnt = temp / 128; 1058 } else 1059 f_cnt = temp & 0x1ff; 1060 1061 dpll_clk = info->dpll_clk; 1062 pci_clk = (f_cnt * dpll_clk) / 192; 1063 1064 /* Clamp PCI clock to bands. */ 1065 if (pci_clk < 40) 1066 pci_clk = 33; 1067 else if(pci_clk < 45) 1068 pci_clk = 40; 1069 else if(pci_clk < 55) 1070 pci_clk = 50; 1071 else 1072 pci_clk = 66; 1073 1074 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, " 1075 "assuming %d MHz PCI\n", name, pci_name(dev), 1076 dpll_clk, f_cnt, pci_clk); 1077 } else { 1078 u32 itr1 = 0; 1079 1080 pci_read_config_dword(dev, 0x40, &itr1); 1081 1082 /* Detect PCI clock by looking at cmd_high_time. */ 1083 switch((itr1 >> 8) & 0x07) { 1084 case 0x09: 1085 pci_clk = 40; 1086 break; 1087 case 0x05: 1088 pci_clk = 25; 1089 break; 1090 case 0x07: 1091 default: 1092 pci_clk = 33; 1093 break; 1094 } 1095 } 1096 1097 /* Let's assume we'll use PCI clock for the ATA clock... */ 1098 switch (pci_clk) { 1099 case 25: 1100 clock = ATA_CLOCK_25MHZ; 1101 break; 1102 case 33: 1103 default: 1104 clock = ATA_CLOCK_33MHZ; 1105 break; 1106 case 40: 1107 clock = ATA_CLOCK_40MHZ; 1108 break; 1109 case 50: 1110 clock = ATA_CLOCK_50MHZ; 1111 break; 1112 case 66: 1113 clock = ATA_CLOCK_66MHZ; 1114 break; 1115 } 1116 1117 /* 1118 * Only try the DPLL if we don't have a table for the PCI clock that 1119 * we are running at for HPT370/A, always use it for anything newer... 1120 * 1121 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI. 1122 * We also don't like using the DPLL because this causes glitches 1123 * on PRST-/SRST- when the state engine gets reset... 1124 */ 1125 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) { 1126 u16 f_low, delta = pci_clk < 50 ? 2 : 4; 1127 int adjust; 1128 1129 /* 1130 * Select 66 MHz DPLL clock only if UltraATA/133 mode is 1131 * supported/enabled, use 50 MHz DPLL clock otherwise... 1132 */ 1133 if (info->udma_mask == ATA_UDMA6) { 1134 dpll_clk = 66; 1135 clock = ATA_CLOCK_66MHZ; 1136 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ 1137 dpll_clk = 50; 1138 clock = ATA_CLOCK_50MHZ; 1139 } 1140 1141 if (info->timings->clock_table[clock] == NULL) { 1142 printk(KERN_ERR "%s %s: unknown bus timing!\n", 1143 name, pci_name(dev)); 1144 return -EIO; 1145 } 1146 1147 /* Select the DPLL clock. */ 1148 pci_write_config_byte(dev, 0x5b, 0x21); 1149 1150 /* 1151 * Adjust the DPLL based upon PCI clock, enable it, 1152 * and wait for stabilization... 1153 */ 1154 f_low = (pci_clk * 48) / dpll_clk; 1155 1156 for (adjust = 0; adjust < 8; adjust++) { 1157 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta)) 1158 break; 1159 1160 /* 1161 * See if it'll settle at a fractionally different clock 1162 */ 1163 if (adjust & 1) 1164 f_low -= adjust >> 1; 1165 else 1166 f_low += adjust >> 1; 1167 } 1168 if (adjust == 8) { 1169 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n", 1170 name, pci_name(dev)); 1171 return -EIO; 1172 } 1173 1174 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n", 1175 name, pci_name(dev), dpll_clk); 1176 } else { 1177 /* Mark the fact that we're not using the DPLL. */ 1178 dpll_clk = 0; 1179 1180 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n", 1181 name, pci_name(dev), pci_clk); 1182 } 1183 1184 /* Store the clock frequencies. */ 1185 info->dpll_clk = dpll_clk; 1186 info->pci_clk = pci_clk; 1187 info->clock = clock; 1188 1189 if (chip_type >= HPT370) { 1190 u8 mcr1, mcr4; 1191 1192 /* 1193 * Reset the state engines. 1194 * NOTE: Avoid accidentally enabling the disabled channels. 1195 */ 1196 pci_read_config_byte (dev, 0x50, &mcr1); 1197 pci_read_config_byte (dev, 0x54, &mcr4); 1198 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32)); 1199 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32)); 1200 udelay(100); 1201 } 1202 1203 /* 1204 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in 1205 * the MISC. register to stretch the UltraDMA Tss timing. 1206 * NOTE: This register is only writeable via I/O space. 1207 */ 1208 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ) 1209 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c); 1210 1211 hpt3xx_disable_fast_irq(dev, 0x50); 1212 hpt3xx_disable_fast_irq(dev, 0x54); 1213 1214 return 0; 1215} 1216 1217static u8 hpt3xx_cable_detect(ide_hwif_t *hwif) 1218{ 1219 struct pci_dev *dev = to_pci_dev(hwif->dev); 1220 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 1221 u8 chip_type = info->chip_type; 1222 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02; 1223 1224 /* 1225 * The HPT37x uses the CBLID pins as outputs for MA15/MA16 1226 * address lines to access an external EEPROM. To read valid 1227 * cable detect state the pins must be enabled as inputs. 1228 */ 1229 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { 1230 /* 1231 * HPT374 PCI function 1 1232 * - set bit 15 of reg 0x52 to enable TCBLID as input 1233 * - set bit 15 of reg 0x56 to enable FCBLID as input 1234 */ 1235 u8 mcr_addr = hwif->select_data + 2; 1236 u16 mcr; 1237 1238 pci_read_config_word(dev, mcr_addr, &mcr); 1239 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); 1240 /* now read cable id register */ 1241 pci_read_config_byte(dev, 0x5a, &scr1); 1242 pci_write_config_word(dev, mcr_addr, mcr); 1243 } else if (chip_type >= HPT370) { 1244 /* 1245 * HPT370/372 and 374 pcifn 0 1246 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs 1247 */ 1248 u8 scr2 = 0; 1249 1250 pci_read_config_byte(dev, 0x5b, &scr2); 1251 pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); 1252 /* now read cable id register */ 1253 pci_read_config_byte(dev, 0x5a, &scr1); 1254 pci_write_config_byte(dev, 0x5b, scr2); 1255 } else 1256 pci_read_config_byte(dev, 0x5a, &scr1); 1257 1258 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; 1259} 1260 1261static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) 1262{ 1263 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 1264 u8 chip_type = info->chip_type; 1265 1266 /* Cache the channel's MISC. control registers' offset */ 1267 hwif->select_data = hwif->channel ? 0x54 : 0x50; 1268 1269 /* 1270 * HPT3xxN chips have some complications: 1271 * 1272 * - on 33 MHz PCI we must clock switch 1273 * - on 66 MHz PCI we must NOT use the PCI clock 1274 */ 1275 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) { 1276 /* 1277 * Clock is shared between the channels, 1278 * so we'll have to serialize them... :-( 1279 */ 1280 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE; 1281 hwif->rw_disk = &hpt3xxn_rw_disk; 1282 } 1283} 1284 1285static int __devinit init_dma_hpt366(ide_hwif_t *hwif, 1286 const struct ide_port_info *d) 1287{ 1288 struct pci_dev *dev = to_pci_dev(hwif->dev); 1289 unsigned long flags, base = ide_pci_dma_base(hwif, d); 1290 u8 dma_old, dma_new, masterdma = 0, slavedma = 0; 1291 1292 if (base == 0) 1293 return -1; 1294 1295 hwif->dma_base = base; 1296 1297 if (ide_pci_check_simplex(hwif, d) < 0) 1298 return -1; 1299 1300 if (ide_pci_set_master(dev, d->name) < 0) 1301 return -1; 1302 1303 dma_old = inb(base + 2); 1304 1305 local_irq_save(flags); 1306 1307 dma_new = dma_old; 1308 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); 1309 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); 1310 1311 if (masterdma & 0x30) dma_new |= 0x20; 1312 if ( slavedma & 0x30) dma_new |= 0x40; 1313 if (dma_new != dma_old) 1314 outb(dma_new, base + 2); 1315 1316 local_irq_restore(flags); 1317 1318 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", 1319 hwif->name, base, base + 7); 1320 1321 hwif->extra_base = base + (hwif->channel ? 8 : 16); 1322 1323 if (ide_allocate_dma_engine(hwif)) 1324 return -1; 1325 1326 return 0; 1327} 1328 1329static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2) 1330{ 1331 if (dev2->irq != dev->irq) { 1332 /* FIXME: we need a core pci_set_interrupt() */ 1333 dev2->irq = dev->irq; 1334 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt " 1335 "fixed\n", pci_name(dev2)); 1336 } 1337} 1338 1339static void __devinit hpt371_init(struct pci_dev *dev) 1340{ 1341 u8 mcr1 = 0; 1342 1343 /* 1344 * HPT371 chips physically have only one channel, the secondary one, 1345 * but the primary channel registers do exist! Go figure... 1346 * So, we manually disable the non-existing channel here 1347 * (if the BIOS hasn't done this already). 1348 */ 1349 pci_read_config_byte(dev, 0x50, &mcr1); 1350 if (mcr1 & 0x04) 1351 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); 1352} 1353 1354static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2) 1355{ 1356 u8 mcr1 = 0, pin1 = 0, pin2 = 0; 1357 1358 /* 1359 * Now we'll have to force both channels enabled if 1360 * at least one of them has been enabled by BIOS... 1361 */ 1362 pci_read_config_byte(dev, 0x50, &mcr1); 1363 if (mcr1 & 0x30) 1364 pci_write_config_byte(dev, 0x50, mcr1 | 0x30); 1365 1366 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); 1367 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); 1368 1369 if (pin1 != pin2 && dev->irq == dev2->irq) { 1370 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, " 1371 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2); 1372 return 1; 1373 } 1374 1375 return 0; 1376} 1377 1378#define IDE_HFLAGS_HPT3XX \ 1379 (IDE_HFLAG_NO_ATAPI_DMA | \ 1380 IDE_HFLAG_OFF_BOARD) 1381 1382static const struct ide_port_ops hpt3xx_port_ops = { 1383 .set_pio_mode = hpt3xx_set_pio_mode, 1384 .set_dma_mode = hpt3xx_set_mode, 1385 .maskproc = hpt3xx_maskproc, 1386 .mdma_filter = hpt3xx_mdma_filter, 1387 .udma_filter = hpt3xx_udma_filter, 1388 .cable_detect = hpt3xx_cable_detect, 1389}; 1390 1391static const struct ide_dma_ops hpt37x_dma_ops = { 1392 .dma_host_set = ide_dma_host_set, 1393 .dma_setup = ide_dma_setup, 1394 .dma_start = ide_dma_start, 1395 .dma_end = hpt374_dma_end, 1396 .dma_test_irq = hpt374_dma_test_irq, 1397 .dma_lost_irq = ide_dma_lost_irq, 1398 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1399 .dma_sff_read_status = ide_dma_sff_read_status, 1400}; 1401 1402static const struct ide_dma_ops hpt370_dma_ops = { 1403 .dma_host_set = ide_dma_host_set, 1404 .dma_setup = ide_dma_setup, 1405 .dma_start = hpt370_dma_start, 1406 .dma_end = hpt370_dma_end, 1407 .dma_test_irq = ide_dma_test_irq, 1408 .dma_lost_irq = ide_dma_lost_irq, 1409 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1410 .dma_clear = hpt370_irq_timeout, 1411 .dma_sff_read_status = ide_dma_sff_read_status, 1412}; 1413 1414static const struct ide_dma_ops hpt36x_dma_ops = { 1415 .dma_host_set = ide_dma_host_set, 1416 .dma_setup = ide_dma_setup, 1417 .dma_start = ide_dma_start, 1418 .dma_end = ide_dma_end, 1419 .dma_test_irq = ide_dma_test_irq, 1420 .dma_lost_irq = hpt366_dma_lost_irq, 1421 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1422 .dma_sff_read_status = ide_dma_sff_read_status, 1423}; 1424 1425static const struct ide_port_info hpt366_chipsets[] __devinitdata = { 1426 { /* 0: HPT36x */ 1427 .name = DRV_NAME, 1428 .init_chipset = init_chipset_hpt366, 1429 .init_hwif = init_hwif_hpt366, 1430 .init_dma = init_dma_hpt366, 1431 /* 1432 * HPT36x chips have one channel per function and have 1433 * both channel enable bits located differently and visible 1434 * to both functions -- really stupid design decision... :-( 1435 * Bit 4 is for the primary channel, bit 5 for the secondary. 1436 */ 1437 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}}, 1438 .port_ops = &hpt3xx_port_ops, 1439 .dma_ops = &hpt36x_dma_ops, 1440 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE, 1441 .pio_mask = ATA_PIO4, 1442 .mwdma_mask = ATA_MWDMA2, 1443 }, 1444 { /* 1: HPT3xx */ 1445 .name = DRV_NAME, 1446 .init_chipset = init_chipset_hpt366, 1447 .init_hwif = init_hwif_hpt366, 1448 .init_dma = init_dma_hpt366, 1449 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1450 .port_ops = &hpt3xx_port_ops, 1451 .dma_ops = &hpt37x_dma_ops, 1452 .host_flags = IDE_HFLAGS_HPT3XX, 1453 .pio_mask = ATA_PIO4, 1454 .mwdma_mask = ATA_MWDMA2, 1455 } 1456}; 1457 1458/** 1459 * hpt366_init_one - called when an HPT366 is found 1460 * @dev: the hpt366 device 1461 * @id: the matching pci id 1462 * 1463 * Called when the PCI registration layer (or the IDE initialization) 1464 * finds a device matching our IDE device tables. 1465 */ 1466static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) 1467{ 1468 const struct hpt_info *info = NULL; 1469 struct hpt_info *dyn_info; 1470 struct pci_dev *dev2 = NULL; 1471 struct ide_port_info d; 1472 u8 idx = id->driver_data; 1473 u8 rev = dev->revision; 1474 int ret; 1475 1476 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1)) 1477 return -ENODEV; 1478 1479 switch (idx) { 1480 case 0: 1481 if (rev < 3) 1482 info = &hpt36x; 1483 else { 1484 switch (min_t(u8, rev, 6)) { 1485 case 3: info = &hpt370; break; 1486 case 4: info = &hpt370a; break; 1487 case 5: info = &hpt372; break; 1488 case 6: info = &hpt372n; break; 1489 } 1490 idx++; 1491 } 1492 break; 1493 case 1: 1494 info = (rev > 1) ? &hpt372n : &hpt372a; 1495 break; 1496 case 2: 1497 info = (rev > 1) ? &hpt302n : &hpt302; 1498 break; 1499 case 3: 1500 hpt371_init(dev); 1501 info = (rev > 1) ? &hpt371n : &hpt371; 1502 break; 1503 case 4: 1504 info = &hpt374; 1505 break; 1506 case 5: 1507 info = &hpt372n; 1508 break; 1509 } 1510 1511 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name); 1512 1513 d = hpt366_chipsets[min_t(u8, idx, 1)]; 1514 1515 d.udma_mask = info->udma_mask; 1516 1517 /* fixup ->dma_ops for HPT370/HPT370A */ 1518 if (info == &hpt370 || info == &hpt370a) 1519 d.dma_ops = &hpt370_dma_ops; 1520 1521 if (info == &hpt36x || info == &hpt374) 1522 dev2 = pci_get_slot(dev->bus, dev->devfn + 1); 1523 1524 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL); 1525 if (dyn_info == NULL) { 1526 printk(KERN_ERR "%s %s: out of memory!\n", 1527 d.name, pci_name(dev)); 1528 pci_dev_put(dev2); 1529 return -ENOMEM; 1530 } 1531 1532 /* 1533 * Copy everything from a static "template" structure 1534 * to just allocated per-chip hpt_info structure. 1535 */ 1536 memcpy(dyn_info, info, sizeof(*dyn_info)); 1537 1538 if (dev2) { 1539 memcpy(dyn_info + 1, info, sizeof(*dyn_info)); 1540 1541 if (info == &hpt374) 1542 hpt374_init(dev, dev2); 1543 else { 1544 if (hpt36x_init(dev, dev2)) 1545 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE; 1546 } 1547 1548 ret = ide_pci_init_two(dev, dev2, &d, dyn_info); 1549 if (ret < 0) { 1550 pci_dev_put(dev2); 1551 kfree(dyn_info); 1552 } 1553 return ret; 1554 } 1555 1556 ret = ide_pci_init_one(dev, &d, dyn_info); 1557 if (ret < 0) 1558 kfree(dyn_info); 1559 1560 return ret; 1561} 1562 1563static void __devexit hpt366_remove(struct pci_dev *dev) 1564{ 1565 struct ide_host *host = pci_get_drvdata(dev); 1566 struct ide_info *info = host->host_priv; 1567 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL; 1568 1569 ide_pci_remove(dev); 1570 pci_dev_put(dev2); 1571 kfree(info); 1572} 1573 1574static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = { 1575 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 }, 1576 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 }, 1577 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 }, 1578 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 }, 1579 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 }, 1580 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 }, 1581 { 0, }, 1582}; 1583MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl); 1584 1585static struct pci_driver hpt366_pci_driver = { 1586 .name = "HPT366_IDE", 1587 .id_table = hpt366_pci_tbl, 1588 .probe = hpt366_init_one, 1589 .remove = __devexit_p(hpt366_remove), 1590 .suspend = ide_pci_suspend, 1591 .resume = ide_pci_resume, 1592}; 1593 1594static int __init hpt366_ide_init(void) 1595{ 1596 return ide_pci_register_driver(&hpt366_pci_driver); 1597} 1598 1599static void __exit hpt366_ide_exit(void) 1600{ 1601 pci_unregister_driver(&hpt366_pci_driver); 1602} 1603 1604module_init(hpt366_ide_init); 1605module_exit(hpt366_ide_exit); 1606 1607MODULE_AUTHOR("Andre Hedrick"); 1608MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE"); 1609MODULE_LICENSE("GPL"); 1610