ide-dma-sff.c revision e6830a86c260d73c6f370aa7ed17ee6c71e5ee05
1#include <linux/types.h> 2#include <linux/kernel.h> 3#include <linux/ide.h> 4#include <linux/scatterlist.h> 5#include <linux/dma-mapping.h> 6#include <linux/io.h> 7 8/** 9 * config_drive_for_dma - attempt to activate IDE DMA 10 * @drive: the drive to place in DMA mode 11 * 12 * If the drive supports at least mode 2 DMA or UDMA of any kind 13 * then attempt to place it into DMA mode. Drives that are known to 14 * support DMA but predate the DMA properties or that are known 15 * to have DMA handling bugs are also set up appropriately based 16 * on the good/bad drive lists. 17 */ 18 19int config_drive_for_dma(ide_drive_t *drive) 20{ 21 ide_hwif_t *hwif = drive->hwif; 22 u16 *id = drive->id; 23 24 if (drive->media != ide_disk) { 25 if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) 26 return 0; 27 } 28 29 /* 30 * Enable DMA on any drive that has 31 * UltraDMA (mode 0/1/2/3/4/5/6) enabled 32 */ 33 if ((id[ATA_ID_FIELD_VALID] & 4) && 34 ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f)) 35 return 1; 36 37 /* 38 * Enable DMA on any drive that has mode2 DMA 39 * (multi or single) enabled 40 */ 41 if (id[ATA_ID_FIELD_VALID] & 2) /* regular DMA */ 42 if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 || 43 (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404) 44 return 1; 45 46 /* Consult the list of known "good" drives */ 47 if (ide_dma_good_drive(drive)) 48 return 1; 49 50 return 0; 51} 52 53u8 ide_dma_sff_read_status(ide_hwif_t *hwif) 54{ 55 unsigned long addr = hwif->dma_base + ATA_DMA_STATUS; 56 57 if (hwif->host_flags & IDE_HFLAG_MMIO) 58 return readb((void __iomem *)addr); 59 else 60 return inb(addr); 61} 62EXPORT_SYMBOL_GPL(ide_dma_sff_read_status); 63 64static void ide_dma_sff_write_status(ide_hwif_t *hwif, u8 val) 65{ 66 unsigned long addr = hwif->dma_base + ATA_DMA_STATUS; 67 68 if (hwif->host_flags & IDE_HFLAG_MMIO) 69 writeb(val, (void __iomem *)addr); 70 else 71 outb(val, addr); 72} 73 74/** 75 * ide_dma_host_set - Enable/disable DMA on a host 76 * @drive: drive to control 77 * 78 * Enable/disable DMA on an IDE controller following generic 79 * bus-mastering IDE controller behaviour. 80 */ 81 82void ide_dma_host_set(ide_drive_t *drive, int on) 83{ 84 ide_hwif_t *hwif = drive->hwif; 85 u8 unit = drive->dn & 1; 86 u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif); 87 88 if (on) 89 dma_stat |= (1 << (5 + unit)); 90 else 91 dma_stat &= ~(1 << (5 + unit)); 92 93 ide_dma_sff_write_status(hwif, dma_stat); 94} 95EXPORT_SYMBOL_GPL(ide_dma_host_set); 96 97/** 98 * ide_build_dmatable - build IDE DMA table 99 * 100 * ide_build_dmatable() prepares a dma request. We map the command 101 * to get the pci bus addresses of the buffers and then build up 102 * the PRD table that the IDE layer wants to be fed. 103 * 104 * Most chipsets correctly interpret a length of 0x0000 as 64KB, 105 * but at least one (e.g. CS5530) misinterprets it as zero (!). 106 * So we break the 64KB entry into two 32KB entries instead. 107 * 108 * Returns the number of built PRD entries if all went okay, 109 * returns 0 otherwise. 110 * 111 * May also be invoked from trm290.c 112 */ 113 114int ide_build_dmatable(ide_drive_t *drive, struct request *rq) 115{ 116 ide_hwif_t *hwif = drive->hwif; 117 __le32 *table = (__le32 *)hwif->dmatable_cpu; 118 unsigned int count = 0; 119 int i; 120 struct scatterlist *sg; 121 u8 is_trm290 = !!(hwif->host_flags & IDE_HFLAG_TRM290); 122 123 for_each_sg(hwif->sg_table, sg, hwif->sg_nents, i) { 124 u32 cur_addr, cur_len, xcount, bcount; 125 126 cur_addr = sg_dma_address(sg); 127 cur_len = sg_dma_len(sg); 128 129 /* 130 * Fill in the dma table, without crossing any 64kB boundaries. 131 * Most hardware requires 16-bit alignment of all blocks, 132 * but the trm290 requires 32-bit alignment. 133 */ 134 135 while (cur_len) { 136 if (count++ >= PRD_ENTRIES) 137 goto use_pio_instead; 138 139 bcount = 0x10000 - (cur_addr & 0xffff); 140 if (bcount > cur_len) 141 bcount = cur_len; 142 *table++ = cpu_to_le32(cur_addr); 143 xcount = bcount & 0xffff; 144 if (is_trm290) 145 xcount = ((xcount >> 2) - 1) << 16; 146 else if (xcount == 0x0000) { 147 if (count++ >= PRD_ENTRIES) 148 goto use_pio_instead; 149 *table++ = cpu_to_le32(0x8000); 150 *table++ = cpu_to_le32(cur_addr + 0x8000); 151 xcount = 0x8000; 152 } 153 *table++ = cpu_to_le32(xcount); 154 cur_addr += bcount; 155 cur_len -= bcount; 156 } 157 } 158 159 if (count) { 160 if (!is_trm290) 161 *--table |= cpu_to_le32(0x80000000); 162 return count; 163 } 164 165use_pio_instead: 166 printk(KERN_ERR "%s: %s\n", drive->name, 167 count ? "DMA table too small" : "empty DMA table?"); 168 169 ide_destroy_dmatable(drive); 170 171 return 0; /* revert to PIO for this request */ 172} 173EXPORT_SYMBOL_GPL(ide_build_dmatable); 174 175/** 176 * ide_dma_setup - begin a DMA phase 177 * @drive: target device 178 * 179 * Build an IDE DMA PRD (IDE speak for scatter gather table) 180 * and then set up the DMA transfer registers for a device 181 * that follows generic IDE PCI DMA behaviour. Controllers can 182 * override this function if they need to 183 * 184 * Returns 0 on success. If a PIO fallback is required then 1 185 * is returned. 186 */ 187 188int ide_dma_setup(ide_drive_t *drive) 189{ 190 ide_hwif_t *hwif = drive->hwif; 191 struct request *rq = hwif->rq; 192 unsigned int reading = rq_data_dir(rq) ? 0 : ATA_DMA_WR; 193 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 194 u8 dma_stat; 195 196 /* fall back to pio! */ 197 if (!ide_build_dmatable(drive, rq)) { 198 ide_map_sg(drive, rq); 199 return 1; 200 } 201 202 /* PRD table */ 203 if (mmio) 204 writel(hwif->dmatable_dma, 205 (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS)); 206 else 207 outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS); 208 209 /* specify r/w */ 210 if (mmio) 211 writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 212 else 213 outb(reading, hwif->dma_base + ATA_DMA_CMD); 214 215 /* read DMA status for INTR & ERROR flags */ 216 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif); 217 218 /* clear INTR & ERROR flags */ 219 ide_dma_sff_write_status(hwif, dma_stat | ATA_DMA_ERR | ATA_DMA_INTR); 220 221 drive->waiting_for_dma = 1; 222 return 0; 223} 224EXPORT_SYMBOL_GPL(ide_dma_setup); 225 226/** 227 * dma_timer_expiry - handle a DMA timeout 228 * @drive: Drive that timed out 229 * 230 * An IDE DMA transfer timed out. In the event of an error we ask 231 * the driver to resolve the problem, if a DMA transfer is still 232 * in progress we continue to wait (arguably we need to add a 233 * secondary 'I don't care what the drive thinks' timeout here) 234 * Finally if we have an interrupt we let it complete the I/O. 235 * But only one time - we clear expiry and if it's still not 236 * completed after WAIT_CMD, we error and retry in PIO. 237 * This can occur if an interrupt is lost or due to hang or bugs. 238 */ 239 240static int dma_timer_expiry(ide_drive_t *drive) 241{ 242 ide_hwif_t *hwif = drive->hwif; 243 u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif); 244 245 printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n", 246 drive->name, __func__, dma_stat); 247 248 if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ 249 return WAIT_CMD; 250 251 hwif->expiry = NULL; /* one free ride for now */ 252 253 if (dma_stat & ATA_DMA_ERR) /* ERROR */ 254 return -1; 255 256 if (dma_stat & ATA_DMA_ACTIVE) /* DMAing */ 257 return WAIT_CMD; 258 259 if (dma_stat & ATA_DMA_INTR) /* Got an Interrupt */ 260 return WAIT_CMD; 261 262 return 0; /* Status is unknown -- reset the bus */ 263} 264 265void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) 266{ 267 /* issue cmd to drive */ 268 ide_execute_command(drive, command, &ide_dma_intr, 2 * WAIT_CMD, 269 dma_timer_expiry); 270} 271EXPORT_SYMBOL_GPL(ide_dma_exec_cmd); 272 273void ide_dma_start(ide_drive_t *drive) 274{ 275 ide_hwif_t *hwif = drive->hwif; 276 u8 dma_cmd; 277 278 /* Note that this is done *after* the cmd has 279 * been issued to the drive, as per the BM-IDE spec. 280 * The Promise Ultra33 doesn't work correctly when 281 * we do this part before issuing the drive cmd. 282 */ 283 if (hwif->host_flags & IDE_HFLAG_MMIO) { 284 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 285 writeb(dma_cmd | ATA_DMA_START, 286 (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 287 } else { 288 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 289 outb(dma_cmd | ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD); 290 } 291 292 wmb(); 293} 294EXPORT_SYMBOL_GPL(ide_dma_start); 295 296/* returns 1 on error, 0 otherwise */ 297int ide_dma_end(ide_drive_t *drive) 298{ 299 ide_hwif_t *hwif = drive->hwif; 300 u8 dma_stat = 0, dma_cmd = 0, mask; 301 302 drive->waiting_for_dma = 0; 303 304 /* stop DMA */ 305 if (hwif->host_flags & IDE_HFLAG_MMIO) { 306 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 307 writeb(dma_cmd & ~ATA_DMA_START, 308 (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 309 } else { 310 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 311 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD); 312 } 313 314 /* get DMA status */ 315 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif); 316 317 /* clear INTR & ERROR bits */ 318 ide_dma_sff_write_status(hwif, dma_stat | ATA_DMA_ERR | ATA_DMA_INTR); 319 320 /* purge DMA mappings */ 321 ide_destroy_dmatable(drive); 322 wmb(); 323 324 /* verify good DMA status */ 325 mask = ATA_DMA_ACTIVE | ATA_DMA_ERR | ATA_DMA_INTR; 326 if ((dma_stat & mask) != ATA_DMA_INTR) 327 return 0x10 | dma_stat; 328 return 0; 329} 330EXPORT_SYMBOL_GPL(ide_dma_end); 331 332/* returns 1 if dma irq issued, 0 otherwise */ 333int ide_dma_test_irq(ide_drive_t *drive) 334{ 335 ide_hwif_t *hwif = drive->hwif; 336 u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif); 337 338 return (dma_stat & ATA_DMA_INTR) ? 1 : 0; 339} 340EXPORT_SYMBOL_GPL(ide_dma_test_irq); 341 342const struct ide_dma_ops sff_dma_ops = { 343 .dma_host_set = ide_dma_host_set, 344 .dma_setup = ide_dma_setup, 345 .dma_exec_cmd = ide_dma_exec_cmd, 346 .dma_start = ide_dma_start, 347 .dma_end = ide_dma_end, 348 .dma_test_irq = ide_dma_test_irq, 349 .dma_timeout = ide_dma_timeout, 350 .dma_lost_irq = ide_dma_lost_irq, 351 .dma_sff_read_status = ide_dma_sff_read_status, 352}; 353EXPORT_SYMBOL_GPL(sff_dma_ops); 354