ide-dma.c revision a5b7e70d787f528386eda025d3e38f545017f241
1/* 2 * linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000 3 * 4 * Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org> 5 * May be copied or modified under the terms of the GNU General Public License 6 */ 7 8/* 9 * Special Thanks to Mark for his Six years of work. 10 * 11 * Copyright (c) 1995-1998 Mark Lord 12 * May be copied or modified under the terms of the GNU General Public License 13 */ 14 15/* 16 * This module provides support for the bus-master IDE DMA functions 17 * of various PCI chipsets, including the Intel PIIX (i82371FB for 18 * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and 19 * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset) 20 * ("PIIX" stands for "PCI ISA IDE Xcellerator"). 21 * 22 * Pretty much the same code works for other IDE PCI bus-mastering chipsets. 23 * 24 * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). 25 * 26 * By default, DMA support is prepared for use, but is currently enabled only 27 * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single), 28 * or which are recognized as "good" (see table below). Drives with only mode0 29 * or mode1 (multi/single) DMA should also work with this chipset/driver 30 * (eg. MC2112A) but are not enabled by default. 31 * 32 * Use "hdparm -i" to view modes supported by a given drive. 33 * 34 * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling 35 * DMA support, but must be (re-)compiled against this kernel version or later. 36 * 37 * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting. 38 * If problems arise, ide.c will disable DMA operation after a few retries. 39 * This error recovery mechanism works and has been extremely well exercised. 40 * 41 * IDE drives, depending on their vintage, may support several different modes 42 * of DMA operation. The boot-time modes are indicated with a "*" in 43 * the "hdparm -i" listing, and can be changed with *knowledgeable* use of 44 * the "hdparm -X" feature. There is seldom a need to do this, as drives 45 * normally power-up with their "best" PIO/DMA modes enabled. 46 * 47 * Testing has been done with a rather extensive number of drives, 48 * with Quantum & Western Digital models generally outperforming the pack, 49 * and Fujitsu & Conner (and some Seagate which are really Conner) drives 50 * showing more lackluster throughput. 51 * 52 * Keep an eye on /var/adm/messages for "DMA disabled" messages. 53 * 54 * Some people have reported trouble with Intel Zappa motherboards. 55 * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0, 56 * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe 57 * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this). 58 * 59 * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for 60 * fixing the problem with the BIOS on some Acer motherboards. 61 * 62 * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing 63 * "TX" chipset compatibility and for providing patches for the "TX" chipset. 64 * 65 * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack 66 * at generic DMA -- his patches were referred to when preparing this code. 67 * 68 * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> 69 * for supplying a Promise UDMA board & WD UDMA drive for this work! 70 * 71 * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports. 72 * 73 * ATA-66/100 and recovery functions, I forgot the rest...... 74 * 75 */ 76 77#include <linux/module.h> 78#include <linux/types.h> 79#include <linux/kernel.h> 80#include <linux/timer.h> 81#include <linux/mm.h> 82#include <linux/interrupt.h> 83#include <linux/pci.h> 84#include <linux/init.h> 85#include <linux/ide.h> 86#include <linux/delay.h> 87#include <linux/scatterlist.h> 88 89#include <asm/io.h> 90#include <asm/irq.h> 91 92static const struct drive_list_entry drive_whitelist [] = { 93 94 { "Micropolis 2112A" , NULL }, 95 { "CONNER CTMA 4000" , NULL }, 96 { "CONNER CTT8000-A" , NULL }, 97 { "ST34342A" , NULL }, 98 { NULL , NULL } 99}; 100 101static const struct drive_list_entry drive_blacklist [] = { 102 103 { "WDC AC11000H" , NULL }, 104 { "WDC AC22100H" , NULL }, 105 { "WDC AC32500H" , NULL }, 106 { "WDC AC33100H" , NULL }, 107 { "WDC AC31600H" , NULL }, 108 { "WDC AC32100H" , "24.09P07" }, 109 { "WDC AC23200L" , "21.10N21" }, 110 { "Compaq CRD-8241B" , NULL }, 111 { "CRD-8400B" , NULL }, 112 { "CRD-8480B", NULL }, 113 { "CRD-8482B", NULL }, 114 { "CRD-84" , NULL }, 115 { "SanDisk SDP3B" , NULL }, 116 { "SanDisk SDP3B-64" , NULL }, 117 { "SANYO CD-ROM CRD" , NULL }, 118 { "HITACHI CDR-8" , NULL }, 119 { "HITACHI CDR-8335" , NULL }, 120 { "HITACHI CDR-8435" , NULL }, 121 { "Toshiba CD-ROM XM-6202B" , NULL }, 122 { "TOSHIBA CD-ROM XM-1702BC", NULL }, 123 { "CD-532E-A" , NULL }, 124 { "E-IDE CD-ROM CR-840", NULL }, 125 { "CD-ROM Drive/F5A", NULL }, 126 { "WPI CDD-820", NULL }, 127 { "SAMSUNG CD-ROM SC-148C", NULL }, 128 { "SAMSUNG CD-ROM SC", NULL }, 129 { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL }, 130 { "_NEC DV5800A", NULL }, 131 { "SAMSUNG CD-ROM SN-124", "N001" }, 132 { "Seagate STT20000A", NULL }, 133 { NULL , NULL } 134 135}; 136 137/** 138 * ide_dma_intr - IDE DMA interrupt handler 139 * @drive: the drive the interrupt is for 140 * 141 * Handle an interrupt completing a read/write DMA transfer on an 142 * IDE device 143 */ 144 145ide_startstop_t ide_dma_intr (ide_drive_t *drive) 146{ 147 u8 stat = 0, dma_stat = 0; 148 149 dma_stat = HWIF(drive)->ide_dma_end(drive); 150 stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ 151 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { 152 if (!dma_stat) { 153 struct request *rq = HWGROUP(drive)->rq; 154 155 if (rq->rq_disk) { 156 ide_driver_t *drv; 157 158 drv = *(ide_driver_t **)rq->rq_disk->private_data; 159 drv->end_request(drive, 1, rq->nr_sectors); 160 } else 161 ide_end_request(drive, 1, rq->nr_sectors); 162 return ide_stopped; 163 } 164 printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", 165 drive->name, dma_stat); 166 } 167 return ide_error(drive, "dma_intr", stat); 168} 169 170EXPORT_SYMBOL_GPL(ide_dma_intr); 171 172#ifdef CONFIG_BLK_DEV_IDEDMA_PCI 173/** 174 * ide_build_sglist - map IDE scatter gather for DMA I/O 175 * @drive: the drive to build the DMA table for 176 * @rq: the request holding the sg list 177 * 178 * Perform the PCI mapping magic necessary to access the source or 179 * target buffers of a request via PCI DMA. The lower layers of the 180 * kernel provide the necessary cache management so that we can 181 * operate in a portable fashion 182 */ 183 184int ide_build_sglist(ide_drive_t *drive, struct request *rq) 185{ 186 ide_hwif_t *hwif = HWIF(drive); 187 struct scatterlist *sg = hwif->sg_table; 188 189 BUG_ON((rq->cmd_type == REQ_TYPE_ATA_TASKFILE) && rq->nr_sectors > 256); 190 191 ide_map_sg(drive, rq); 192 193 if (rq_data_dir(rq) == READ) 194 hwif->sg_dma_direction = PCI_DMA_FROMDEVICE; 195 else 196 hwif->sg_dma_direction = PCI_DMA_TODEVICE; 197 198 return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction); 199} 200 201EXPORT_SYMBOL_GPL(ide_build_sglist); 202 203/** 204 * ide_build_dmatable - build IDE DMA table 205 * 206 * ide_build_dmatable() prepares a dma request. We map the command 207 * to get the pci bus addresses of the buffers and then build up 208 * the PRD table that the IDE layer wants to be fed. The code 209 * knows about the 64K wrap bug in the CS5530. 210 * 211 * Returns the number of built PRD entries if all went okay, 212 * returns 0 otherwise. 213 * 214 * May also be invoked from trm290.c 215 */ 216 217int ide_build_dmatable (ide_drive_t *drive, struct request *rq) 218{ 219 ide_hwif_t *hwif = HWIF(drive); 220 unsigned int *table = hwif->dmatable_cpu; 221 unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; 222 unsigned int count = 0; 223 int i; 224 struct scatterlist *sg; 225 226 hwif->sg_nents = i = ide_build_sglist(drive, rq); 227 228 if (!i) 229 return 0; 230 231 sg = hwif->sg_table; 232 while (i) { 233 u32 cur_addr; 234 u32 cur_len; 235 236 cur_addr = sg_dma_address(sg); 237 cur_len = sg_dma_len(sg); 238 239 /* 240 * Fill in the dma table, without crossing any 64kB boundaries. 241 * Most hardware requires 16-bit alignment of all blocks, 242 * but the trm290 requires 32-bit alignment. 243 */ 244 245 while (cur_len) { 246 if (count++ >= PRD_ENTRIES) { 247 printk(KERN_ERR "%s: DMA table too small\n", drive->name); 248 goto use_pio_instead; 249 } else { 250 u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); 251 252 if (bcount > cur_len) 253 bcount = cur_len; 254 *table++ = cpu_to_le32(cur_addr); 255 xcount = bcount & 0xffff; 256 if (is_trm290) 257 xcount = ((xcount >> 2) - 1) << 16; 258 if (xcount == 0x0000) { 259 /* 260 * Most chipsets correctly interpret a length of 0x0000 as 64KB, 261 * but at least one (e.g. CS5530) misinterprets it as zero (!). 262 * So here we break the 64KB entry into two 32KB entries instead. 263 */ 264 if (count++ >= PRD_ENTRIES) { 265 printk(KERN_ERR "%s: DMA table too small\n", drive->name); 266 goto use_pio_instead; 267 } 268 *table++ = cpu_to_le32(0x8000); 269 *table++ = cpu_to_le32(cur_addr + 0x8000); 270 xcount = 0x8000; 271 } 272 *table++ = cpu_to_le32(xcount); 273 cur_addr += bcount; 274 cur_len -= bcount; 275 } 276 } 277 278 sg++; 279 i--; 280 } 281 282 if (count) { 283 if (!is_trm290) 284 *--table |= cpu_to_le32(0x80000000); 285 return count; 286 } 287 printk(KERN_ERR "%s: empty DMA table?\n", drive->name); 288use_pio_instead: 289 pci_unmap_sg(hwif->pci_dev, 290 hwif->sg_table, 291 hwif->sg_nents, 292 hwif->sg_dma_direction); 293 return 0; /* revert to PIO for this request */ 294} 295 296EXPORT_SYMBOL_GPL(ide_build_dmatable); 297 298/** 299 * ide_destroy_dmatable - clean up DMA mapping 300 * @drive: The drive to unmap 301 * 302 * Teardown mappings after DMA has completed. This must be called 303 * after the completion of each use of ide_build_dmatable and before 304 * the next use of ide_build_dmatable. Failure to do so will cause 305 * an oops as only one mapping can be live for each target at a given 306 * time. 307 */ 308 309void ide_destroy_dmatable (ide_drive_t *drive) 310{ 311 struct pci_dev *dev = HWIF(drive)->pci_dev; 312 struct scatterlist *sg = HWIF(drive)->sg_table; 313 int nents = HWIF(drive)->sg_nents; 314 315 pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction); 316} 317 318EXPORT_SYMBOL_GPL(ide_destroy_dmatable); 319 320/** 321 * config_drive_for_dma - attempt to activate IDE DMA 322 * @drive: the drive to place in DMA mode 323 * 324 * If the drive supports at least mode 2 DMA or UDMA of any kind 325 * then attempt to place it into DMA mode. Drives that are known to 326 * support DMA but predate the DMA properties or that are known 327 * to have DMA handling bugs are also set up appropriately based 328 * on the good/bad drive lists. 329 */ 330 331static int config_drive_for_dma (ide_drive_t *drive) 332{ 333 ide_hwif_t *hwif = drive->hwif; 334 struct hd_driveid *id = drive->id; 335 336 /* consult the list of known "bad" drives */ 337 if (__ide_dma_bad_drive(drive)) 338 return -1; 339 340 if (drive->media != ide_disk && hwif->atapi_dma == 0) 341 return -1; 342 343 if ((id->capability & 1) && drive->autodma) { 344 /* 345 * Enable DMA on any drive that has 346 * UltraDMA (mode 0/1/2/3/4/5/6) enabled 347 */ 348 if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f)) 349 return 0; 350 /* 351 * Enable DMA on any drive that has mode2 DMA 352 * (multi or single) enabled 353 */ 354 if (id->field_valid & 2) /* regular DMA */ 355 if ((id->dma_mword & 0x404) == 0x404 || 356 (id->dma_1word & 0x404) == 0x404) 357 return 0; 358 359 /* Consult the list of known "good" drives */ 360 if (__ide_dma_good_drive(drive)) 361 return 0; 362 } 363 364 return -1; 365} 366 367/** 368 * dma_timer_expiry - handle a DMA timeout 369 * @drive: Drive that timed out 370 * 371 * An IDE DMA transfer timed out. In the event of an error we ask 372 * the driver to resolve the problem, if a DMA transfer is still 373 * in progress we continue to wait (arguably we need to add a 374 * secondary 'I don't care what the drive thinks' timeout here) 375 * Finally if we have an interrupt we let it complete the I/O. 376 * But only one time - we clear expiry and if it's still not 377 * completed after WAIT_CMD, we error and retry in PIO. 378 * This can occur if an interrupt is lost or due to hang or bugs. 379 */ 380 381static int dma_timer_expiry (ide_drive_t *drive) 382{ 383 ide_hwif_t *hwif = HWIF(drive); 384 u8 dma_stat = hwif->INB(hwif->dma_status); 385 386 printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", 387 drive->name, dma_stat); 388 389 if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ 390 return WAIT_CMD; 391 392 HWGROUP(drive)->expiry = NULL; /* one free ride for now */ 393 394 /* 1 dmaing, 2 error, 4 intr */ 395 if (dma_stat & 2) /* ERROR */ 396 return -1; 397 398 if (dma_stat & 1) /* DMAing */ 399 return WAIT_CMD; 400 401 if (dma_stat & 4) /* Got an Interrupt */ 402 return WAIT_CMD; 403 404 return 0; /* Status is unknown -- reset the bus */ 405} 406 407/** 408 * ide_dma_host_off - Generic DMA kill 409 * @drive: drive to control 410 * 411 * Perform the generic IDE controller DMA off operation. This 412 * works for most IDE bus mastering controllers 413 */ 414 415void ide_dma_host_off(ide_drive_t *drive) 416{ 417 ide_hwif_t *hwif = HWIF(drive); 418 u8 unit = (drive->select.b.unit & 0x01); 419 u8 dma_stat = hwif->INB(hwif->dma_status); 420 421 hwif->OUTB((dma_stat & ~(1<<(5+unit))), hwif->dma_status); 422} 423 424EXPORT_SYMBOL(ide_dma_host_off); 425 426/** 427 * ide_dma_off_quietly - Generic DMA kill 428 * @drive: drive to control 429 * 430 * Turn off the current DMA on this IDE controller. 431 */ 432 433void ide_dma_off_quietly(ide_drive_t *drive) 434{ 435 drive->using_dma = 0; 436 ide_toggle_bounce(drive, 0); 437 438 drive->hwif->dma_host_off(drive); 439} 440 441EXPORT_SYMBOL(ide_dma_off_quietly); 442#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ 443 444/** 445 * ide_dma_off - disable DMA on a device 446 * @drive: drive to disable DMA on 447 * 448 * Disable IDE DMA for a device on this IDE controller. 449 * Inform the user that DMA has been disabled. 450 */ 451 452void ide_dma_off(ide_drive_t *drive) 453{ 454 printk(KERN_INFO "%s: DMA disabled\n", drive->name); 455 drive->hwif->dma_off_quietly(drive); 456} 457 458EXPORT_SYMBOL(ide_dma_off); 459 460#ifdef CONFIG_BLK_DEV_IDEDMA_PCI 461/** 462 * ide_dma_host_on - Enable DMA on a host 463 * @drive: drive to enable for DMA 464 * 465 * Enable DMA on an IDE controller following generic bus mastering 466 * IDE controller behaviour 467 */ 468 469void ide_dma_host_on(ide_drive_t *drive) 470{ 471 if (drive->using_dma) { 472 ide_hwif_t *hwif = HWIF(drive); 473 u8 unit = (drive->select.b.unit & 0x01); 474 u8 dma_stat = hwif->INB(hwif->dma_status); 475 476 hwif->OUTB((dma_stat|(1<<(5+unit))), hwif->dma_status); 477 } 478} 479 480EXPORT_SYMBOL(ide_dma_host_on); 481 482/** 483 * __ide_dma_on - Enable DMA on a device 484 * @drive: drive to enable DMA on 485 * 486 * Enable IDE DMA for a device on this IDE controller. 487 */ 488 489int __ide_dma_on (ide_drive_t *drive) 490{ 491 /* consult the list of known "bad" drives */ 492 if (__ide_dma_bad_drive(drive)) 493 return 1; 494 495 drive->using_dma = 1; 496 ide_toggle_bounce(drive, 1); 497 498 drive->hwif->dma_host_on(drive); 499 500 return 0; 501} 502 503EXPORT_SYMBOL(__ide_dma_on); 504 505/** 506 * ide_dma_setup - begin a DMA phase 507 * @drive: target device 508 * 509 * Build an IDE DMA PRD (IDE speak for scatter gather table) 510 * and then set up the DMA transfer registers for a device 511 * that follows generic IDE PCI DMA behaviour. Controllers can 512 * override this function if they need to 513 * 514 * Returns 0 on success. If a PIO fallback is required then 1 515 * is returned. 516 */ 517 518int ide_dma_setup(ide_drive_t *drive) 519{ 520 ide_hwif_t *hwif = drive->hwif; 521 struct request *rq = HWGROUP(drive)->rq; 522 unsigned int reading; 523 u8 dma_stat; 524 525 if (rq_data_dir(rq)) 526 reading = 0; 527 else 528 reading = 1 << 3; 529 530 /* fall back to pio! */ 531 if (!ide_build_dmatable(drive, rq)) { 532 ide_map_sg(drive, rq); 533 return 1; 534 } 535 536 /* PRD table */ 537 if (hwif->mmio) 538 writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable); 539 else 540 outl(hwif->dmatable_dma, hwif->dma_prdtable); 541 542 /* specify r/w */ 543 hwif->OUTB(reading, hwif->dma_command); 544 545 /* read dma_status for INTR & ERROR flags */ 546 dma_stat = hwif->INB(hwif->dma_status); 547 548 /* clear INTR & ERROR flags */ 549 hwif->OUTB(dma_stat|6, hwif->dma_status); 550 drive->waiting_for_dma = 1; 551 return 0; 552} 553 554EXPORT_SYMBOL_GPL(ide_dma_setup); 555 556static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) 557{ 558 /* issue cmd to drive */ 559 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); 560} 561 562void ide_dma_start(ide_drive_t *drive) 563{ 564 ide_hwif_t *hwif = HWIF(drive); 565 u8 dma_cmd = hwif->INB(hwif->dma_command); 566 567 /* Note that this is done *after* the cmd has 568 * been issued to the drive, as per the BM-IDE spec. 569 * The Promise Ultra33 doesn't work correctly when 570 * we do this part before issuing the drive cmd. 571 */ 572 /* start DMA */ 573 hwif->OUTB(dma_cmd|1, hwif->dma_command); 574 hwif->dma = 1; 575 wmb(); 576} 577 578EXPORT_SYMBOL_GPL(ide_dma_start); 579 580/* returns 1 on error, 0 otherwise */ 581int __ide_dma_end (ide_drive_t *drive) 582{ 583 ide_hwif_t *hwif = HWIF(drive); 584 u8 dma_stat = 0, dma_cmd = 0; 585 586 drive->waiting_for_dma = 0; 587 /* get dma_command mode */ 588 dma_cmd = hwif->INB(hwif->dma_command); 589 /* stop DMA */ 590 hwif->OUTB(dma_cmd&~1, hwif->dma_command); 591 /* get DMA status */ 592 dma_stat = hwif->INB(hwif->dma_status); 593 /* clear the INTR & ERROR bits */ 594 hwif->OUTB(dma_stat|6, hwif->dma_status); 595 /* purge DMA mappings */ 596 ide_destroy_dmatable(drive); 597 /* verify good DMA status */ 598 hwif->dma = 0; 599 wmb(); 600 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; 601} 602 603EXPORT_SYMBOL(__ide_dma_end); 604 605/* returns 1 if dma irq issued, 0 otherwise */ 606static int __ide_dma_test_irq(ide_drive_t *drive) 607{ 608 ide_hwif_t *hwif = HWIF(drive); 609 u8 dma_stat = hwif->INB(hwif->dma_status); 610 611#if 0 /* do not set unless you know what you are doing */ 612 if (dma_stat & 4) { 613 u8 stat = hwif->INB(IDE_STATUS_REG); 614 hwif->OUTB(hwif->dma_status, dma_stat & 0xE4); 615 } 616#endif 617 /* return 1 if INTR asserted */ 618 if ((dma_stat & 4) == 4) 619 return 1; 620 if (!drive->waiting_for_dma) 621 printk(KERN_WARNING "%s: (%s) called while not waiting\n", 622 drive->name, __FUNCTION__); 623 return 0; 624} 625#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ 626 627int __ide_dma_bad_drive (ide_drive_t *drive) 628{ 629 struct hd_driveid *id = drive->id; 630 631 int blacklist = ide_in_drive_list(id, drive_blacklist); 632 if (blacklist) { 633 printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", 634 drive->name, id->model); 635 return blacklist; 636 } 637 return 0; 638} 639 640EXPORT_SYMBOL(__ide_dma_bad_drive); 641 642int __ide_dma_good_drive (ide_drive_t *drive) 643{ 644 struct hd_driveid *id = drive->id; 645 return ide_in_drive_list(id, drive_whitelist); 646} 647 648EXPORT_SYMBOL(__ide_dma_good_drive); 649 650static const u8 xfer_mode_bases[] = { 651 XFER_UDMA_0, 652 XFER_MW_DMA_0, 653 XFER_SW_DMA_0, 654}; 655 656static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base) 657{ 658 struct hd_driveid *id = drive->id; 659 ide_hwif_t *hwif = drive->hwif; 660 unsigned int mask = 0; 661 662 switch(base) { 663 case XFER_UDMA_0: 664 if ((id->field_valid & 4) == 0) 665 break; 666 667 mask = id->dma_ultra & hwif->ultra_mask; 668 669 if (hwif->udma_filter) 670 mask &= hwif->udma_filter(drive); 671 672 if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) 673 mask &= 0x07; 674 break; 675 case XFER_MW_DMA_0: 676 if (id->field_valid & 2) 677 mask = id->dma_mword & hwif->mwdma_mask; 678 break; 679 case XFER_SW_DMA_0: 680 if (id->field_valid & 2) { 681 mask = id->dma_1word & hwif->swdma_mask; 682 } else if (id->tDMA) { 683 /* 684 * ide_fix_driveid() doesn't convert ->tDMA to the 685 * CPU endianness so we need to do it here 686 */ 687 u8 mode = le16_to_cpu(id->tDMA); 688 689 /* 690 * if the mode is valid convert it to the mask 691 * (the maximum allowed mode is XFER_SW_DMA_2) 692 */ 693 if (mode <= 2) 694 mask = ((2 << mode) - 1) & hwif->swdma_mask; 695 } 696 break; 697 default: 698 BUG(); 699 break; 700 } 701 702 return mask; 703} 704 705/** 706 * ide_max_dma_mode - compute DMA speed 707 * @drive: IDE device 708 * 709 * Checks the drive capabilities and returns the speed to use 710 * for the DMA transfer. Returns 0 if the drive is incapable 711 * of DMA transfers. 712 */ 713 714u8 ide_max_dma_mode(ide_drive_t *drive) 715{ 716 ide_hwif_t *hwif = drive->hwif; 717 unsigned int mask; 718 int x, i; 719 u8 mode = 0; 720 721 if (drive->media != ide_disk && hwif->atapi_dma == 0) 722 return 0; 723 724 for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { 725 mask = ide_get_mode_mask(drive, xfer_mode_bases[i]); 726 x = fls(mask) - 1; 727 if (x >= 0) { 728 mode = xfer_mode_bases[i] + x; 729 break; 730 } 731 } 732 733 printk(KERN_DEBUG "%s: selected mode 0x%x\n", drive->name, mode); 734 735 return mode; 736} 737 738EXPORT_SYMBOL_GPL(ide_max_dma_mode); 739 740int ide_tune_dma(ide_drive_t *drive) 741{ 742 u8 speed; 743 744 if ((drive->id->capability & 1) == 0 || drive->autodma == 0) 745 return 0; 746 747 /* consult the list of known "bad" drives */ 748 if (__ide_dma_bad_drive(drive)) 749 return 0; 750 751 speed = ide_max_dma_mode(drive); 752 753 if (!speed) 754 return 0; 755 756 if (drive->hwif->speedproc(drive, speed)) 757 return 0; 758 759 return 1; 760} 761 762EXPORT_SYMBOL_GPL(ide_tune_dma); 763 764void ide_dma_verbose(ide_drive_t *drive) 765{ 766 struct hd_driveid *id = drive->id; 767 ide_hwif_t *hwif = HWIF(drive); 768 769 if (id->field_valid & 4) { 770 if ((id->dma_ultra >> 8) && (id->dma_mword >> 8)) 771 goto bug_dma_off; 772 if (id->dma_ultra & ((id->dma_ultra >> 8) & hwif->ultra_mask)) { 773 if (((id->dma_ultra >> 11) & 0x1F) && 774 eighty_ninty_three(drive)) { 775 if ((id->dma_ultra >> 15) & 1) { 776 printk(", UDMA(mode 7)"); 777 } else if ((id->dma_ultra >> 14) & 1) { 778 printk(", UDMA(133)"); 779 } else if ((id->dma_ultra >> 13) & 1) { 780 printk(", UDMA(100)"); 781 } else if ((id->dma_ultra >> 12) & 1) { 782 printk(", UDMA(66)"); 783 } else if ((id->dma_ultra >> 11) & 1) { 784 printk(", UDMA(44)"); 785 } else 786 goto mode_two; 787 } else { 788 mode_two: 789 if ((id->dma_ultra >> 10) & 1) { 790 printk(", UDMA(33)"); 791 } else if ((id->dma_ultra >> 9) & 1) { 792 printk(", UDMA(25)"); 793 } else if ((id->dma_ultra >> 8) & 1) { 794 printk(", UDMA(16)"); 795 } 796 } 797 } else { 798 printk(", (U)DMA"); /* Can be BIOS-enabled! */ 799 } 800 } else if (id->field_valid & 2) { 801 if ((id->dma_mword >> 8) && (id->dma_1word >> 8)) 802 goto bug_dma_off; 803 printk(", DMA"); 804 } else if (id->field_valid & 1) { 805 goto bug_dma_off; 806 } 807 return; 808bug_dma_off: 809 printk(", BUG DMA OFF"); 810 hwif->dma_off_quietly(drive); 811 return; 812} 813 814EXPORT_SYMBOL(ide_dma_verbose); 815 816int ide_set_dma(ide_drive_t *drive) 817{ 818 ide_hwif_t *hwif = drive->hwif; 819 int rc; 820 821 rc = hwif->ide_dma_check(drive); 822 823 switch(rc) { 824 case -1: /* DMA needs to be disabled */ 825 hwif->dma_off_quietly(drive); 826 return -1; 827 case 0: /* DMA needs to be enabled */ 828 return hwif->ide_dma_on(drive); 829 case 1: /* DMA setting cannot be changed */ 830 break; 831 default: 832 BUG(); 833 break; 834 } 835 836 return rc; 837} 838 839#ifdef CONFIG_BLK_DEV_IDEDMA_PCI 840void ide_dma_lost_irq (ide_drive_t *drive) 841{ 842 printk("%s: DMA interrupt recovery\n", drive->name); 843} 844 845EXPORT_SYMBOL(ide_dma_lost_irq); 846 847void ide_dma_timeout (ide_drive_t *drive) 848{ 849 ide_hwif_t *hwif = HWIF(drive); 850 851 printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); 852 853 if (hwif->ide_dma_test_irq(drive)) 854 return; 855 856 hwif->ide_dma_end(drive); 857} 858 859EXPORT_SYMBOL(ide_dma_timeout); 860 861/* 862 * Needed for allowing full modular support of ide-driver 863 */ 864static int ide_release_dma_engine(ide_hwif_t *hwif) 865{ 866 if (hwif->dmatable_cpu) { 867 pci_free_consistent(hwif->pci_dev, 868 PRD_ENTRIES * PRD_BYTES, 869 hwif->dmatable_cpu, 870 hwif->dmatable_dma); 871 hwif->dmatable_cpu = NULL; 872 } 873 return 1; 874} 875 876static int ide_release_iomio_dma(ide_hwif_t *hwif) 877{ 878 release_region(hwif->dma_base, 8); 879 if (hwif->extra_ports) 880 release_region(hwif->extra_base, hwif->extra_ports); 881 return 1; 882} 883 884/* 885 * Needed for allowing full modular support of ide-driver 886 */ 887int ide_release_dma(ide_hwif_t *hwif) 888{ 889 ide_release_dma_engine(hwif); 890 891 if (hwif->mmio) 892 return 1; 893 else 894 return ide_release_iomio_dma(hwif); 895} 896 897static int ide_allocate_dma_engine(ide_hwif_t *hwif) 898{ 899 hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev, 900 PRD_ENTRIES * PRD_BYTES, 901 &hwif->dmatable_dma); 902 903 if (hwif->dmatable_cpu) 904 return 0; 905 906 printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n", 907 hwif->cds->name); 908 909 return 1; 910} 911 912static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) 913{ 914 printk(KERN_INFO " %s: MMIO-DMA ", hwif->name); 915 916 hwif->dma_base = base; 917 918 if(hwif->mate) 919 hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base; 920 else 921 hwif->dma_master = base; 922 return 0; 923} 924 925static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) 926{ 927 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx", 928 hwif->name, base, base + ports - 1); 929 930 if (!request_region(base, ports, hwif->name)) { 931 printk(" -- Error, ports in use.\n"); 932 return 1; 933 } 934 935 hwif->dma_base = base; 936 937 if (hwif->cds->extra) { 938 hwif->extra_base = base + (hwif->channel ? 8 : 16); 939 940 if (!hwif->mate || !hwif->mate->extra_ports) { 941 if (!request_region(hwif->extra_base, 942 hwif->cds->extra, hwif->cds->name)) { 943 printk(" -- Error, extra ports in use.\n"); 944 release_region(base, ports); 945 return 1; 946 } 947 hwif->extra_ports = hwif->cds->extra; 948 } 949 } 950 951 if(hwif->mate) 952 hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base:base; 953 else 954 hwif->dma_master = base; 955 return 0; 956} 957 958static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports) 959{ 960 if (hwif->mmio) 961 return ide_mapped_mmio_dma(hwif, base,ports); 962 963 return ide_iomio_dma(hwif, base, ports); 964} 965 966/* 967 * This can be called for a dynamically installed interface. Don't __init it 968 */ 969void ide_setup_dma (ide_hwif_t *hwif, unsigned long dma_base, unsigned int num_ports) 970{ 971 if (ide_dma_iobase(hwif, dma_base, num_ports)) 972 return; 973 974 if (ide_allocate_dma_engine(hwif)) { 975 ide_release_dma(hwif); 976 return; 977 } 978 979 if (!(hwif->dma_command)) 980 hwif->dma_command = hwif->dma_base; 981 if (!(hwif->dma_vendor1)) 982 hwif->dma_vendor1 = (hwif->dma_base + 1); 983 if (!(hwif->dma_status)) 984 hwif->dma_status = (hwif->dma_base + 2); 985 if (!(hwif->dma_vendor3)) 986 hwif->dma_vendor3 = (hwif->dma_base + 3); 987 if (!(hwif->dma_prdtable)) 988 hwif->dma_prdtable = (hwif->dma_base + 4); 989 990 if (!hwif->dma_off_quietly) 991 hwif->dma_off_quietly = &ide_dma_off_quietly; 992 if (!hwif->dma_host_off) 993 hwif->dma_host_off = &ide_dma_host_off; 994 if (!hwif->ide_dma_on) 995 hwif->ide_dma_on = &__ide_dma_on; 996 if (!hwif->dma_host_on) 997 hwif->dma_host_on = &ide_dma_host_on; 998 if (!hwif->ide_dma_check) 999 hwif->ide_dma_check = &config_drive_for_dma; 1000 if (!hwif->dma_setup) 1001 hwif->dma_setup = &ide_dma_setup; 1002 if (!hwif->dma_exec_cmd) 1003 hwif->dma_exec_cmd = &ide_dma_exec_cmd; 1004 if (!hwif->dma_start) 1005 hwif->dma_start = &ide_dma_start; 1006 if (!hwif->ide_dma_end) 1007 hwif->ide_dma_end = &__ide_dma_end; 1008 if (!hwif->ide_dma_test_irq) 1009 hwif->ide_dma_test_irq = &__ide_dma_test_irq; 1010 if (!hwif->dma_timeout) 1011 hwif->dma_timeout = &ide_dma_timeout; 1012 if (!hwif->dma_lost_irq) 1013 hwif->dma_lost_irq = &ide_dma_lost_irq; 1014 1015 if (hwif->chipset != ide_trm290) { 1016 u8 dma_stat = hwif->INB(hwif->dma_status); 1017 printk(", BIOS settings: %s:%s, %s:%s", 1018 hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio", 1019 hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio"); 1020 } 1021 printk("\n"); 1022 1023 BUG_ON(!hwif->dma_master); 1024} 1025 1026EXPORT_SYMBOL_GPL(ide_setup_dma); 1027#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ 1028