ide-dma.c revision b73c7ee25da6133f97f47ffd3557288417da7c76
1/* 2 * IDE DMA support (including IDE PCI BM-DMA). 3 * 4 * Copyright (C) 1995-1998 Mark Lord 5 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 6 * Copyright (C) 2004, 2007 Bartlomiej Zolnierkiewicz 7 * 8 * May be copied or modified under the terms of the GNU General Public License 9 * 10 * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). 11 */ 12 13/* 14 * Special Thanks to Mark for his Six years of work. 15 */ 16 17/* 18 * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for 19 * fixing the problem with the BIOS on some Acer motherboards. 20 * 21 * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing 22 * "TX" chipset compatibility and for providing patches for the "TX" chipset. 23 * 24 * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack 25 * at generic DMA -- his patches were referred to when preparing this code. 26 * 27 * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> 28 * for supplying a Promise UDMA board & WD UDMA drive for this work! 29 */ 30 31#include <linux/module.h> 32#include <linux/types.h> 33#include <linux/kernel.h> 34#include <linux/timer.h> 35#include <linux/mm.h> 36#include <linux/interrupt.h> 37#include <linux/pci.h> 38#include <linux/init.h> 39#include <linux/ide.h> 40#include <linux/delay.h> 41#include <linux/scatterlist.h> 42#include <linux/dma-mapping.h> 43 44#include <asm/io.h> 45#include <asm/irq.h> 46 47static const struct drive_list_entry drive_whitelist [] = { 48 49 { "Micropolis 2112A" , NULL }, 50 { "CONNER CTMA 4000" , NULL }, 51 { "CONNER CTT8000-A" , NULL }, 52 { "ST34342A" , NULL }, 53 { NULL , NULL } 54}; 55 56static const struct drive_list_entry drive_blacklist [] = { 57 58 { "WDC AC11000H" , NULL }, 59 { "WDC AC22100H" , NULL }, 60 { "WDC AC32500H" , NULL }, 61 { "WDC AC33100H" , NULL }, 62 { "WDC AC31600H" , NULL }, 63 { "WDC AC32100H" , "24.09P07" }, 64 { "WDC AC23200L" , "21.10N21" }, 65 { "Compaq CRD-8241B" , NULL }, 66 { "CRD-8400B" , NULL }, 67 { "CRD-8480B", NULL }, 68 { "CRD-8482B", NULL }, 69 { "CRD-84" , NULL }, 70 { "SanDisk SDP3B" , NULL }, 71 { "SanDisk SDP3B-64" , NULL }, 72 { "SANYO CD-ROM CRD" , NULL }, 73 { "HITACHI CDR-8" , NULL }, 74 { "HITACHI CDR-8335" , NULL }, 75 { "HITACHI CDR-8435" , NULL }, 76 { "Toshiba CD-ROM XM-6202B" , NULL }, 77 { "TOSHIBA CD-ROM XM-1702BC", NULL }, 78 { "CD-532E-A" , NULL }, 79 { "E-IDE CD-ROM CR-840", NULL }, 80 { "CD-ROM Drive/F5A", NULL }, 81 { "WPI CDD-820", NULL }, 82 { "SAMSUNG CD-ROM SC-148C", NULL }, 83 { "SAMSUNG CD-ROM SC", NULL }, 84 { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL }, 85 { "_NEC DV5800A", NULL }, 86 { "SAMSUNG CD-ROM SN-124", "N001" }, 87 { "Seagate STT20000A", NULL }, 88 { "CD-ROM CDR_U200", "1.09" }, 89 { NULL , NULL } 90 91}; 92 93/** 94 * ide_dma_intr - IDE DMA interrupt handler 95 * @drive: the drive the interrupt is for 96 * 97 * Handle an interrupt completing a read/write DMA transfer on an 98 * IDE device 99 */ 100 101ide_startstop_t ide_dma_intr (ide_drive_t *drive) 102{ 103 ide_hwif_t *hwif = drive->hwif; 104 u8 stat = 0, dma_stat = 0; 105 106 dma_stat = hwif->dma_ops->dma_end(drive); 107 stat = hwif->read_status(hwif); 108 109 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { 110 if (!dma_stat) { 111 struct request *rq = HWGROUP(drive)->rq; 112 113 task_end_request(drive, rq, stat); 114 return ide_stopped; 115 } 116 printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", 117 drive->name, dma_stat); 118 } 119 return ide_error(drive, "dma_intr", stat); 120} 121 122EXPORT_SYMBOL_GPL(ide_dma_intr); 123 124static int ide_dma_good_drive(ide_drive_t *drive) 125{ 126 return ide_in_drive_list(drive->id, drive_whitelist); 127} 128 129/** 130 * ide_build_sglist - map IDE scatter gather for DMA I/O 131 * @drive: the drive to build the DMA table for 132 * @rq: the request holding the sg list 133 * 134 * Perform the DMA mapping magic necessary to access the source or 135 * target buffers of a request via DMA. The lower layers of the 136 * kernel provide the necessary cache management so that we can 137 * operate in a portable fashion. 138 */ 139 140int ide_build_sglist(ide_drive_t *drive, struct request *rq) 141{ 142 ide_hwif_t *hwif = HWIF(drive); 143 struct scatterlist *sg = hwif->sg_table; 144 145 ide_map_sg(drive, rq); 146 147 if (rq_data_dir(rq) == READ) 148 hwif->sg_dma_direction = DMA_FROM_DEVICE; 149 else 150 hwif->sg_dma_direction = DMA_TO_DEVICE; 151 152 return dma_map_sg(hwif->dev, sg, hwif->sg_nents, 153 hwif->sg_dma_direction); 154} 155 156EXPORT_SYMBOL_GPL(ide_build_sglist); 157 158#ifdef CONFIG_BLK_DEV_IDEDMA_SFF 159/** 160 * ide_build_dmatable - build IDE DMA table 161 * 162 * ide_build_dmatable() prepares a dma request. We map the command 163 * to get the pci bus addresses of the buffers and then build up 164 * the PRD table that the IDE layer wants to be fed. The code 165 * knows about the 64K wrap bug in the CS5530. 166 * 167 * Returns the number of built PRD entries if all went okay, 168 * returns 0 otherwise. 169 * 170 * May also be invoked from trm290.c 171 */ 172 173int ide_build_dmatable (ide_drive_t *drive, struct request *rq) 174{ 175 ide_hwif_t *hwif = HWIF(drive); 176 unsigned int *table = hwif->dmatable_cpu; 177 unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; 178 unsigned int count = 0; 179 int i; 180 struct scatterlist *sg; 181 182 hwif->sg_nents = i = ide_build_sglist(drive, rq); 183 184 if (!i) 185 return 0; 186 187 sg = hwif->sg_table; 188 while (i) { 189 u32 cur_addr; 190 u32 cur_len; 191 192 cur_addr = sg_dma_address(sg); 193 cur_len = sg_dma_len(sg); 194 195 /* 196 * Fill in the dma table, without crossing any 64kB boundaries. 197 * Most hardware requires 16-bit alignment of all blocks, 198 * but the trm290 requires 32-bit alignment. 199 */ 200 201 while (cur_len) { 202 if (count++ >= PRD_ENTRIES) { 203 printk(KERN_ERR "%s: DMA table too small\n", drive->name); 204 goto use_pio_instead; 205 } else { 206 u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); 207 208 if (bcount > cur_len) 209 bcount = cur_len; 210 *table++ = cpu_to_le32(cur_addr); 211 xcount = bcount & 0xffff; 212 if (is_trm290) 213 xcount = ((xcount >> 2) - 1) << 16; 214 if (xcount == 0x0000) { 215 /* 216 * Most chipsets correctly interpret a length of 0x0000 as 64KB, 217 * but at least one (e.g. CS5530) misinterprets it as zero (!). 218 * So here we break the 64KB entry into two 32KB entries instead. 219 */ 220 if (count++ >= PRD_ENTRIES) { 221 printk(KERN_ERR "%s: DMA table too small\n", drive->name); 222 goto use_pio_instead; 223 } 224 *table++ = cpu_to_le32(0x8000); 225 *table++ = cpu_to_le32(cur_addr + 0x8000); 226 xcount = 0x8000; 227 } 228 *table++ = cpu_to_le32(xcount); 229 cur_addr += bcount; 230 cur_len -= bcount; 231 } 232 } 233 234 sg = sg_next(sg); 235 i--; 236 } 237 238 if (count) { 239 if (!is_trm290) 240 *--table |= cpu_to_le32(0x80000000); 241 return count; 242 } 243 244 printk(KERN_ERR "%s: empty DMA table?\n", drive->name); 245 246use_pio_instead: 247 ide_destroy_dmatable(drive); 248 249 return 0; /* revert to PIO for this request */ 250} 251 252EXPORT_SYMBOL_GPL(ide_build_dmatable); 253#endif 254 255/** 256 * ide_destroy_dmatable - clean up DMA mapping 257 * @drive: The drive to unmap 258 * 259 * Teardown mappings after DMA has completed. This must be called 260 * after the completion of each use of ide_build_dmatable and before 261 * the next use of ide_build_dmatable. Failure to do so will cause 262 * an oops as only one mapping can be live for each target at a given 263 * time. 264 */ 265 266void ide_destroy_dmatable (ide_drive_t *drive) 267{ 268 ide_hwif_t *hwif = drive->hwif; 269 270 dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->sg_nents, 271 hwif->sg_dma_direction); 272} 273 274EXPORT_SYMBOL_GPL(ide_destroy_dmatable); 275 276#ifdef CONFIG_BLK_DEV_IDEDMA_SFF 277/** 278 * config_drive_for_dma - attempt to activate IDE DMA 279 * @drive: the drive to place in DMA mode 280 * 281 * If the drive supports at least mode 2 DMA or UDMA of any kind 282 * then attempt to place it into DMA mode. Drives that are known to 283 * support DMA but predate the DMA properties or that are known 284 * to have DMA handling bugs are also set up appropriately based 285 * on the good/bad drive lists. 286 */ 287 288static int config_drive_for_dma (ide_drive_t *drive) 289{ 290 ide_hwif_t *hwif = drive->hwif; 291 struct hd_driveid *id = drive->id; 292 293 if (drive->media != ide_disk) { 294 if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) 295 return 0; 296 } 297 298 /* 299 * Enable DMA on any drive that has 300 * UltraDMA (mode 0/1/2/3/4/5/6) enabled 301 */ 302 if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f)) 303 return 1; 304 305 /* 306 * Enable DMA on any drive that has mode2 DMA 307 * (multi or single) enabled 308 */ 309 if (id->field_valid & 2) /* regular DMA */ 310 if ((id->dma_mword & 0x404) == 0x404 || 311 (id->dma_1word & 0x404) == 0x404) 312 return 1; 313 314 /* Consult the list of known "good" drives */ 315 if (ide_dma_good_drive(drive)) 316 return 1; 317 318 return 0; 319} 320 321/** 322 * dma_timer_expiry - handle a DMA timeout 323 * @drive: Drive that timed out 324 * 325 * An IDE DMA transfer timed out. In the event of an error we ask 326 * the driver to resolve the problem, if a DMA transfer is still 327 * in progress we continue to wait (arguably we need to add a 328 * secondary 'I don't care what the drive thinks' timeout here) 329 * Finally if we have an interrupt we let it complete the I/O. 330 * But only one time - we clear expiry and if it's still not 331 * completed after WAIT_CMD, we error and retry in PIO. 332 * This can occur if an interrupt is lost or due to hang or bugs. 333 */ 334 335static int dma_timer_expiry (ide_drive_t *drive) 336{ 337 ide_hwif_t *hwif = HWIF(drive); 338 u8 dma_stat = hwif->read_sff_dma_status(hwif); 339 340 printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", 341 drive->name, dma_stat); 342 343 if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ 344 return WAIT_CMD; 345 346 HWGROUP(drive)->expiry = NULL; /* one free ride for now */ 347 348 /* 1 dmaing, 2 error, 4 intr */ 349 if (dma_stat & 2) /* ERROR */ 350 return -1; 351 352 if (dma_stat & 1) /* DMAing */ 353 return WAIT_CMD; 354 355 if (dma_stat & 4) /* Got an Interrupt */ 356 return WAIT_CMD; 357 358 return 0; /* Status is unknown -- reset the bus */ 359} 360 361/** 362 * ide_dma_host_set - Enable/disable DMA on a host 363 * @drive: drive to control 364 * 365 * Enable/disable DMA on an IDE controller following generic 366 * bus-mastering IDE controller behaviour. 367 */ 368 369void ide_dma_host_set(ide_drive_t *drive, int on) 370{ 371 ide_hwif_t *hwif = HWIF(drive); 372 u8 unit = (drive->select.b.unit & 0x01); 373 u8 dma_stat = hwif->read_sff_dma_status(hwif); 374 375 if (on) 376 dma_stat |= (1 << (5 + unit)); 377 else 378 dma_stat &= ~(1 << (5 + unit)); 379 380 if (hwif->host_flags & IDE_HFLAG_MMIO) 381 writeb(dma_stat, 382 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); 383 else 384 outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS); 385} 386 387EXPORT_SYMBOL_GPL(ide_dma_host_set); 388#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ 389 390/** 391 * ide_dma_off_quietly - Generic DMA kill 392 * @drive: drive to control 393 * 394 * Turn off the current DMA on this IDE controller. 395 */ 396 397void ide_dma_off_quietly(ide_drive_t *drive) 398{ 399 drive->using_dma = 0; 400 ide_toggle_bounce(drive, 0); 401 402 drive->hwif->dma_ops->dma_host_set(drive, 0); 403} 404 405EXPORT_SYMBOL(ide_dma_off_quietly); 406 407/** 408 * ide_dma_off - disable DMA on a device 409 * @drive: drive to disable DMA on 410 * 411 * Disable IDE DMA for a device on this IDE controller. 412 * Inform the user that DMA has been disabled. 413 */ 414 415void ide_dma_off(ide_drive_t *drive) 416{ 417 printk(KERN_INFO "%s: DMA disabled\n", drive->name); 418 ide_dma_off_quietly(drive); 419} 420 421EXPORT_SYMBOL(ide_dma_off); 422 423/** 424 * ide_dma_on - Enable DMA on a device 425 * @drive: drive to enable DMA on 426 * 427 * Enable IDE DMA for a device on this IDE controller. 428 */ 429 430void ide_dma_on(ide_drive_t *drive) 431{ 432 drive->using_dma = 1; 433 ide_toggle_bounce(drive, 1); 434 435 drive->hwif->dma_ops->dma_host_set(drive, 1); 436} 437 438#ifdef CONFIG_BLK_DEV_IDEDMA_SFF 439/** 440 * ide_dma_setup - begin a DMA phase 441 * @drive: target device 442 * 443 * Build an IDE DMA PRD (IDE speak for scatter gather table) 444 * and then set up the DMA transfer registers for a device 445 * that follows generic IDE PCI DMA behaviour. Controllers can 446 * override this function if they need to 447 * 448 * Returns 0 on success. If a PIO fallback is required then 1 449 * is returned. 450 */ 451 452int ide_dma_setup(ide_drive_t *drive) 453{ 454 ide_hwif_t *hwif = drive->hwif; 455 struct request *rq = HWGROUP(drive)->rq; 456 unsigned int reading; 457 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 458 u8 dma_stat; 459 460 if (rq_data_dir(rq)) 461 reading = 0; 462 else 463 reading = 1 << 3; 464 465 /* fall back to pio! */ 466 if (!ide_build_dmatable(drive, rq)) { 467 ide_map_sg(drive, rq); 468 return 1; 469 } 470 471 /* PRD table */ 472 if (hwif->host_flags & IDE_HFLAG_MMIO) 473 writel(hwif->dmatable_dma, 474 (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS)); 475 else 476 outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS); 477 478 /* specify r/w */ 479 if (mmio) 480 writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 481 else 482 outb(reading, hwif->dma_base + ATA_DMA_CMD); 483 484 /* read DMA status for INTR & ERROR flags */ 485 dma_stat = hwif->read_sff_dma_status(hwif); 486 487 /* clear INTR & ERROR flags */ 488 if (mmio) 489 writeb(dma_stat | 6, 490 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); 491 else 492 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); 493 494 drive->waiting_for_dma = 1; 495 return 0; 496} 497 498EXPORT_SYMBOL_GPL(ide_dma_setup); 499 500void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) 501{ 502 /* issue cmd to drive */ 503 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); 504} 505EXPORT_SYMBOL_GPL(ide_dma_exec_cmd); 506 507void ide_dma_start(ide_drive_t *drive) 508{ 509 ide_hwif_t *hwif = drive->hwif; 510 u8 dma_cmd; 511 512 /* Note that this is done *after* the cmd has 513 * been issued to the drive, as per the BM-IDE spec. 514 * The Promise Ultra33 doesn't work correctly when 515 * we do this part before issuing the drive cmd. 516 */ 517 if (hwif->host_flags & IDE_HFLAG_MMIO) { 518 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 519 /* start DMA */ 520 writeb(dma_cmd | 1, 521 (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 522 } else { 523 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 524 outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD); 525 } 526 527 hwif->dma = 1; 528 wmb(); 529} 530 531EXPORT_SYMBOL_GPL(ide_dma_start); 532 533/* returns 1 on error, 0 otherwise */ 534int __ide_dma_end (ide_drive_t *drive) 535{ 536 ide_hwif_t *hwif = drive->hwif; 537 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 538 u8 dma_stat = 0, dma_cmd = 0; 539 540 drive->waiting_for_dma = 0; 541 542 if (mmio) { 543 /* get DMA command mode */ 544 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 545 /* stop DMA */ 546 writeb(dma_cmd & ~1, 547 (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 548 } else { 549 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 550 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); 551 } 552 553 /* get DMA status */ 554 dma_stat = hwif->read_sff_dma_status(hwif); 555 556 if (mmio) 557 /* clear the INTR & ERROR bits */ 558 writeb(dma_stat | 6, 559 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); 560 else 561 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); 562 563 /* purge DMA mappings */ 564 ide_destroy_dmatable(drive); 565 /* verify good DMA status */ 566 hwif->dma = 0; 567 wmb(); 568 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; 569} 570 571EXPORT_SYMBOL(__ide_dma_end); 572 573/* returns 1 if dma irq issued, 0 otherwise */ 574int ide_dma_test_irq(ide_drive_t *drive) 575{ 576 ide_hwif_t *hwif = HWIF(drive); 577 u8 dma_stat = hwif->read_sff_dma_status(hwif); 578 579 /* return 1 if INTR asserted */ 580 if ((dma_stat & 4) == 4) 581 return 1; 582 if (!drive->waiting_for_dma) 583 printk(KERN_WARNING "%s: (%s) called while not waiting\n", 584 drive->name, __func__); 585 return 0; 586} 587EXPORT_SYMBOL_GPL(ide_dma_test_irq); 588#else 589static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; } 590#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ 591 592int __ide_dma_bad_drive (ide_drive_t *drive) 593{ 594 struct hd_driveid *id = drive->id; 595 596 int blacklist = ide_in_drive_list(id, drive_blacklist); 597 if (blacklist) { 598 printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", 599 drive->name, id->model); 600 return blacklist; 601 } 602 return 0; 603} 604 605EXPORT_SYMBOL(__ide_dma_bad_drive); 606 607static const u8 xfer_mode_bases[] = { 608 XFER_UDMA_0, 609 XFER_MW_DMA_0, 610 XFER_SW_DMA_0, 611}; 612 613static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode) 614{ 615 struct hd_driveid *id = drive->id; 616 ide_hwif_t *hwif = drive->hwif; 617 const struct ide_port_ops *port_ops = hwif->port_ops; 618 unsigned int mask = 0; 619 620 switch(base) { 621 case XFER_UDMA_0: 622 if ((id->field_valid & 4) == 0) 623 break; 624 625 if (port_ops && port_ops->udma_filter) 626 mask = port_ops->udma_filter(drive); 627 else 628 mask = hwif->ultra_mask; 629 mask &= id->dma_ultra; 630 631 /* 632 * avoid false cable warning from eighty_ninty_three() 633 */ 634 if (req_mode > XFER_UDMA_2) { 635 if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) 636 mask &= 0x07; 637 } 638 break; 639 case XFER_MW_DMA_0: 640 if ((id->field_valid & 2) == 0) 641 break; 642 if (port_ops && port_ops->mdma_filter) 643 mask = port_ops->mdma_filter(drive); 644 else 645 mask = hwif->mwdma_mask; 646 mask &= id->dma_mword; 647 break; 648 case XFER_SW_DMA_0: 649 if (id->field_valid & 2) { 650 mask = id->dma_1word & hwif->swdma_mask; 651 } else if (id->tDMA) { 652 /* 653 * ide_fix_driveid() doesn't convert ->tDMA to the 654 * CPU endianness so we need to do it here 655 */ 656 u8 mode = le16_to_cpu(id->tDMA); 657 658 /* 659 * if the mode is valid convert it to the mask 660 * (the maximum allowed mode is XFER_SW_DMA_2) 661 */ 662 if (mode <= 2) 663 mask = ((2 << mode) - 1) & hwif->swdma_mask; 664 } 665 break; 666 default: 667 BUG(); 668 break; 669 } 670 671 return mask; 672} 673 674/** 675 * ide_find_dma_mode - compute DMA speed 676 * @drive: IDE device 677 * @req_mode: requested mode 678 * 679 * Checks the drive/host capabilities and finds the speed to use for 680 * the DMA transfer. The speed is then limited by the requested mode. 681 * 682 * Returns 0 if the drive/host combination is incapable of DMA transfers 683 * or if the requested mode is not a DMA mode. 684 */ 685 686u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode) 687{ 688 ide_hwif_t *hwif = drive->hwif; 689 unsigned int mask; 690 int x, i; 691 u8 mode = 0; 692 693 if (drive->media != ide_disk) { 694 if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) 695 return 0; 696 } 697 698 for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { 699 if (req_mode < xfer_mode_bases[i]) 700 continue; 701 mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode); 702 x = fls(mask) - 1; 703 if (x >= 0) { 704 mode = xfer_mode_bases[i] + x; 705 break; 706 } 707 } 708 709 if (hwif->chipset == ide_acorn && mode == 0) { 710 /* 711 * is this correct? 712 */ 713 if (ide_dma_good_drive(drive) && drive->id->eide_dma_time < 150) 714 mode = XFER_MW_DMA_1; 715 } 716 717 mode = min(mode, req_mode); 718 719 printk(KERN_INFO "%s: %s mode selected\n", drive->name, 720 mode ? ide_xfer_verbose(mode) : "no DMA"); 721 722 return mode; 723} 724 725EXPORT_SYMBOL_GPL(ide_find_dma_mode); 726 727static int ide_tune_dma(ide_drive_t *drive) 728{ 729 ide_hwif_t *hwif = drive->hwif; 730 u8 speed; 731 732 if (drive->nodma || (drive->id->capability & 1) == 0) 733 return 0; 734 735 /* consult the list of known "bad" drives */ 736 if (__ide_dma_bad_drive(drive)) 737 return 0; 738 739 if (ide_id_dma_bug(drive)) 740 return 0; 741 742 if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) 743 return config_drive_for_dma(drive); 744 745 speed = ide_max_dma_mode(drive); 746 747 if (!speed) 748 return 0; 749 750 if (ide_set_dma_mode(drive, speed)) 751 return 0; 752 753 return 1; 754} 755 756static int ide_dma_check(ide_drive_t *drive) 757{ 758 ide_hwif_t *hwif = drive->hwif; 759 int vdma = (hwif->host_flags & IDE_HFLAG_VDMA)? 1 : 0; 760 761 if (!vdma && ide_tune_dma(drive)) 762 return 0; 763 764 /* TODO: always do PIO fallback */ 765 if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) 766 return -1; 767 768 ide_set_max_pio(drive); 769 770 return vdma ? 0 : -1; 771} 772 773int ide_id_dma_bug(ide_drive_t *drive) 774{ 775 struct hd_driveid *id = drive->id; 776 777 if (id->field_valid & 4) { 778 if ((id->dma_ultra >> 8) && (id->dma_mword >> 8)) 779 goto err_out; 780 } else if (id->field_valid & 2) { 781 if ((id->dma_mword >> 8) && (id->dma_1word >> 8)) 782 goto err_out; 783 } 784 return 0; 785err_out: 786 printk(KERN_ERR "%s: bad DMA info in identify block\n", drive->name); 787 return 1; 788} 789 790int ide_set_dma(ide_drive_t *drive) 791{ 792 int rc; 793 794 /* 795 * Force DMAing for the beginning of the check. 796 * Some chipsets appear to do interesting 797 * things, if not checked and cleared. 798 * PARANOIA!!! 799 */ 800 ide_dma_off_quietly(drive); 801 802 rc = ide_dma_check(drive); 803 if (rc) 804 return rc; 805 806 ide_dma_on(drive); 807 808 return 0; 809} 810 811void ide_check_dma_crc(ide_drive_t *drive) 812{ 813 u8 mode; 814 815 ide_dma_off_quietly(drive); 816 drive->crc_count = 0; 817 mode = drive->current_speed; 818 /* 819 * Don't try non Ultra-DMA modes without iCRC's. Force the 820 * device to PIO and make the user enable SWDMA/MWDMA modes. 821 */ 822 if (mode > XFER_UDMA_0 && mode <= XFER_UDMA_7) 823 mode--; 824 else 825 mode = XFER_PIO_4; 826 ide_set_xfer_rate(drive, mode); 827 if (drive->current_speed >= XFER_SW_DMA_0) 828 ide_dma_on(drive); 829} 830 831#ifdef CONFIG_BLK_DEV_IDEDMA_SFF 832void ide_dma_lost_irq (ide_drive_t *drive) 833{ 834 printk("%s: DMA interrupt recovery\n", drive->name); 835} 836 837EXPORT_SYMBOL(ide_dma_lost_irq); 838 839void ide_dma_timeout (ide_drive_t *drive) 840{ 841 ide_hwif_t *hwif = HWIF(drive); 842 843 printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); 844 845 if (hwif->dma_ops->dma_test_irq(drive)) 846 return; 847 848 hwif->dma_ops->dma_end(drive); 849} 850 851EXPORT_SYMBOL(ide_dma_timeout); 852 853void ide_release_dma_engine(ide_hwif_t *hwif) 854{ 855 if (hwif->dmatable_cpu) { 856 struct pci_dev *pdev = to_pci_dev(hwif->dev); 857 858 pci_free_consistent(pdev, PRD_ENTRIES * PRD_BYTES, 859 hwif->dmatable_cpu, hwif->dmatable_dma); 860 hwif->dmatable_cpu = NULL; 861 } 862} 863 864int ide_allocate_dma_engine(ide_hwif_t *hwif) 865{ 866 struct pci_dev *pdev = to_pci_dev(hwif->dev); 867 868 hwif->dmatable_cpu = pci_alloc_consistent(pdev, 869 PRD_ENTRIES * PRD_BYTES, 870 &hwif->dmatable_dma); 871 872 if (hwif->dmatable_cpu) 873 return 0; 874 875 printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n", 876 hwif->name); 877 878 return 1; 879} 880EXPORT_SYMBOL_GPL(ide_allocate_dma_engine); 881 882const struct ide_dma_ops sff_dma_ops = { 883 .dma_host_set = ide_dma_host_set, 884 .dma_setup = ide_dma_setup, 885 .dma_exec_cmd = ide_dma_exec_cmd, 886 .dma_start = ide_dma_start, 887 .dma_end = __ide_dma_end, 888 .dma_test_irq = ide_dma_test_irq, 889 .dma_timeout = ide_dma_timeout, 890 .dma_lost_irq = ide_dma_lost_irq, 891}; 892EXPORT_SYMBOL_GPL(sff_dma_ops); 893#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ 894