ide-dma.c revision de23ec9ca82357e6d337a2263befb1a65cf19c83
1/* 2 * IDE DMA support (including IDE PCI BM-DMA). 3 * 4 * Copyright (C) 1995-1998 Mark Lord 5 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 6 * Copyright (C) 2004, 2007 Bartlomiej Zolnierkiewicz 7 * 8 * May be copied or modified under the terms of the GNU General Public License 9 * 10 * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). 11 */ 12 13/* 14 * Special Thanks to Mark for his Six years of work. 15 */ 16 17/* 18 * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for 19 * fixing the problem with the BIOS on some Acer motherboards. 20 * 21 * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing 22 * "TX" chipset compatibility and for providing patches for the "TX" chipset. 23 * 24 * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack 25 * at generic DMA -- his patches were referred to when preparing this code. 26 * 27 * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> 28 * for supplying a Promise UDMA board & WD UDMA drive for this work! 29 */ 30 31#include <linux/module.h> 32#include <linux/types.h> 33#include <linux/kernel.h> 34#include <linux/timer.h> 35#include <linux/mm.h> 36#include <linux/interrupt.h> 37#include <linux/pci.h> 38#include <linux/init.h> 39#include <linux/ide.h> 40#include <linux/delay.h> 41#include <linux/scatterlist.h> 42#include <linux/dma-mapping.h> 43 44#include <asm/io.h> 45#include <asm/irq.h> 46 47static const struct drive_list_entry drive_whitelist [] = { 48 49 { "Micropolis 2112A" , NULL }, 50 { "CONNER CTMA 4000" , NULL }, 51 { "CONNER CTT8000-A" , NULL }, 52 { "ST34342A" , NULL }, 53 { NULL , NULL } 54}; 55 56static const struct drive_list_entry drive_blacklist [] = { 57 58 { "WDC AC11000H" , NULL }, 59 { "WDC AC22100H" , NULL }, 60 { "WDC AC32500H" , NULL }, 61 { "WDC AC33100H" , NULL }, 62 { "WDC AC31600H" , NULL }, 63 { "WDC AC32100H" , "24.09P07" }, 64 { "WDC AC23200L" , "21.10N21" }, 65 { "Compaq CRD-8241B" , NULL }, 66 { "CRD-8400B" , NULL }, 67 { "CRD-8480B", NULL }, 68 { "CRD-8482B", NULL }, 69 { "CRD-84" , NULL }, 70 { "SanDisk SDP3B" , NULL }, 71 { "SanDisk SDP3B-64" , NULL }, 72 { "SANYO CD-ROM CRD" , NULL }, 73 { "HITACHI CDR-8" , NULL }, 74 { "HITACHI CDR-8335" , NULL }, 75 { "HITACHI CDR-8435" , NULL }, 76 { "Toshiba CD-ROM XM-6202B" , NULL }, 77 { "TOSHIBA CD-ROM XM-1702BC", NULL }, 78 { "CD-532E-A" , NULL }, 79 { "E-IDE CD-ROM CR-840", NULL }, 80 { "CD-ROM Drive/F5A", NULL }, 81 { "WPI CDD-820", NULL }, 82 { "SAMSUNG CD-ROM SC-148C", NULL }, 83 { "SAMSUNG CD-ROM SC", NULL }, 84 { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL }, 85 { "_NEC DV5800A", NULL }, 86 { "SAMSUNG CD-ROM SN-124", "N001" }, 87 { "Seagate STT20000A", NULL }, 88 { "CD-ROM CDR_U200", "1.09" }, 89 { NULL , NULL } 90 91}; 92 93/** 94 * ide_dma_intr - IDE DMA interrupt handler 95 * @drive: the drive the interrupt is for 96 * 97 * Handle an interrupt completing a read/write DMA transfer on an 98 * IDE device 99 */ 100 101ide_startstop_t ide_dma_intr (ide_drive_t *drive) 102{ 103 ide_hwif_t *hwif = drive->hwif; 104 u8 stat = 0, dma_stat = 0; 105 106 dma_stat = hwif->dma_ops->dma_end(drive); 107 stat = hwif->tp_ops->read_status(hwif); 108 109 if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | ATA_DRQ)) { 110 if (!dma_stat) { 111 struct request *rq = HWGROUP(drive)->rq; 112 113 task_end_request(drive, rq, stat); 114 return ide_stopped; 115 } 116 printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", 117 drive->name, dma_stat); 118 } 119 return ide_error(drive, "dma_intr", stat); 120} 121 122EXPORT_SYMBOL_GPL(ide_dma_intr); 123 124static int ide_dma_good_drive(ide_drive_t *drive) 125{ 126 return ide_in_drive_list(drive->id, drive_whitelist); 127} 128 129/** 130 * ide_build_sglist - map IDE scatter gather for DMA I/O 131 * @drive: the drive to build the DMA table for 132 * @rq: the request holding the sg list 133 * 134 * Perform the DMA mapping magic necessary to access the source or 135 * target buffers of a request via DMA. The lower layers of the 136 * kernel provide the necessary cache management so that we can 137 * operate in a portable fashion. 138 */ 139 140int ide_build_sglist(ide_drive_t *drive, struct request *rq) 141{ 142 ide_hwif_t *hwif = HWIF(drive); 143 struct scatterlist *sg = hwif->sg_table; 144 145 ide_map_sg(drive, rq); 146 147 if (rq_data_dir(rq) == READ) 148 hwif->sg_dma_direction = DMA_FROM_DEVICE; 149 else 150 hwif->sg_dma_direction = DMA_TO_DEVICE; 151 152 return dma_map_sg(hwif->dev, sg, hwif->sg_nents, 153 hwif->sg_dma_direction); 154} 155 156EXPORT_SYMBOL_GPL(ide_build_sglist); 157 158#ifdef CONFIG_BLK_DEV_IDEDMA_SFF 159/** 160 * ide_build_dmatable - build IDE DMA table 161 * 162 * ide_build_dmatable() prepares a dma request. We map the command 163 * to get the pci bus addresses of the buffers and then build up 164 * the PRD table that the IDE layer wants to be fed. The code 165 * knows about the 64K wrap bug in the CS5530. 166 * 167 * Returns the number of built PRD entries if all went okay, 168 * returns 0 otherwise. 169 * 170 * May also be invoked from trm290.c 171 */ 172 173int ide_build_dmatable (ide_drive_t *drive, struct request *rq) 174{ 175 ide_hwif_t *hwif = HWIF(drive); 176 __le32 *table = (__le32 *)hwif->dmatable_cpu; 177 unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; 178 unsigned int count = 0; 179 int i; 180 struct scatterlist *sg; 181 182 hwif->sg_nents = i = ide_build_sglist(drive, rq); 183 184 if (!i) 185 return 0; 186 187 sg = hwif->sg_table; 188 while (i) { 189 u32 cur_addr; 190 u32 cur_len; 191 192 cur_addr = sg_dma_address(sg); 193 cur_len = sg_dma_len(sg); 194 195 /* 196 * Fill in the dma table, without crossing any 64kB boundaries. 197 * Most hardware requires 16-bit alignment of all blocks, 198 * but the trm290 requires 32-bit alignment. 199 */ 200 201 while (cur_len) { 202 if (count++ >= PRD_ENTRIES) { 203 printk(KERN_ERR "%s: DMA table too small\n", drive->name); 204 goto use_pio_instead; 205 } else { 206 u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); 207 208 if (bcount > cur_len) 209 bcount = cur_len; 210 *table++ = cpu_to_le32(cur_addr); 211 xcount = bcount & 0xffff; 212 if (is_trm290) 213 xcount = ((xcount >> 2) - 1) << 16; 214 else if (xcount == 0x0000) { 215 /* 216 * Most chipsets correctly interpret a length of 0x0000 as 64KB, 217 * but at least one (e.g. CS5530) misinterprets it as zero (!). 218 * So here we break the 64KB entry into two 32KB entries instead. 219 */ 220 if (count++ >= PRD_ENTRIES) { 221 printk(KERN_ERR "%s: DMA table too small\n", drive->name); 222 goto use_pio_instead; 223 } 224 *table++ = cpu_to_le32(0x8000); 225 *table++ = cpu_to_le32(cur_addr + 0x8000); 226 xcount = 0x8000; 227 } 228 *table++ = cpu_to_le32(xcount); 229 cur_addr += bcount; 230 cur_len -= bcount; 231 } 232 } 233 234 sg = sg_next(sg); 235 i--; 236 } 237 238 if (count) { 239 if (!is_trm290) 240 *--table |= cpu_to_le32(0x80000000); 241 return count; 242 } 243 244 printk(KERN_ERR "%s: empty DMA table?\n", drive->name); 245 246use_pio_instead: 247 ide_destroy_dmatable(drive); 248 249 return 0; /* revert to PIO for this request */ 250} 251 252EXPORT_SYMBOL_GPL(ide_build_dmatable); 253#endif 254 255/** 256 * ide_destroy_dmatable - clean up DMA mapping 257 * @drive: The drive to unmap 258 * 259 * Teardown mappings after DMA has completed. This must be called 260 * after the completion of each use of ide_build_dmatable and before 261 * the next use of ide_build_dmatable. Failure to do so will cause 262 * an oops as only one mapping can be live for each target at a given 263 * time. 264 */ 265 266void ide_destroy_dmatable (ide_drive_t *drive) 267{ 268 ide_hwif_t *hwif = drive->hwif; 269 270 dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->sg_nents, 271 hwif->sg_dma_direction); 272} 273 274EXPORT_SYMBOL_GPL(ide_destroy_dmatable); 275 276#ifdef CONFIG_BLK_DEV_IDEDMA_SFF 277/** 278 * config_drive_for_dma - attempt to activate IDE DMA 279 * @drive: the drive to place in DMA mode 280 * 281 * If the drive supports at least mode 2 DMA or UDMA of any kind 282 * then attempt to place it into DMA mode. Drives that are known to 283 * support DMA but predate the DMA properties or that are known 284 * to have DMA handling bugs are also set up appropriately based 285 * on the good/bad drive lists. 286 */ 287 288static int config_drive_for_dma (ide_drive_t *drive) 289{ 290 ide_hwif_t *hwif = drive->hwif; 291 u16 *id = drive->id; 292 293 if (drive->media != ide_disk) { 294 if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) 295 return 0; 296 } 297 298 /* 299 * Enable DMA on any drive that has 300 * UltraDMA (mode 0/1/2/3/4/5/6) enabled 301 */ 302 if ((id[ATA_ID_FIELD_VALID] & 4) && 303 ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f)) 304 return 1; 305 306 /* 307 * Enable DMA on any drive that has mode2 DMA 308 * (multi or single) enabled 309 */ 310 if (id[ATA_ID_FIELD_VALID] & 2) /* regular DMA */ 311 if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 || 312 (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404) 313 return 1; 314 315 /* Consult the list of known "good" drives */ 316 if (ide_dma_good_drive(drive)) 317 return 1; 318 319 return 0; 320} 321 322/** 323 * dma_timer_expiry - handle a DMA timeout 324 * @drive: Drive that timed out 325 * 326 * An IDE DMA transfer timed out. In the event of an error we ask 327 * the driver to resolve the problem, if a DMA transfer is still 328 * in progress we continue to wait (arguably we need to add a 329 * secondary 'I don't care what the drive thinks' timeout here) 330 * Finally if we have an interrupt we let it complete the I/O. 331 * But only one time - we clear expiry and if it's still not 332 * completed after WAIT_CMD, we error and retry in PIO. 333 * This can occur if an interrupt is lost or due to hang or bugs. 334 */ 335 336static int dma_timer_expiry (ide_drive_t *drive) 337{ 338 ide_hwif_t *hwif = HWIF(drive); 339 u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); 340 341 printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", 342 drive->name, dma_stat); 343 344 if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ 345 return WAIT_CMD; 346 347 HWGROUP(drive)->expiry = NULL; /* one free ride for now */ 348 349 /* 1 dmaing, 2 error, 4 intr */ 350 if (dma_stat & 2) /* ERROR */ 351 return -1; 352 353 if (dma_stat & 1) /* DMAing */ 354 return WAIT_CMD; 355 356 if (dma_stat & 4) /* Got an Interrupt */ 357 return WAIT_CMD; 358 359 return 0; /* Status is unknown -- reset the bus */ 360} 361 362/** 363 * ide_dma_host_set - Enable/disable DMA on a host 364 * @drive: drive to control 365 * 366 * Enable/disable DMA on an IDE controller following generic 367 * bus-mastering IDE controller behaviour. 368 */ 369 370void ide_dma_host_set(ide_drive_t *drive, int on) 371{ 372 ide_hwif_t *hwif = HWIF(drive); 373 u8 unit = drive->dn & 1; 374 u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); 375 376 if (on) 377 dma_stat |= (1 << (5 + unit)); 378 else 379 dma_stat &= ~(1 << (5 + unit)); 380 381 if (hwif->host_flags & IDE_HFLAG_MMIO) 382 writeb(dma_stat, 383 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); 384 else 385 outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS); 386} 387 388EXPORT_SYMBOL_GPL(ide_dma_host_set); 389#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ 390 391/** 392 * ide_dma_off_quietly - Generic DMA kill 393 * @drive: drive to control 394 * 395 * Turn off the current DMA on this IDE controller. 396 */ 397 398void ide_dma_off_quietly(ide_drive_t *drive) 399{ 400 drive->dev_flags &= ~IDE_DFLAG_USING_DMA; 401 ide_toggle_bounce(drive, 0); 402 403 drive->hwif->dma_ops->dma_host_set(drive, 0); 404} 405 406EXPORT_SYMBOL(ide_dma_off_quietly); 407 408/** 409 * ide_dma_off - disable DMA on a device 410 * @drive: drive to disable DMA on 411 * 412 * Disable IDE DMA for a device on this IDE controller. 413 * Inform the user that DMA has been disabled. 414 */ 415 416void ide_dma_off(ide_drive_t *drive) 417{ 418 printk(KERN_INFO "%s: DMA disabled\n", drive->name); 419 ide_dma_off_quietly(drive); 420} 421 422EXPORT_SYMBOL(ide_dma_off); 423 424/** 425 * ide_dma_on - Enable DMA on a device 426 * @drive: drive to enable DMA on 427 * 428 * Enable IDE DMA for a device on this IDE controller. 429 */ 430 431void ide_dma_on(ide_drive_t *drive) 432{ 433 drive->dev_flags |= IDE_DFLAG_USING_DMA; 434 ide_toggle_bounce(drive, 1); 435 436 drive->hwif->dma_ops->dma_host_set(drive, 1); 437} 438 439#ifdef CONFIG_BLK_DEV_IDEDMA_SFF 440/** 441 * ide_dma_setup - begin a DMA phase 442 * @drive: target device 443 * 444 * Build an IDE DMA PRD (IDE speak for scatter gather table) 445 * and then set up the DMA transfer registers for a device 446 * that follows generic IDE PCI DMA behaviour. Controllers can 447 * override this function if they need to 448 * 449 * Returns 0 on success. If a PIO fallback is required then 1 450 * is returned. 451 */ 452 453int ide_dma_setup(ide_drive_t *drive) 454{ 455 ide_hwif_t *hwif = drive->hwif; 456 struct request *rq = HWGROUP(drive)->rq; 457 unsigned int reading; 458 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 459 u8 dma_stat; 460 461 if (rq_data_dir(rq)) 462 reading = 0; 463 else 464 reading = 1 << 3; 465 466 /* fall back to pio! */ 467 if (!ide_build_dmatable(drive, rq)) { 468 ide_map_sg(drive, rq); 469 return 1; 470 } 471 472 /* PRD table */ 473 if (hwif->host_flags & IDE_HFLAG_MMIO) 474 writel(hwif->dmatable_dma, 475 (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS)); 476 else 477 outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS); 478 479 /* specify r/w */ 480 if (mmio) 481 writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 482 else 483 outb(reading, hwif->dma_base + ATA_DMA_CMD); 484 485 /* read DMA status for INTR & ERROR flags */ 486 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); 487 488 /* clear INTR & ERROR flags */ 489 if (mmio) 490 writeb(dma_stat | 6, 491 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); 492 else 493 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); 494 495 drive->waiting_for_dma = 1; 496 return 0; 497} 498 499EXPORT_SYMBOL_GPL(ide_dma_setup); 500 501void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) 502{ 503 /* issue cmd to drive */ 504 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); 505} 506EXPORT_SYMBOL_GPL(ide_dma_exec_cmd); 507 508void ide_dma_start(ide_drive_t *drive) 509{ 510 ide_hwif_t *hwif = drive->hwif; 511 u8 dma_cmd; 512 513 /* Note that this is done *after* the cmd has 514 * been issued to the drive, as per the BM-IDE spec. 515 * The Promise Ultra33 doesn't work correctly when 516 * we do this part before issuing the drive cmd. 517 */ 518 if (hwif->host_flags & IDE_HFLAG_MMIO) { 519 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 520 /* start DMA */ 521 writeb(dma_cmd | 1, 522 (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 523 } else { 524 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 525 outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD); 526 } 527 528 wmb(); 529} 530 531EXPORT_SYMBOL_GPL(ide_dma_start); 532 533/* returns 1 on error, 0 otherwise */ 534int ide_dma_end(ide_drive_t *drive) 535{ 536 ide_hwif_t *hwif = drive->hwif; 537 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 538 u8 dma_stat = 0, dma_cmd = 0; 539 540 drive->waiting_for_dma = 0; 541 542 if (mmio) { 543 /* get DMA command mode */ 544 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 545 /* stop DMA */ 546 writeb(dma_cmd & ~1, 547 (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); 548 } else { 549 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 550 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); 551 } 552 553 /* get DMA status */ 554 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); 555 556 if (mmio) 557 /* clear the INTR & ERROR bits */ 558 writeb(dma_stat | 6, 559 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); 560 else 561 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); 562 563 /* purge DMA mappings */ 564 ide_destroy_dmatable(drive); 565 /* verify good DMA status */ 566 wmb(); 567 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; 568} 569EXPORT_SYMBOL_GPL(ide_dma_end); 570 571/* returns 1 if dma irq issued, 0 otherwise */ 572int ide_dma_test_irq(ide_drive_t *drive) 573{ 574 ide_hwif_t *hwif = HWIF(drive); 575 u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); 576 577 /* return 1 if INTR asserted */ 578 if ((dma_stat & 4) == 4) 579 return 1; 580 581 return 0; 582} 583EXPORT_SYMBOL_GPL(ide_dma_test_irq); 584#else 585static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; } 586#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ 587 588int __ide_dma_bad_drive (ide_drive_t *drive) 589{ 590 u16 *id = drive->id; 591 592 int blacklist = ide_in_drive_list(id, drive_blacklist); 593 if (blacklist) { 594 printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", 595 drive->name, (char *)&id[ATA_ID_PROD]); 596 return blacklist; 597 } 598 return 0; 599} 600 601EXPORT_SYMBOL(__ide_dma_bad_drive); 602 603static const u8 xfer_mode_bases[] = { 604 XFER_UDMA_0, 605 XFER_MW_DMA_0, 606 XFER_SW_DMA_0, 607}; 608 609static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode) 610{ 611 u16 *id = drive->id; 612 ide_hwif_t *hwif = drive->hwif; 613 const struct ide_port_ops *port_ops = hwif->port_ops; 614 unsigned int mask = 0; 615 616 switch(base) { 617 case XFER_UDMA_0: 618 if ((id[ATA_ID_FIELD_VALID] & 4) == 0) 619 break; 620 621 if (port_ops && port_ops->udma_filter) 622 mask = port_ops->udma_filter(drive); 623 else 624 mask = hwif->ultra_mask; 625 mask &= id[ATA_ID_UDMA_MODES]; 626 627 /* 628 * avoid false cable warning from eighty_ninty_three() 629 */ 630 if (req_mode > XFER_UDMA_2) { 631 if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) 632 mask &= 0x07; 633 } 634 break; 635 case XFER_MW_DMA_0: 636 if ((id[ATA_ID_FIELD_VALID] & 2) == 0) 637 break; 638 if (port_ops && port_ops->mdma_filter) 639 mask = port_ops->mdma_filter(drive); 640 else 641 mask = hwif->mwdma_mask; 642 mask &= id[ATA_ID_MWDMA_MODES]; 643 break; 644 case XFER_SW_DMA_0: 645 if (id[ATA_ID_FIELD_VALID] & 2) { 646 mask = id[ATA_ID_SWDMA_MODES] & hwif->swdma_mask; 647 } else if (id[ATA_ID_OLD_DMA_MODES] >> 8) { 648 u8 mode = id[ATA_ID_OLD_DMA_MODES] >> 8; 649 650 /* 651 * if the mode is valid convert it to the mask 652 * (the maximum allowed mode is XFER_SW_DMA_2) 653 */ 654 if (mode <= 2) 655 mask = ((2 << mode) - 1) & hwif->swdma_mask; 656 } 657 break; 658 default: 659 BUG(); 660 break; 661 } 662 663 return mask; 664} 665 666/** 667 * ide_find_dma_mode - compute DMA speed 668 * @drive: IDE device 669 * @req_mode: requested mode 670 * 671 * Checks the drive/host capabilities and finds the speed to use for 672 * the DMA transfer. The speed is then limited by the requested mode. 673 * 674 * Returns 0 if the drive/host combination is incapable of DMA transfers 675 * or if the requested mode is not a DMA mode. 676 */ 677 678u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode) 679{ 680 ide_hwif_t *hwif = drive->hwif; 681 unsigned int mask; 682 int x, i; 683 u8 mode = 0; 684 685 if (drive->media != ide_disk) { 686 if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) 687 return 0; 688 } 689 690 for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { 691 if (req_mode < xfer_mode_bases[i]) 692 continue; 693 mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode); 694 x = fls(mask) - 1; 695 if (x >= 0) { 696 mode = xfer_mode_bases[i] + x; 697 break; 698 } 699 } 700 701 if (hwif->chipset == ide_acorn && mode == 0) { 702 /* 703 * is this correct? 704 */ 705 if (ide_dma_good_drive(drive) && 706 drive->id[ATA_ID_EIDE_DMA_TIME] < 150) 707 mode = XFER_MW_DMA_1; 708 } 709 710 mode = min(mode, req_mode); 711 712 printk(KERN_INFO "%s: %s mode selected\n", drive->name, 713 mode ? ide_xfer_verbose(mode) : "no DMA"); 714 715 return mode; 716} 717 718EXPORT_SYMBOL_GPL(ide_find_dma_mode); 719 720static int ide_tune_dma(ide_drive_t *drive) 721{ 722 ide_hwif_t *hwif = drive->hwif; 723 u8 speed; 724 725 if (ata_id_has_dma(drive->id) == 0 || 726 (drive->dev_flags & IDE_DFLAG_NODMA)) 727 return 0; 728 729 /* consult the list of known "bad" drives */ 730 if (__ide_dma_bad_drive(drive)) 731 return 0; 732 733 if (ide_id_dma_bug(drive)) 734 return 0; 735 736 if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) 737 return config_drive_for_dma(drive); 738 739 speed = ide_max_dma_mode(drive); 740 741 if (!speed) 742 return 0; 743 744 if (ide_set_dma_mode(drive, speed)) 745 return 0; 746 747 return 1; 748} 749 750static int ide_dma_check(ide_drive_t *drive) 751{ 752 ide_hwif_t *hwif = drive->hwif; 753 754 if (ide_tune_dma(drive)) 755 return 0; 756 757 /* TODO: always do PIO fallback */ 758 if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) 759 return -1; 760 761 ide_set_max_pio(drive); 762 763 return -1; 764} 765 766int ide_id_dma_bug(ide_drive_t *drive) 767{ 768 u16 *id = drive->id; 769 770 if (id[ATA_ID_FIELD_VALID] & 4) { 771 if ((id[ATA_ID_UDMA_MODES] >> 8) && 772 (id[ATA_ID_MWDMA_MODES] >> 8)) 773 goto err_out; 774 } else if (id[ATA_ID_FIELD_VALID] & 2) { 775 if ((id[ATA_ID_MWDMA_MODES] >> 8) && 776 (id[ATA_ID_SWDMA_MODES] >> 8)) 777 goto err_out; 778 } 779 return 0; 780err_out: 781 printk(KERN_ERR "%s: bad DMA info in identify block\n", drive->name); 782 return 1; 783} 784 785int ide_set_dma(ide_drive_t *drive) 786{ 787 int rc; 788 789 /* 790 * Force DMAing for the beginning of the check. 791 * Some chipsets appear to do interesting 792 * things, if not checked and cleared. 793 * PARANOIA!!! 794 */ 795 ide_dma_off_quietly(drive); 796 797 rc = ide_dma_check(drive); 798 if (rc) 799 return rc; 800 801 ide_dma_on(drive); 802 803 return 0; 804} 805 806void ide_check_dma_crc(ide_drive_t *drive) 807{ 808 u8 mode; 809 810 ide_dma_off_quietly(drive); 811 drive->crc_count = 0; 812 mode = drive->current_speed; 813 /* 814 * Don't try non Ultra-DMA modes without iCRC's. Force the 815 * device to PIO and make the user enable SWDMA/MWDMA modes. 816 */ 817 if (mode > XFER_UDMA_0 && mode <= XFER_UDMA_7) 818 mode--; 819 else 820 mode = XFER_PIO_4; 821 ide_set_xfer_rate(drive, mode); 822 if (drive->current_speed >= XFER_SW_DMA_0) 823 ide_dma_on(drive); 824} 825 826void ide_dma_lost_irq(ide_drive_t *drive) 827{ 828 printk(KERN_ERR "%s: DMA interrupt recovery\n", drive->name); 829} 830EXPORT_SYMBOL_GPL(ide_dma_lost_irq); 831 832#ifdef CONFIG_BLK_DEV_IDEDMA_SFF 833void ide_dma_timeout (ide_drive_t *drive) 834{ 835 ide_hwif_t *hwif = HWIF(drive); 836 837 printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); 838 839 if (hwif->dma_ops->dma_test_irq(drive)) 840 return; 841 842 hwif->dma_ops->dma_end(drive); 843} 844 845EXPORT_SYMBOL(ide_dma_timeout); 846 847void ide_release_dma_engine(ide_hwif_t *hwif) 848{ 849 if (hwif->dmatable_cpu) { 850 struct pci_dev *pdev = to_pci_dev(hwif->dev); 851 852 pci_free_consistent(pdev, PRD_ENTRIES * PRD_BYTES, 853 hwif->dmatable_cpu, hwif->dmatable_dma); 854 hwif->dmatable_cpu = NULL; 855 } 856} 857 858int ide_allocate_dma_engine(ide_hwif_t *hwif) 859{ 860 struct pci_dev *pdev = to_pci_dev(hwif->dev); 861 862 hwif->dmatable_cpu = pci_alloc_consistent(pdev, 863 PRD_ENTRIES * PRD_BYTES, 864 &hwif->dmatable_dma); 865 866 if (hwif->dmatable_cpu) 867 return 0; 868 869 printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n", 870 hwif->name); 871 872 return 1; 873} 874EXPORT_SYMBOL_GPL(ide_allocate_dma_engine); 875 876const struct ide_dma_ops sff_dma_ops = { 877 .dma_host_set = ide_dma_host_set, 878 .dma_setup = ide_dma_setup, 879 .dma_exec_cmd = ide_dma_exec_cmd, 880 .dma_start = ide_dma_start, 881 .dma_end = ide_dma_end, 882 .dma_test_irq = ide_dma_test_irq, 883 .dma_timeout = ide_dma_timeout, 884 .dma_lost_irq = ide_dma_lost_irq, 885}; 886EXPORT_SYMBOL_GPL(sff_dma_ops); 887#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ 888