ide-iops.c revision cab7f8eda40d3e3e16b137c67cdddc2cf893c5d7
1/* 2 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org> 3 * Copyright (C) 2003 Red Hat <alan@redhat.com> 4 * 5 */ 6 7#include <linux/module.h> 8#include <linux/types.h> 9#include <linux/string.h> 10#include <linux/kernel.h> 11#include <linux/timer.h> 12#include <linux/mm.h> 13#include <linux/interrupt.h> 14#include <linux/major.h> 15#include <linux/errno.h> 16#include <linux/genhd.h> 17#include <linux/blkpg.h> 18#include <linux/slab.h> 19#include <linux/pci.h> 20#include <linux/delay.h> 21#include <linux/hdreg.h> 22#include <linux/ide.h> 23#include <linux/bitops.h> 24#include <linux/nmi.h> 25 26#include <asm/byteorder.h> 27#include <asm/irq.h> 28#include <asm/uaccess.h> 29#include <asm/io.h> 30 31/* 32 * Conventional PIO operations for ATA devices 33 */ 34 35static u8 ide_inb (unsigned long port) 36{ 37 return (u8) inb(port); 38} 39 40static void ide_outb (u8 val, unsigned long port) 41{ 42 outb(val, port); 43} 44 45static void ide_outbsync(ide_hwif_t *hwif, u8 addr, unsigned long port) 46{ 47 outb(addr, port); 48} 49 50void default_hwif_iops (ide_hwif_t *hwif) 51{ 52 hwif->OUTB = ide_outb; 53 hwif->OUTBSYNC = ide_outbsync; 54 hwif->INB = ide_inb; 55} 56 57/* 58 * MMIO operations, typically used for SATA controllers 59 */ 60 61static u8 ide_mm_inb (unsigned long port) 62{ 63 return (u8) readb((void __iomem *) port); 64} 65 66static void ide_mm_outb (u8 value, unsigned long port) 67{ 68 writeb(value, (void __iomem *) port); 69} 70 71static void ide_mm_outbsync(ide_hwif_t *hwif, u8 value, unsigned long port) 72{ 73 writeb(value, (void __iomem *) port); 74} 75 76void default_hwif_mmiops (ide_hwif_t *hwif) 77{ 78 hwif->OUTB = ide_mm_outb; 79 /* Most systems will need to override OUTBSYNC, alas however 80 this one is controller specific! */ 81 hwif->OUTBSYNC = ide_mm_outbsync; 82 hwif->INB = ide_mm_inb; 83} 84 85EXPORT_SYMBOL(default_hwif_mmiops); 86 87void SELECT_DRIVE (ide_drive_t *drive) 88{ 89 ide_hwif_t *hwif = drive->hwif; 90 const struct ide_port_ops *port_ops = hwif->port_ops; 91 92 if (port_ops && port_ops->selectproc) 93 port_ops->selectproc(drive); 94 95 hwif->OUTB(drive->select.all, hwif->io_ports.device_addr); 96} 97 98void SELECT_MASK(ide_drive_t *drive, int mask) 99{ 100 const struct ide_port_ops *port_ops = drive->hwif->port_ops; 101 102 if (port_ops && port_ops->maskproc) 103 port_ops->maskproc(drive, mask); 104} 105 106static u8 ide_read_sff_dma_status(ide_hwif_t *hwif) 107{ 108 if (hwif->host_flags & IDE_HFLAG_MMIO) 109 return readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); 110 else 111 return inb(hwif->dma_base + ATA_DMA_STATUS); 112} 113 114static void ide_tf_load(ide_drive_t *drive, ide_task_t *task) 115{ 116 ide_hwif_t *hwif = drive->hwif; 117 struct ide_io_ports *io_ports = &hwif->io_ports; 118 struct ide_taskfile *tf = &task->tf; 119 void (*tf_outb)(u8 addr, unsigned long port); 120 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 121 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF; 122 123 if (mmio) 124 tf_outb = ide_mm_outb; 125 else 126 tf_outb = ide_outb; 127 128 if (task->tf_flags & IDE_TFLAG_FLAGGED) 129 HIHI = 0xFF; 130 131 if (task->tf_flags & IDE_TFLAG_OUT_DATA) { 132 u16 data = (tf->hob_data << 8) | tf->data; 133 134 if (mmio) 135 writew(data, (void __iomem *)io_ports->data_addr); 136 else 137 outw(data, io_ports->data_addr); 138 } 139 140 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE) 141 tf_outb(tf->hob_feature, io_ports->feature_addr); 142 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT) 143 tf_outb(tf->hob_nsect, io_ports->nsect_addr); 144 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL) 145 tf_outb(tf->hob_lbal, io_ports->lbal_addr); 146 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM) 147 tf_outb(tf->hob_lbam, io_ports->lbam_addr); 148 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH) 149 tf_outb(tf->hob_lbah, io_ports->lbah_addr); 150 151 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE) 152 tf_outb(tf->feature, io_ports->feature_addr); 153 if (task->tf_flags & IDE_TFLAG_OUT_NSECT) 154 tf_outb(tf->nsect, io_ports->nsect_addr); 155 if (task->tf_flags & IDE_TFLAG_OUT_LBAL) 156 tf_outb(tf->lbal, io_ports->lbal_addr); 157 if (task->tf_flags & IDE_TFLAG_OUT_LBAM) 158 tf_outb(tf->lbam, io_ports->lbam_addr); 159 if (task->tf_flags & IDE_TFLAG_OUT_LBAH) 160 tf_outb(tf->lbah, io_ports->lbah_addr); 161 162 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) 163 tf_outb((tf->device & HIHI) | drive->select.all, 164 io_ports->device_addr); 165} 166 167static void ide_tf_read(ide_drive_t *drive, ide_task_t *task) 168{ 169 ide_hwif_t *hwif = drive->hwif; 170 struct ide_io_ports *io_ports = &hwif->io_ports; 171 struct ide_taskfile *tf = &task->tf; 172 void (*tf_outb)(u8 addr, unsigned long port); 173 u8 (*tf_inb)(unsigned long port); 174 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 175 176 if (mmio) { 177 tf_outb = ide_mm_outb; 178 tf_inb = ide_mm_inb; 179 } else { 180 tf_outb = ide_outb; 181 tf_inb = ide_inb; 182 } 183 184 if (task->tf_flags & IDE_TFLAG_IN_DATA) { 185 u16 data; 186 187 if (mmio) 188 data = readw((void __iomem *)io_ports->data_addr); 189 else 190 data = inw(io_ports->data_addr); 191 192 tf->data = data & 0xff; 193 tf->hob_data = (data >> 8) & 0xff; 194 } 195 196 /* be sure we're looking at the low order bits */ 197 tf_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); 198 199 if (task->tf_flags & IDE_TFLAG_IN_NSECT) 200 tf->nsect = tf_inb(io_ports->nsect_addr); 201 if (task->tf_flags & IDE_TFLAG_IN_LBAL) 202 tf->lbal = tf_inb(io_ports->lbal_addr); 203 if (task->tf_flags & IDE_TFLAG_IN_LBAM) 204 tf->lbam = tf_inb(io_ports->lbam_addr); 205 if (task->tf_flags & IDE_TFLAG_IN_LBAH) 206 tf->lbah = tf_inb(io_ports->lbah_addr); 207 if (task->tf_flags & IDE_TFLAG_IN_DEVICE) 208 tf->device = tf_inb(io_ports->device_addr); 209 210 if (task->tf_flags & IDE_TFLAG_LBA48) { 211 tf_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr); 212 213 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE) 214 tf->hob_feature = tf_inb(io_ports->feature_addr); 215 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT) 216 tf->hob_nsect = tf_inb(io_ports->nsect_addr); 217 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL) 218 tf->hob_lbal = tf_inb(io_ports->lbal_addr); 219 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM) 220 tf->hob_lbam = tf_inb(io_ports->lbam_addr); 221 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH) 222 tf->hob_lbah = tf_inb(io_ports->lbah_addr); 223 } 224} 225 226/* 227 * Some localbus EIDE interfaces require a special access sequence 228 * when using 32-bit I/O instructions to transfer data. We call this 229 * the "vlb_sync" sequence, which consists of three successive reads 230 * of the sector count register location, with interrupts disabled 231 * to ensure that the reads all happen together. 232 */ 233static void ata_vlb_sync(unsigned long port) 234{ 235 (void)inb(port); 236 (void)inb(port); 237 (void)inb(port); 238} 239 240/* 241 * This is used for most PIO data transfers *from* the IDE interface 242 * 243 * These routines will round up any request for an odd number of bytes, 244 * so if an odd len is specified, be sure that there's at least one 245 * extra byte allocated for the buffer. 246 */ 247static void ata_input_data(ide_drive_t *drive, struct request *rq, 248 void *buf, unsigned int len) 249{ 250 ide_hwif_t *hwif = drive->hwif; 251 struct ide_io_ports *io_ports = &hwif->io_ports; 252 unsigned long data_addr = io_ports->data_addr; 253 u8 io_32bit = drive->io_32bit; 254 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 255 256 len++; 257 258 if (io_32bit) { 259 unsigned long uninitialized_var(flags); 260 261 if ((io_32bit & 2) && !mmio) { 262 local_irq_save(flags); 263 ata_vlb_sync(io_ports->nsect_addr); 264 } 265 266 if (mmio) 267 __ide_mm_insl((void __iomem *)data_addr, buf, len / 4); 268 else 269 insl(data_addr, buf, len / 4); 270 271 if ((io_32bit & 2) && !mmio) 272 local_irq_restore(flags); 273 274 if ((len & 3) >= 2) { 275 if (mmio) 276 __ide_mm_insw((void __iomem *)data_addr, 277 (u8 *)buf + (len & ~3), 1); 278 else 279 insw(data_addr, (u8 *)buf + (len & ~3), 1); 280 } 281 } else { 282 if (mmio) 283 __ide_mm_insw((void __iomem *)data_addr, buf, len / 2); 284 else 285 insw(data_addr, buf, len / 2); 286 } 287} 288 289/* 290 * This is used for most PIO data transfers *to* the IDE interface 291 */ 292static void ata_output_data(ide_drive_t *drive, struct request *rq, 293 void *buf, unsigned int len) 294{ 295 ide_hwif_t *hwif = drive->hwif; 296 struct ide_io_ports *io_ports = &hwif->io_ports; 297 unsigned long data_addr = io_ports->data_addr; 298 u8 io_32bit = drive->io_32bit; 299 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 300 301 if (io_32bit) { 302 unsigned long uninitialized_var(flags); 303 304 if ((io_32bit & 2) && !mmio) { 305 local_irq_save(flags); 306 ata_vlb_sync(io_ports->nsect_addr); 307 } 308 309 if (mmio) 310 __ide_mm_outsl((void __iomem *)data_addr, buf, len / 4); 311 else 312 outsl(data_addr, buf, len / 4); 313 314 if ((io_32bit & 2) && !mmio) 315 local_irq_restore(flags); 316 317 if ((len & 3) >= 2) { 318 if (mmio) 319 __ide_mm_outsw((void __iomem *)data_addr, 320 (u8 *)buf + (len & ~3), 1); 321 else 322 outsw(data_addr, (u8 *)buf + (len & ~3), 1); 323 } 324 } else { 325 if (mmio) 326 __ide_mm_outsw((void __iomem *)data_addr, buf, len / 2); 327 else 328 outsw(data_addr, buf, len / 2); 329 } 330} 331 332void default_hwif_transport(ide_hwif_t *hwif) 333{ 334 hwif->read_sff_dma_status = ide_read_sff_dma_status; 335 336 hwif->tf_load = ide_tf_load; 337 hwif->tf_read = ide_tf_read; 338 339 hwif->input_data = ata_input_data; 340 hwif->output_data = ata_output_data; 341} 342 343void ide_fix_driveid (struct hd_driveid *id) 344{ 345#ifndef __LITTLE_ENDIAN 346# ifdef __BIG_ENDIAN 347 int i; 348 u16 *stringcast; 349 350 id->config = __le16_to_cpu(id->config); 351 id->cyls = __le16_to_cpu(id->cyls); 352 id->reserved2 = __le16_to_cpu(id->reserved2); 353 id->heads = __le16_to_cpu(id->heads); 354 id->track_bytes = __le16_to_cpu(id->track_bytes); 355 id->sector_bytes = __le16_to_cpu(id->sector_bytes); 356 id->sectors = __le16_to_cpu(id->sectors); 357 id->vendor0 = __le16_to_cpu(id->vendor0); 358 id->vendor1 = __le16_to_cpu(id->vendor1); 359 id->vendor2 = __le16_to_cpu(id->vendor2); 360 stringcast = (u16 *)&id->serial_no[0]; 361 for (i = 0; i < (20/2); i++) 362 stringcast[i] = __le16_to_cpu(stringcast[i]); 363 id->buf_type = __le16_to_cpu(id->buf_type); 364 id->buf_size = __le16_to_cpu(id->buf_size); 365 id->ecc_bytes = __le16_to_cpu(id->ecc_bytes); 366 stringcast = (u16 *)&id->fw_rev[0]; 367 for (i = 0; i < (8/2); i++) 368 stringcast[i] = __le16_to_cpu(stringcast[i]); 369 stringcast = (u16 *)&id->model[0]; 370 for (i = 0; i < (40/2); i++) 371 stringcast[i] = __le16_to_cpu(stringcast[i]); 372 id->dword_io = __le16_to_cpu(id->dword_io); 373 id->reserved50 = __le16_to_cpu(id->reserved50); 374 id->field_valid = __le16_to_cpu(id->field_valid); 375 id->cur_cyls = __le16_to_cpu(id->cur_cyls); 376 id->cur_heads = __le16_to_cpu(id->cur_heads); 377 id->cur_sectors = __le16_to_cpu(id->cur_sectors); 378 id->cur_capacity0 = __le16_to_cpu(id->cur_capacity0); 379 id->cur_capacity1 = __le16_to_cpu(id->cur_capacity1); 380 id->lba_capacity = __le32_to_cpu(id->lba_capacity); 381 id->dma_1word = __le16_to_cpu(id->dma_1word); 382 id->dma_mword = __le16_to_cpu(id->dma_mword); 383 id->eide_pio_modes = __le16_to_cpu(id->eide_pio_modes); 384 id->eide_dma_min = __le16_to_cpu(id->eide_dma_min); 385 id->eide_dma_time = __le16_to_cpu(id->eide_dma_time); 386 id->eide_pio = __le16_to_cpu(id->eide_pio); 387 id->eide_pio_iordy = __le16_to_cpu(id->eide_pio_iordy); 388 for (i = 0; i < 2; ++i) 389 id->words69_70[i] = __le16_to_cpu(id->words69_70[i]); 390 for (i = 0; i < 4; ++i) 391 id->words71_74[i] = __le16_to_cpu(id->words71_74[i]); 392 id->queue_depth = __le16_to_cpu(id->queue_depth); 393 for (i = 0; i < 4; ++i) 394 id->words76_79[i] = __le16_to_cpu(id->words76_79[i]); 395 id->major_rev_num = __le16_to_cpu(id->major_rev_num); 396 id->minor_rev_num = __le16_to_cpu(id->minor_rev_num); 397 id->command_set_1 = __le16_to_cpu(id->command_set_1); 398 id->command_set_2 = __le16_to_cpu(id->command_set_2); 399 id->cfsse = __le16_to_cpu(id->cfsse); 400 id->cfs_enable_1 = __le16_to_cpu(id->cfs_enable_1); 401 id->cfs_enable_2 = __le16_to_cpu(id->cfs_enable_2); 402 id->csf_default = __le16_to_cpu(id->csf_default); 403 id->dma_ultra = __le16_to_cpu(id->dma_ultra); 404 id->trseuc = __le16_to_cpu(id->trseuc); 405 id->trsEuc = __le16_to_cpu(id->trsEuc); 406 id->CurAPMvalues = __le16_to_cpu(id->CurAPMvalues); 407 id->mprc = __le16_to_cpu(id->mprc); 408 id->hw_config = __le16_to_cpu(id->hw_config); 409 id->acoustic = __le16_to_cpu(id->acoustic); 410 id->msrqs = __le16_to_cpu(id->msrqs); 411 id->sxfert = __le16_to_cpu(id->sxfert); 412 id->sal = __le16_to_cpu(id->sal); 413 id->spg = __le32_to_cpu(id->spg); 414 id->lba_capacity_2 = __le64_to_cpu(id->lba_capacity_2); 415 for (i = 0; i < 22; i++) 416 id->words104_125[i] = __le16_to_cpu(id->words104_125[i]); 417 id->last_lun = __le16_to_cpu(id->last_lun); 418 id->word127 = __le16_to_cpu(id->word127); 419 id->dlf = __le16_to_cpu(id->dlf); 420 id->csfo = __le16_to_cpu(id->csfo); 421 for (i = 0; i < 26; i++) 422 id->words130_155[i] = __le16_to_cpu(id->words130_155[i]); 423 id->word156 = __le16_to_cpu(id->word156); 424 for (i = 0; i < 3; i++) 425 id->words157_159[i] = __le16_to_cpu(id->words157_159[i]); 426 id->cfa_power = __le16_to_cpu(id->cfa_power); 427 for (i = 0; i < 14; i++) 428 id->words161_175[i] = __le16_to_cpu(id->words161_175[i]); 429 for (i = 0; i < 31; i++) 430 id->words176_205[i] = __le16_to_cpu(id->words176_205[i]); 431 for (i = 0; i < 48; i++) 432 id->words206_254[i] = __le16_to_cpu(id->words206_254[i]); 433 id->integrity_word = __le16_to_cpu(id->integrity_word); 434# else 435# error "Please fix <asm/byteorder.h>" 436# endif 437#endif 438} 439 440/* 441 * ide_fixstring() cleans up and (optionally) byte-swaps a text string, 442 * removing leading/trailing blanks and compressing internal blanks. 443 * It is primarily used to tidy up the model name/number fields as 444 * returned by the WIN_[P]IDENTIFY commands. 445 */ 446 447void ide_fixstring (u8 *s, const int bytecount, const int byteswap) 448{ 449 u8 *p = s, *end = &s[bytecount & ~1]; /* bytecount must be even */ 450 451 if (byteswap) { 452 /* convert from big-endian to host byte order */ 453 for (p = end ; p != s;) { 454 unsigned short *pp = (unsigned short *) (p -= 2); 455 *pp = ntohs(*pp); 456 } 457 } 458 /* strip leading blanks */ 459 while (s != end && *s == ' ') 460 ++s; 461 /* compress internal blanks and strip trailing blanks */ 462 while (s != end && *s) { 463 if (*s++ != ' ' || (s != end && *s && *s != ' ')) 464 *p++ = *(s-1); 465 } 466 /* wipe out trailing garbage */ 467 while (p != end) 468 *p++ = '\0'; 469} 470 471EXPORT_SYMBOL(ide_fixstring); 472 473/* 474 * Needed for PCI irq sharing 475 */ 476int drive_is_ready (ide_drive_t *drive) 477{ 478 ide_hwif_t *hwif = HWIF(drive); 479 u8 stat = 0; 480 481 if (drive->waiting_for_dma) 482 return hwif->dma_ops->dma_test_irq(drive); 483 484#if 0 485 /* need to guarantee 400ns since last command was issued */ 486 udelay(1); 487#endif 488 489 /* 490 * We do a passive status test under shared PCI interrupts on 491 * cards that truly share the ATA side interrupt, but may also share 492 * an interrupt with another pci card/device. We make no assumptions 493 * about possible isa-pnp and pci-pnp issues yet. 494 */ 495 if (hwif->io_ports.ctl_addr) 496 stat = ide_read_altstatus(drive); 497 else 498 /* Note: this may clear a pending IRQ!! */ 499 stat = ide_read_status(drive); 500 501 if (stat & BUSY_STAT) 502 /* drive busy: definitely not interrupting */ 503 return 0; 504 505 /* drive ready: *might* be interrupting */ 506 return 1; 507} 508 509EXPORT_SYMBOL(drive_is_ready); 510 511/* 512 * This routine busy-waits for the drive status to be not "busy". 513 * It then checks the status for all of the "good" bits and none 514 * of the "bad" bits, and if all is okay it returns 0. All other 515 * cases return error -- caller may then invoke ide_error(). 516 * 517 * This routine should get fixed to not hog the cpu during extra long waits.. 518 * That could be done by busy-waiting for the first jiffy or two, and then 519 * setting a timer to wake up at half second intervals thereafter, 520 * until timeout is achieved, before timing out. 521 */ 522static int __ide_wait_stat(ide_drive_t *drive, u8 good, u8 bad, unsigned long timeout, u8 *rstat) 523{ 524 unsigned long flags; 525 int i; 526 u8 stat; 527 528 udelay(1); /* spec allows drive 400ns to assert "BUSY" */ 529 stat = ide_read_status(drive); 530 531 if (stat & BUSY_STAT) { 532 local_irq_set(flags); 533 timeout += jiffies; 534 while ((stat = ide_read_status(drive)) & BUSY_STAT) { 535 if (time_after(jiffies, timeout)) { 536 /* 537 * One last read after the timeout in case 538 * heavy interrupt load made us not make any 539 * progress during the timeout.. 540 */ 541 stat = ide_read_status(drive); 542 if (!(stat & BUSY_STAT)) 543 break; 544 545 local_irq_restore(flags); 546 *rstat = stat; 547 return -EBUSY; 548 } 549 } 550 local_irq_restore(flags); 551 } 552 /* 553 * Allow status to settle, then read it again. 554 * A few rare drives vastly violate the 400ns spec here, 555 * so we'll wait up to 10usec for a "good" status 556 * rather than expensively fail things immediately. 557 * This fix courtesy of Matthew Faupel & Niccolo Rigacci. 558 */ 559 for (i = 0; i < 10; i++) { 560 udelay(1); 561 stat = ide_read_status(drive); 562 563 if (OK_STAT(stat, good, bad)) { 564 *rstat = stat; 565 return 0; 566 } 567 } 568 *rstat = stat; 569 return -EFAULT; 570} 571 572/* 573 * In case of error returns error value after doing "*startstop = ide_error()". 574 * The caller should return the updated value of "startstop" in this case, 575 * "startstop" is unchanged when the function returns 0. 576 */ 577int ide_wait_stat(ide_startstop_t *startstop, ide_drive_t *drive, u8 good, u8 bad, unsigned long timeout) 578{ 579 int err; 580 u8 stat; 581 582 /* bail early if we've exceeded max_failures */ 583 if (drive->max_failures && (drive->failures > drive->max_failures)) { 584 *startstop = ide_stopped; 585 return 1; 586 } 587 588 err = __ide_wait_stat(drive, good, bad, timeout, &stat); 589 590 if (err) { 591 char *s = (err == -EBUSY) ? "status timeout" : "status error"; 592 *startstop = ide_error(drive, s, stat); 593 } 594 595 return err; 596} 597 598EXPORT_SYMBOL(ide_wait_stat); 599 600/** 601 * ide_in_drive_list - look for drive in black/white list 602 * @id: drive identifier 603 * @drive_table: list to inspect 604 * 605 * Look for a drive in the blacklist and the whitelist tables 606 * Returns 1 if the drive is found in the table. 607 */ 608 609int ide_in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table) 610{ 611 for ( ; drive_table->id_model; drive_table++) 612 if ((!strcmp(drive_table->id_model, id->model)) && 613 (!drive_table->id_firmware || 614 strstr(id->fw_rev, drive_table->id_firmware))) 615 return 1; 616 return 0; 617} 618 619EXPORT_SYMBOL_GPL(ide_in_drive_list); 620 621/* 622 * Early UDMA66 devices don't set bit14 to 1, only bit13 is valid. 623 * We list them here and depend on the device side cable detection for them. 624 * 625 * Some optical devices with the buggy firmwares have the same problem. 626 */ 627static const struct drive_list_entry ivb_list[] = { 628 { "QUANTUM FIREBALLlct10 05" , "A03.0900" }, 629 { "TSSTcorp CDDVDW SH-S202J" , "SB00" }, 630 { "TSSTcorp CDDVDW SH-S202J" , "SB01" }, 631 { "TSSTcorp CDDVDW SH-S202N" , "SB00" }, 632 { "TSSTcorp CDDVDW SH-S202N" , "SB01" }, 633 { "TSSTcorp CDDVDW SH-S202H" , "SB00" }, 634 { "TSSTcorp CDDVDW SH-S202H" , "SB01" }, 635 { NULL , NULL } 636}; 637 638/* 639 * All hosts that use the 80c ribbon must use! 640 * The name is derived from upper byte of word 93 and the 80c ribbon. 641 */ 642u8 eighty_ninty_three (ide_drive_t *drive) 643{ 644 ide_hwif_t *hwif = drive->hwif; 645 struct hd_driveid *id = drive->id; 646 int ivb = ide_in_drive_list(id, ivb_list); 647 648 if (hwif->cbl == ATA_CBL_PATA40_SHORT) 649 return 1; 650 651 if (ivb) 652 printk(KERN_DEBUG "%s: skipping word 93 validity check\n", 653 drive->name); 654 655 if (ide_dev_is_sata(id) && !ivb) 656 return 1; 657 658 if (hwif->cbl != ATA_CBL_PATA80 && !ivb) 659 goto no_80w; 660 661 /* 662 * FIXME: 663 * - change master/slave IDENTIFY order 664 * - force bit13 (80c cable present) check also for !ivb devices 665 * (unless the slave device is pre-ATA3) 666 */ 667 if ((id->hw_config & 0x4000) || (ivb && (id->hw_config & 0x2000))) 668 return 1; 669 670no_80w: 671 if (drive->udma33_warned == 1) 672 return 0; 673 674 printk(KERN_WARNING "%s: %s side 80-wire cable detection failed, " 675 "limiting max speed to UDMA33\n", 676 drive->name, 677 hwif->cbl == ATA_CBL_PATA80 ? "drive" : "host"); 678 679 drive->udma33_warned = 1; 680 681 return 0; 682} 683 684int ide_driveid_update(ide_drive_t *drive) 685{ 686 ide_hwif_t *hwif = drive->hwif; 687 struct hd_driveid *id; 688 unsigned long timeout, flags; 689 u8 stat; 690 691 /* 692 * Re-read drive->id for possible DMA mode 693 * change (copied from ide-probe.c) 694 */ 695 696 SELECT_MASK(drive, 1); 697 ide_set_irq(drive, 0); 698 msleep(50); 699 hwif->OUTBSYNC(hwif, WIN_IDENTIFY, hwif->io_ports.command_addr); 700 timeout = jiffies + WAIT_WORSTCASE; 701 do { 702 if (time_after(jiffies, timeout)) { 703 SELECT_MASK(drive, 0); 704 return 0; /* drive timed-out */ 705 } 706 707 msleep(50); /* give drive a breather */ 708 stat = ide_read_altstatus(drive); 709 } while (stat & BUSY_STAT); 710 711 msleep(50); /* wait for IRQ and DRQ_STAT */ 712 stat = ide_read_status(drive); 713 714 if (!OK_STAT(stat, DRQ_STAT, BAD_R_STAT)) { 715 SELECT_MASK(drive, 0); 716 printk("%s: CHECK for good STATUS\n", drive->name); 717 return 0; 718 } 719 local_irq_save(flags); 720 SELECT_MASK(drive, 0); 721 id = kmalloc(SECTOR_WORDS*4, GFP_ATOMIC); 722 if (!id) { 723 local_irq_restore(flags); 724 return 0; 725 } 726 hwif->input_data(drive, NULL, id, SECTOR_SIZE); 727 (void)ide_read_status(drive); /* clear drive IRQ */ 728 local_irq_enable(); 729 local_irq_restore(flags); 730 ide_fix_driveid(id); 731 if (id) { 732 drive->id->dma_ultra = id->dma_ultra; 733 drive->id->dma_mword = id->dma_mword; 734 drive->id->dma_1word = id->dma_1word; 735 /* anything more ? */ 736 kfree(id); 737 738 if (drive->using_dma && ide_id_dma_bug(drive)) 739 ide_dma_off(drive); 740 } 741 742 return 1; 743} 744 745int ide_config_drive_speed(ide_drive_t *drive, u8 speed) 746{ 747 ide_hwif_t *hwif = drive->hwif; 748 struct ide_io_ports *io_ports = &hwif->io_ports; 749 int error = 0; 750 u8 stat; 751 752#ifdef CONFIG_BLK_DEV_IDEDMA 753 if (hwif->dma_ops) /* check if host supports DMA */ 754 hwif->dma_ops->dma_host_set(drive, 0); 755#endif 756 757 /* Skip setting PIO flow-control modes on pre-EIDE drives */ 758 if ((speed & 0xf8) == XFER_PIO_0 && !(drive->id->capability & 0x08)) 759 goto skip; 760 761 /* 762 * Don't use ide_wait_cmd here - it will 763 * attempt to set_geometry and recalibrate, 764 * but for some reason these don't work at 765 * this point (lost interrupt). 766 */ 767 /* 768 * Select the drive, and issue the SETFEATURES command 769 */ 770 disable_irq_nosync(hwif->irq); 771 772 /* 773 * FIXME: we race against the running IRQ here if 774 * this is called from non IRQ context. If we use 775 * disable_irq() we hang on the error path. Work 776 * is needed. 777 */ 778 779 udelay(1); 780 SELECT_DRIVE(drive); 781 SELECT_MASK(drive, 0); 782 udelay(1); 783 ide_set_irq(drive, 0); 784 hwif->OUTB(speed, io_ports->nsect_addr); 785 hwif->OUTB(SETFEATURES_XFER, io_ports->feature_addr); 786 hwif->OUTBSYNC(hwif, WIN_SETFEATURES, io_ports->command_addr); 787 if (drive->quirk_list == 2) 788 ide_set_irq(drive, 1); 789 790 error = __ide_wait_stat(drive, drive->ready_stat, 791 BUSY_STAT|DRQ_STAT|ERR_STAT, 792 WAIT_CMD, &stat); 793 794 SELECT_MASK(drive, 0); 795 796 enable_irq(hwif->irq); 797 798 if (error) { 799 (void) ide_dump_status(drive, "set_drive_speed_status", stat); 800 return error; 801 } 802 803 drive->id->dma_ultra &= ~0xFF00; 804 drive->id->dma_mword &= ~0x0F00; 805 drive->id->dma_1word &= ~0x0F00; 806 807 skip: 808#ifdef CONFIG_BLK_DEV_IDEDMA 809 if ((speed >= XFER_SW_DMA_0 || (hwif->host_flags & IDE_HFLAG_VDMA)) && 810 drive->using_dma) 811 hwif->dma_ops->dma_host_set(drive, 1); 812 else if (hwif->dma_ops) /* check if host supports DMA */ 813 ide_dma_off_quietly(drive); 814#endif 815 816 switch(speed) { 817 case XFER_UDMA_7: drive->id->dma_ultra |= 0x8080; break; 818 case XFER_UDMA_6: drive->id->dma_ultra |= 0x4040; break; 819 case XFER_UDMA_5: drive->id->dma_ultra |= 0x2020; break; 820 case XFER_UDMA_4: drive->id->dma_ultra |= 0x1010; break; 821 case XFER_UDMA_3: drive->id->dma_ultra |= 0x0808; break; 822 case XFER_UDMA_2: drive->id->dma_ultra |= 0x0404; break; 823 case XFER_UDMA_1: drive->id->dma_ultra |= 0x0202; break; 824 case XFER_UDMA_0: drive->id->dma_ultra |= 0x0101; break; 825 case XFER_MW_DMA_2: drive->id->dma_mword |= 0x0404; break; 826 case XFER_MW_DMA_1: drive->id->dma_mword |= 0x0202; break; 827 case XFER_MW_DMA_0: drive->id->dma_mword |= 0x0101; break; 828 case XFER_SW_DMA_2: drive->id->dma_1word |= 0x0404; break; 829 case XFER_SW_DMA_1: drive->id->dma_1word |= 0x0202; break; 830 case XFER_SW_DMA_0: drive->id->dma_1word |= 0x0101; break; 831 default: break; 832 } 833 if (!drive->init_speed) 834 drive->init_speed = speed; 835 drive->current_speed = speed; 836 return error; 837} 838 839/* 840 * This should get invoked any time we exit the driver to 841 * wait for an interrupt response from a drive. handler() points 842 * at the appropriate code to handle the next interrupt, and a 843 * timer is started to prevent us from waiting forever in case 844 * something goes wrong (see the ide_timer_expiry() handler later on). 845 * 846 * See also ide_execute_command 847 */ 848static void __ide_set_handler (ide_drive_t *drive, ide_handler_t *handler, 849 unsigned int timeout, ide_expiry_t *expiry) 850{ 851 ide_hwgroup_t *hwgroup = HWGROUP(drive); 852 853 BUG_ON(hwgroup->handler); 854 hwgroup->handler = handler; 855 hwgroup->expiry = expiry; 856 hwgroup->timer.expires = jiffies + timeout; 857 hwgroup->req_gen_timer = hwgroup->req_gen; 858 add_timer(&hwgroup->timer); 859} 860 861void ide_set_handler (ide_drive_t *drive, ide_handler_t *handler, 862 unsigned int timeout, ide_expiry_t *expiry) 863{ 864 unsigned long flags; 865 spin_lock_irqsave(&ide_lock, flags); 866 __ide_set_handler(drive, handler, timeout, expiry); 867 spin_unlock_irqrestore(&ide_lock, flags); 868} 869 870EXPORT_SYMBOL(ide_set_handler); 871 872/** 873 * ide_execute_command - execute an IDE command 874 * @drive: IDE drive to issue the command against 875 * @command: command byte to write 876 * @handler: handler for next phase 877 * @timeout: timeout for command 878 * @expiry: handler to run on timeout 879 * 880 * Helper function to issue an IDE command. This handles the 881 * atomicity requirements, command timing and ensures that the 882 * handler and IRQ setup do not race. All IDE command kick off 883 * should go via this function or do equivalent locking. 884 */ 885 886void ide_execute_command(ide_drive_t *drive, u8 cmd, ide_handler_t *handler, 887 unsigned timeout, ide_expiry_t *expiry) 888{ 889 unsigned long flags; 890 ide_hwif_t *hwif = HWIF(drive); 891 892 spin_lock_irqsave(&ide_lock, flags); 893 __ide_set_handler(drive, handler, timeout, expiry); 894 hwif->OUTBSYNC(hwif, cmd, hwif->io_ports.command_addr); 895 /* 896 * Drive takes 400nS to respond, we must avoid the IRQ being 897 * serviced before that. 898 * 899 * FIXME: we could skip this delay with care on non shared devices 900 */ 901 ndelay(400); 902 spin_unlock_irqrestore(&ide_lock, flags); 903} 904EXPORT_SYMBOL(ide_execute_command); 905 906void ide_execute_pkt_cmd(ide_drive_t *drive) 907{ 908 ide_hwif_t *hwif = drive->hwif; 909 unsigned long flags; 910 911 spin_lock_irqsave(&ide_lock, flags); 912 hwif->OUTBSYNC(hwif, WIN_PACKETCMD, hwif->io_ports.command_addr); 913 ndelay(400); 914 spin_unlock_irqrestore(&ide_lock, flags); 915} 916EXPORT_SYMBOL_GPL(ide_execute_pkt_cmd); 917 918static inline void ide_complete_drive_reset(ide_drive_t *drive, int err) 919{ 920 struct request *rq = drive->hwif->hwgroup->rq; 921 922 if (rq && blk_special_request(rq) && rq->cmd[0] == REQ_DRIVE_RESET) 923 ide_end_request(drive, err ? err : 1, 0); 924} 925 926/* needed below */ 927static ide_startstop_t do_reset1 (ide_drive_t *, int); 928 929/* 930 * atapi_reset_pollfunc() gets invoked to poll the interface for completion every 50ms 931 * during an atapi drive reset operation. If the drive has not yet responded, 932 * and we have not yet hit our maximum waiting time, then the timer is restarted 933 * for another 50ms. 934 */ 935static ide_startstop_t atapi_reset_pollfunc (ide_drive_t *drive) 936{ 937 ide_hwgroup_t *hwgroup = HWGROUP(drive); 938 u8 stat; 939 940 SELECT_DRIVE(drive); 941 udelay (10); 942 stat = ide_read_status(drive); 943 944 if (OK_STAT(stat, 0, BUSY_STAT)) 945 printk("%s: ATAPI reset complete\n", drive->name); 946 else { 947 if (time_before(jiffies, hwgroup->poll_timeout)) { 948 ide_set_handler(drive, &atapi_reset_pollfunc, HZ/20, NULL); 949 /* continue polling */ 950 return ide_started; 951 } 952 /* end of polling */ 953 hwgroup->polling = 0; 954 printk("%s: ATAPI reset timed-out, status=0x%02x\n", 955 drive->name, stat); 956 /* do it the old fashioned way */ 957 return do_reset1(drive, 1); 958 } 959 /* done polling */ 960 hwgroup->polling = 0; 961 ide_complete_drive_reset(drive, 0); 962 return ide_stopped; 963} 964 965/* 966 * reset_pollfunc() gets invoked to poll the interface for completion every 50ms 967 * during an ide reset operation. If the drives have not yet responded, 968 * and we have not yet hit our maximum waiting time, then the timer is restarted 969 * for another 50ms. 970 */ 971static ide_startstop_t reset_pollfunc (ide_drive_t *drive) 972{ 973 ide_hwgroup_t *hwgroup = HWGROUP(drive); 974 ide_hwif_t *hwif = HWIF(drive); 975 const struct ide_port_ops *port_ops = hwif->port_ops; 976 u8 tmp; 977 int err = 0; 978 979 if (port_ops && port_ops->reset_poll) { 980 err = port_ops->reset_poll(drive); 981 if (err) { 982 printk(KERN_ERR "%s: host reset_poll failure for %s.\n", 983 hwif->name, drive->name); 984 goto out; 985 } 986 } 987 988 tmp = ide_read_status(drive); 989 990 if (!OK_STAT(tmp, 0, BUSY_STAT)) { 991 if (time_before(jiffies, hwgroup->poll_timeout)) { 992 ide_set_handler(drive, &reset_pollfunc, HZ/20, NULL); 993 /* continue polling */ 994 return ide_started; 995 } 996 printk("%s: reset timed-out, status=0x%02x\n", hwif->name, tmp); 997 drive->failures++; 998 err = -EIO; 999 } else { 1000 printk("%s: reset: ", hwif->name); 1001 tmp = ide_read_error(drive); 1002 1003 if (tmp == 1) { 1004 printk("success\n"); 1005 drive->failures = 0; 1006 } else { 1007 drive->failures++; 1008 printk("master: "); 1009 switch (tmp & 0x7f) { 1010 case 1: printk("passed"); 1011 break; 1012 case 2: printk("formatter device error"); 1013 break; 1014 case 3: printk("sector buffer error"); 1015 break; 1016 case 4: printk("ECC circuitry error"); 1017 break; 1018 case 5: printk("controlling MPU error"); 1019 break; 1020 default:printk("error (0x%02x?)", tmp); 1021 } 1022 if (tmp & 0x80) 1023 printk("; slave: failed"); 1024 printk("\n"); 1025 err = -EIO; 1026 } 1027 } 1028out: 1029 hwgroup->polling = 0; /* done polling */ 1030 ide_complete_drive_reset(drive, err); 1031 return ide_stopped; 1032} 1033 1034static void ide_disk_pre_reset(ide_drive_t *drive) 1035{ 1036 int legacy = (drive->id->cfs_enable_2 & 0x0400) ? 0 : 1; 1037 1038 drive->special.all = 0; 1039 drive->special.b.set_geometry = legacy; 1040 drive->special.b.recalibrate = legacy; 1041 drive->mult_count = 0; 1042 if (!drive->keep_settings && !drive->using_dma) 1043 drive->mult_req = 0; 1044 if (drive->mult_req != drive->mult_count) 1045 drive->special.b.set_multmode = 1; 1046} 1047 1048static void pre_reset(ide_drive_t *drive) 1049{ 1050 const struct ide_port_ops *port_ops = drive->hwif->port_ops; 1051 1052 if (drive->media == ide_disk) 1053 ide_disk_pre_reset(drive); 1054 else 1055 drive->post_reset = 1; 1056 1057 if (drive->using_dma) { 1058 if (drive->crc_count) 1059 ide_check_dma_crc(drive); 1060 else 1061 ide_dma_off(drive); 1062 } 1063 1064 if (!drive->keep_settings) { 1065 if (!drive->using_dma) { 1066 drive->unmask = 0; 1067 drive->io_32bit = 0; 1068 } 1069 return; 1070 } 1071 1072 if (port_ops && port_ops->pre_reset) 1073 port_ops->pre_reset(drive); 1074 1075 if (drive->current_speed != 0xff) 1076 drive->desired_speed = drive->current_speed; 1077 drive->current_speed = 0xff; 1078} 1079 1080/* 1081 * do_reset1() attempts to recover a confused drive by resetting it. 1082 * Unfortunately, resetting a disk drive actually resets all devices on 1083 * the same interface, so it can really be thought of as resetting the 1084 * interface rather than resetting the drive. 1085 * 1086 * ATAPI devices have their own reset mechanism which allows them to be 1087 * individually reset without clobbering other devices on the same interface. 1088 * 1089 * Unfortunately, the IDE interface does not generate an interrupt to let 1090 * us know when the reset operation has finished, so we must poll for this. 1091 * Equally poor, though, is the fact that this may a very long time to complete, 1092 * (up to 30 seconds worstcase). So, instead of busy-waiting here for it, 1093 * we set a timer to poll at 50ms intervals. 1094 */ 1095static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi) 1096{ 1097 unsigned int unit; 1098 unsigned long flags; 1099 ide_hwif_t *hwif; 1100 ide_hwgroup_t *hwgroup; 1101 struct ide_io_ports *io_ports; 1102 const struct ide_port_ops *port_ops; 1103 u8 ctl; 1104 1105 spin_lock_irqsave(&ide_lock, flags); 1106 hwif = HWIF(drive); 1107 hwgroup = HWGROUP(drive); 1108 1109 io_ports = &hwif->io_ports; 1110 1111 /* We must not reset with running handlers */ 1112 BUG_ON(hwgroup->handler != NULL); 1113 1114 /* For an ATAPI device, first try an ATAPI SRST. */ 1115 if (drive->media != ide_disk && !do_not_try_atapi) { 1116 pre_reset(drive); 1117 SELECT_DRIVE(drive); 1118 udelay (20); 1119 hwif->OUTBSYNC(hwif, WIN_SRST, io_ports->command_addr); 1120 ndelay(400); 1121 hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE; 1122 hwgroup->polling = 1; 1123 __ide_set_handler(drive, &atapi_reset_pollfunc, HZ/20, NULL); 1124 spin_unlock_irqrestore(&ide_lock, flags); 1125 return ide_started; 1126 } 1127 1128 /* 1129 * First, reset any device state data we were maintaining 1130 * for any of the drives on this interface. 1131 */ 1132 for (unit = 0; unit < MAX_DRIVES; ++unit) 1133 pre_reset(&hwif->drives[unit]); 1134 1135 if (io_ports->ctl_addr == 0) { 1136 spin_unlock_irqrestore(&ide_lock, flags); 1137 ide_complete_drive_reset(drive, -ENXIO); 1138 return ide_stopped; 1139 } 1140 1141 /* 1142 * Note that we also set nIEN while resetting the device, 1143 * to mask unwanted interrupts from the interface during the reset. 1144 * However, due to the design of PC hardware, this will cause an 1145 * immediate interrupt due to the edge transition it produces. 1146 * This single interrupt gives us a "fast poll" for drives that 1147 * recover from reset very quickly, saving us the first 50ms wait time. 1148 */ 1149 /* set SRST and nIEN */ 1150 hwif->OUTBSYNC(hwif, ATA_DEVCTL_OBS | 6, io_ports->ctl_addr); 1151 /* more than enough time */ 1152 udelay(10); 1153 if (drive->quirk_list == 2) 1154 ctl = ATA_DEVCTL_OBS; /* clear SRST and nIEN */ 1155 else 1156 ctl = ATA_DEVCTL_OBS | 2; /* clear SRST, leave nIEN */ 1157 hwif->OUTBSYNC(hwif, ctl, io_ports->ctl_addr); 1158 /* more than enough time */ 1159 udelay(10); 1160 hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE; 1161 hwgroup->polling = 1; 1162 __ide_set_handler(drive, &reset_pollfunc, HZ/20, NULL); 1163 1164 /* 1165 * Some weird controller like resetting themselves to a strange 1166 * state when the disks are reset this way. At least, the Winbond 1167 * 553 documentation says that 1168 */ 1169 port_ops = hwif->port_ops; 1170 if (port_ops && port_ops->resetproc) 1171 port_ops->resetproc(drive); 1172 1173 spin_unlock_irqrestore(&ide_lock, flags); 1174 return ide_started; 1175} 1176 1177/* 1178 * ide_do_reset() is the entry point to the drive/interface reset code. 1179 */ 1180 1181ide_startstop_t ide_do_reset (ide_drive_t *drive) 1182{ 1183 return do_reset1(drive, 0); 1184} 1185 1186EXPORT_SYMBOL(ide_do_reset); 1187 1188/* 1189 * ide_wait_not_busy() waits for the currently selected device on the hwif 1190 * to report a non-busy status, see comments in ide_probe_port(). 1191 */ 1192int ide_wait_not_busy(ide_hwif_t *hwif, unsigned long timeout) 1193{ 1194 u8 stat = 0; 1195 1196 while(timeout--) { 1197 /* 1198 * Turn this into a schedule() sleep once I'm sure 1199 * about locking issues (2.5 work ?). 1200 */ 1201 mdelay(1); 1202 stat = hwif->INB(hwif->io_ports.status_addr); 1203 if ((stat & BUSY_STAT) == 0) 1204 return 0; 1205 /* 1206 * Assume a value of 0xff means nothing is connected to 1207 * the interface and it doesn't implement the pull-down 1208 * resistor on D7. 1209 */ 1210 if (stat == 0xff) 1211 return -ENODEV; 1212 touch_softlockup_watchdog(); 1213 touch_nmi_watchdog(); 1214 } 1215 return -EBUSY; 1216} 1217 1218EXPORT_SYMBOL_GPL(ide_wait_not_busy); 1219 1220