ns87415.c revision 35c9b4daf4c94b30e5cede597d98016ebf31b5ad
1/* 2 * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com> 3 * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be> 4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 5 * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org> 6 * 7 * Inspired by an earlier effort from David S. Miller <davem@redhat.com> 8 */ 9 10#include <linux/module.h> 11#include <linux/types.h> 12#include <linux/kernel.h> 13#include <linux/interrupt.h> 14#include <linux/pci.h> 15#include <linux/delay.h> 16#include <linux/ide.h> 17#include <linux/init.h> 18 19#include <asm/io.h> 20 21#define DRV_NAME "ns87415" 22 23#ifdef CONFIG_SUPERIO 24/* SUPERIO 87560 is a PoS chip that NatSem denies exists. 25 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations 26 * which use the integrated NS87514 cell for CD-ROM support. 27 * i.e we have to support for CD-ROM installs. 28 * See drivers/parisc/superio.c for more gory details. 29 */ 30#include <asm/superio.h> 31 32#define SUPERIO_IDE_MAX_RETRIES 25 33 34/* Because of a defect in Super I/O, all reads of the PCI DMA status 35 * registers, IDE status register and the IDE select register need to be 36 * retried 37 */ 38static u8 superio_ide_inb (unsigned long port) 39{ 40 u8 tmp; 41 int retries = SUPERIO_IDE_MAX_RETRIES; 42 43 /* printk(" [ reading port 0x%x with retry ] ", port); */ 44 45 do { 46 tmp = inb(port); 47 if (tmp == 0) 48 udelay(50); 49 } while (tmp == 0 && retries-- > 0); 50 51 return tmp; 52} 53 54static u8 superio_read_status(ide_hwif_t *hwif) 55{ 56 return superio_ide_inb(hwif->io_ports.status_addr); 57} 58 59static u8 superio_dma_sff_read_status(ide_hwif_t *hwif) 60{ 61 return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS); 62} 63 64static void superio_tf_read(ide_drive_t *drive, struct ide_cmd *cmd) 65{ 66 struct ide_io_ports *io_ports = &drive->hwif->io_ports; 67 struct ide_taskfile *tf = &cmd->tf; 68 69 if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) { 70 u16 data = inw(io_ports->data_addr); 71 72 tf->data = data & 0xff; 73 tf->hob_data = (data >> 8) & 0xff; 74 } 75 76 /* be sure we're looking at the low order bits */ 77 outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); 78 79 if (cmd->tf_flags & IDE_TFLAG_IN_FEATURE) 80 tf->feature = inb(io_ports->feature_addr); 81 if (cmd->tf_flags & IDE_TFLAG_IN_NSECT) 82 tf->nsect = inb(io_ports->nsect_addr); 83 if (cmd->tf_flags & IDE_TFLAG_IN_LBAL) 84 tf->lbal = inb(io_ports->lbal_addr); 85 if (cmd->tf_flags & IDE_TFLAG_IN_LBAM) 86 tf->lbam = inb(io_ports->lbam_addr); 87 if (cmd->tf_flags & IDE_TFLAG_IN_LBAH) 88 tf->lbah = inb(io_ports->lbah_addr); 89 if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE) 90 tf->device = superio_ide_inb(io_ports->device_addr); 91 92 if (cmd->tf_flags & IDE_TFLAG_LBA48) { 93 outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr); 94 95 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_FEATURE) 96 tf->hob_feature = inb(io_ports->feature_addr); 97 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT) 98 tf->hob_nsect = inb(io_ports->nsect_addr); 99 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL) 100 tf->hob_lbal = inb(io_ports->lbal_addr); 101 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM) 102 tf->hob_lbam = inb(io_ports->lbam_addr); 103 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH) 104 tf->hob_lbah = inb(io_ports->lbah_addr); 105 } 106} 107 108static const struct ide_tp_ops superio_tp_ops = { 109 .exec_command = ide_exec_command, 110 .read_status = superio_read_status, 111 .read_altstatus = ide_read_altstatus, 112 113 .set_irq = ide_set_irq, 114 115 .tf_load = ide_tf_load, 116 .tf_read = superio_tf_read, 117 118 .input_data = ide_input_data, 119 .output_data = ide_output_data, 120}; 121 122static void __devinit superio_init_iops(struct hwif_s *hwif) 123{ 124 struct pci_dev *pdev = to_pci_dev(hwif->dev); 125 u32 dma_stat; 126 u8 port = hwif->channel, tmp; 127 128 dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa); 129 130 /* Clear error/interrupt, enable dma */ 131 tmp = superio_ide_inb(dma_stat); 132 outb(tmp | 0x66, dma_stat); 133} 134#else 135#define superio_dma_sff_read_status ide_dma_sff_read_status 136#endif 137 138static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 }; 139 140/* 141 * This routine either enables/disables (according to IDE_DFLAG_PRESENT) 142 * the IRQ associated with the port, 143 * and selects either PIO or DMA handshaking for the next I/O operation. 144 */ 145static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma) 146{ 147 ide_hwif_t *hwif = drive->hwif; 148 struct pci_dev *dev = to_pci_dev(hwif->dev); 149 unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data; 150 unsigned long flags; 151 152 local_irq_save(flags); 153 new = *old; 154 155 /* Adjust IRQ enable bit */ 156 bit = 1 << (8 + hwif->channel); 157 158 if (drive->dev_flags & IDE_DFLAG_PRESENT) 159 new &= ~bit; 160 else 161 new |= bit; 162 163 /* Select PIO or DMA, DMA may only be selected for one drive/channel. */ 164 bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1)); 165 other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1)); 166 new = use_dma ? ((new & ~other) | bit) : (new & ~bit); 167 168 if (new != *old) { 169 unsigned char stat; 170 171 /* 172 * Don't change DMA engine settings while Write Buffers 173 * are busy. 174 */ 175 (void) pci_read_config_byte(dev, 0x43, &stat); 176 while (stat & 0x03) { 177 udelay(1); 178 (void) pci_read_config_byte(dev, 0x43, &stat); 179 } 180 181 *old = new; 182 (void) pci_write_config_dword(dev, 0x40, new); 183 184 /* 185 * And let things settle... 186 */ 187 udelay(10); 188 } 189 190 local_irq_restore(flags); 191} 192 193static void ns87415_selectproc (ide_drive_t *drive) 194{ 195 ns87415_prepare_drive(drive, 196 !!(drive->dev_flags & IDE_DFLAG_USING_DMA)); 197} 198 199static int ns87415_dma_end(ide_drive_t *drive) 200{ 201 ide_hwif_t *hwif = drive->hwif; 202 u8 dma_stat = 0, dma_cmd = 0; 203 204 drive->waiting_for_dma = 0; 205 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif); 206 /* get DMA command mode */ 207 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 208 /* stop DMA */ 209 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); 210 /* from ERRATA: clear the INTR & ERROR bits */ 211 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 212 outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD); 213 /* and free any DMA resources */ 214 ide_destroy_dmatable(drive); 215 /* verify good DMA status */ 216 return (dma_stat & 7) != 4; 217} 218 219static int ns87415_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) 220{ 221 /* select DMA xfer */ 222 ns87415_prepare_drive(drive, 1); 223 if (ide_dma_setup(drive, cmd) == 0) 224 return 0; 225 /* DMA failed: select PIO xfer */ 226 ns87415_prepare_drive(drive, 0); 227 return 1; 228} 229 230static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif) 231{ 232 struct pci_dev *dev = to_pci_dev(hwif->dev); 233 unsigned int ctrl, using_inta; 234 u8 progif; 235#ifdef __sparc_v9__ 236 int timeout; 237 u8 stat; 238#endif 239 240 /* 241 * We cannot probe for IRQ: both ports share common IRQ on INTA. 242 * Also, leave IRQ masked during drive probing, to prevent infinite 243 * interrupts from a potentially floating INTA.. 244 * 245 * IRQs get unmasked in selectproc when drive is first used. 246 */ 247 (void) pci_read_config_dword(dev, 0x40, &ctrl); 248 (void) pci_read_config_byte(dev, 0x09, &progif); 249 /* is irq in "native" mode? */ 250 using_inta = progif & (1 << (hwif->channel << 1)); 251 if (!using_inta) 252 using_inta = ctrl & (1 << (4 + hwif->channel)); 253 if (hwif->mate) { 254 hwif->select_data = hwif->mate->select_data; 255 } else { 256 hwif->select_data = (unsigned long) 257 &ns87415_control[ns87415_count++]; 258 ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */ 259 if (using_inta) 260 ctrl &= ~(1 << 6); /* unmask INTA */ 261 *((unsigned int *)hwif->select_data) = ctrl; 262 (void) pci_write_config_dword(dev, 0x40, ctrl); 263 264 /* 265 * Set prefetch size to 512 bytes for both ports, 266 * but don't turn on/off prefetching here. 267 */ 268 pci_write_config_byte(dev, 0x55, 0xee); 269 270#ifdef __sparc_v9__ 271 /* 272 * XXX: Reset the device, if we don't it will not respond to 273 * SELECT_DRIVE() properly during first ide_probe_port(). 274 */ 275 timeout = 10000; 276 outb(12, hwif->io_ports.ctl_addr); 277 udelay(10); 278 outb(8, hwif->io_ports.ctl_addr); 279 do { 280 udelay(50); 281 stat = hwif->tp_ops->read_status(hwif); 282 if (stat == 0xff) 283 break; 284 } while ((stat & ATA_BUSY) && --timeout); 285#endif 286 } 287 288 if (!using_inta) 289 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel); 290 291 if (!hwif->dma_base) 292 return; 293 294 outb(0x60, hwif->dma_base + ATA_DMA_STATUS); 295} 296 297static const struct ide_port_ops ns87415_port_ops = { 298 .selectproc = ns87415_selectproc, 299}; 300 301static const struct ide_dma_ops ns87415_dma_ops = { 302 .dma_host_set = ide_dma_host_set, 303 .dma_setup = ns87415_dma_setup, 304 .dma_start = ide_dma_start, 305 .dma_end = ns87415_dma_end, 306 .dma_test_irq = ide_dma_test_irq, 307 .dma_lost_irq = ide_dma_lost_irq, 308 .dma_timer_expiry = ide_dma_sff_timer_expiry, 309 .dma_sff_read_status = superio_dma_sff_read_status, 310}; 311 312static const struct ide_port_info ns87415_chipset __devinitdata = { 313 .name = DRV_NAME, 314 .init_hwif = init_hwif_ns87415, 315 .port_ops = &ns87415_port_ops, 316 .dma_ops = &ns87415_dma_ops, 317 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | 318 IDE_HFLAG_NO_ATAPI_DMA, 319}; 320 321static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id) 322{ 323 struct ide_port_info d = ns87415_chipset; 324 325#ifdef CONFIG_SUPERIO 326 if (PCI_SLOT(dev->devfn) == 0xE) { 327 /* Built-in - assume it's under superio. */ 328 d.init_iops = superio_init_iops; 329 d.tp_ops = &superio_tp_ops; 330 } 331#endif 332 return ide_pci_init_one(dev, &d, NULL); 333} 334 335static const struct pci_device_id ns87415_pci_tbl[] = { 336 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 }, 337 { 0, }, 338}; 339MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); 340 341static struct pci_driver ns87415_pci_driver = { 342 .name = "NS87415_IDE", 343 .id_table = ns87415_pci_tbl, 344 .probe = ns87415_init_one, 345 .remove = ide_pci_remove, 346 .suspend = ide_pci_suspend, 347 .resume = ide_pci_resume, 348}; 349 350static int __init ns87415_ide_init(void) 351{ 352 return ide_pci_register_driver(&ns87415_pci_driver); 353} 354 355static void __exit ns87415_ide_exit(void) 356{ 357 pci_unregister_driver(&ns87415_pci_driver); 358} 359 360module_init(ns87415_ide_init); 361module_exit(ns87415_ide_exit); 362 363MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick"); 364MODULE_DESCRIPTION("PCI driver module for NS87415 IDE"); 365MODULE_LICENSE("GPL"); 366