ns87415.c revision 6762511934e6e7287ce3c8baac0d52ef64e3787b
1/* 2 * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com> 3 * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be> 4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 5 * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org> 6 * 7 * Inspired by an earlier effort from David S. Miller <davem@redhat.com> 8 */ 9 10#include <linux/module.h> 11#include <linux/types.h> 12#include <linux/kernel.h> 13#include <linux/interrupt.h> 14#include <linux/pci.h> 15#include <linux/delay.h> 16#include <linux/ide.h> 17#include <linux/init.h> 18 19#include <asm/io.h> 20 21#define DRV_NAME "ns87415" 22 23#ifdef CONFIG_SUPERIO 24/* SUPERIO 87560 is a PoS chip that NatSem denies exists. 25 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations 26 * which use the integrated NS87514 cell for CD-ROM support. 27 * i.e we have to support for CD-ROM installs. 28 * See drivers/parisc/superio.c for more gory details. 29 */ 30#include <asm/superio.h> 31 32#define SUPERIO_IDE_MAX_RETRIES 25 33 34/* Because of a defect in Super I/O, all reads of the PCI DMA status 35 * registers, IDE status register and the IDE select register need to be 36 * retried 37 */ 38static u8 superio_ide_inb (unsigned long port) 39{ 40 u8 tmp; 41 int retries = SUPERIO_IDE_MAX_RETRIES; 42 43 /* printk(" [ reading port 0x%x with retry ] ", port); */ 44 45 do { 46 tmp = inb(port); 47 if (tmp == 0) 48 udelay(50); 49 } while (tmp == 0 && retries-- > 0); 50 51 return tmp; 52} 53 54static u8 superio_read_status(ide_hwif_t *hwif) 55{ 56 return superio_ide_inb(hwif->io_ports.status_addr); 57} 58 59static u8 superio_dma_sff_read_status(ide_hwif_t *hwif) 60{ 61 return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS); 62} 63 64static void superio_tf_read(ide_drive_t *drive, struct ide_cmd *cmd) 65{ 66 struct ide_io_ports *io_ports = &drive->hwif->io_ports; 67 struct ide_taskfile *tf = &cmd->tf; 68 69 if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) { 70 u16 data = inw(io_ports->data_addr); 71 72 tf->data = data & 0xff; 73 tf->hob_data = (data >> 8) & 0xff; 74 } 75 76 /* be sure we're looking at the low order bits */ 77 outb(ATA_DEVCTL_OBS, io_ports->ctl_addr); 78 79 if (cmd->tf_flags & IDE_TFLAG_IN_ERROR) 80 tf->error = inb(io_ports->feature_addr); 81 if (cmd->tf_flags & IDE_TFLAG_IN_NSECT) 82 tf->nsect = inb(io_ports->nsect_addr); 83 if (cmd->tf_flags & IDE_TFLAG_IN_LBAL) 84 tf->lbal = inb(io_ports->lbal_addr); 85 if (cmd->tf_flags & IDE_TFLAG_IN_LBAM) 86 tf->lbam = inb(io_ports->lbam_addr); 87 if (cmd->tf_flags & IDE_TFLAG_IN_LBAH) 88 tf->lbah = inb(io_ports->lbah_addr); 89 if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE) 90 tf->device = superio_ide_inb(io_ports->device_addr); 91 92 if (cmd->tf_flags & IDE_TFLAG_LBA48) { 93 outb(ATA_HOB | ATA_DEVCTL_OBS, io_ports->ctl_addr); 94 95 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_ERROR) 96 tf->hob_error = inb(io_ports->feature_addr); 97 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT) 98 tf->hob_nsect = inb(io_ports->nsect_addr); 99 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL) 100 tf->hob_lbal = inb(io_ports->lbal_addr); 101 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM) 102 tf->hob_lbam = inb(io_ports->lbam_addr); 103 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH) 104 tf->hob_lbah = inb(io_ports->lbah_addr); 105 } 106} 107 108static const struct ide_tp_ops superio_tp_ops = { 109 .exec_command = ide_exec_command, 110 .read_status = superio_read_status, 111 .read_altstatus = ide_read_altstatus, 112 .write_devctl = ide_write_devctl, 113 114 .tf_load = ide_tf_load, 115 .tf_read = superio_tf_read, 116 117 .input_data = ide_input_data, 118 .output_data = ide_output_data, 119}; 120 121static void __devinit superio_init_iops(struct hwif_s *hwif) 122{ 123 struct pci_dev *pdev = to_pci_dev(hwif->dev); 124 u32 dma_stat; 125 u8 port = hwif->channel, tmp; 126 127 dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa); 128 129 /* Clear error/interrupt, enable dma */ 130 tmp = superio_ide_inb(dma_stat); 131 outb(tmp | 0x66, dma_stat); 132} 133#else 134#define superio_dma_sff_read_status ide_dma_sff_read_status 135#endif 136 137static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 }; 138 139/* 140 * This routine either enables/disables (according to IDE_DFLAG_PRESENT) 141 * the IRQ associated with the port, 142 * and selects either PIO or DMA handshaking for the next I/O operation. 143 */ 144static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma) 145{ 146 ide_hwif_t *hwif = drive->hwif; 147 struct pci_dev *dev = to_pci_dev(hwif->dev); 148 unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data; 149 unsigned long flags; 150 151 local_irq_save(flags); 152 new = *old; 153 154 /* Adjust IRQ enable bit */ 155 bit = 1 << (8 + hwif->channel); 156 157 if (drive->dev_flags & IDE_DFLAG_PRESENT) 158 new &= ~bit; 159 else 160 new |= bit; 161 162 /* Select PIO or DMA, DMA may only be selected for one drive/channel. */ 163 bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1)); 164 other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1)); 165 new = use_dma ? ((new & ~other) | bit) : (new & ~bit); 166 167 if (new != *old) { 168 unsigned char stat; 169 170 /* 171 * Don't change DMA engine settings while Write Buffers 172 * are busy. 173 */ 174 (void) pci_read_config_byte(dev, 0x43, &stat); 175 while (stat & 0x03) { 176 udelay(1); 177 (void) pci_read_config_byte(dev, 0x43, &stat); 178 } 179 180 *old = new; 181 (void) pci_write_config_dword(dev, 0x40, new); 182 183 /* 184 * And let things settle... 185 */ 186 udelay(10); 187 } 188 189 local_irq_restore(flags); 190} 191 192static void ns87415_selectproc (ide_drive_t *drive) 193{ 194 ns87415_prepare_drive(drive, 195 !!(drive->dev_flags & IDE_DFLAG_USING_DMA)); 196} 197 198static void ns87415_dma_start(ide_drive_t *drive) 199{ 200 ns87415_prepare_drive(drive, 1); 201 ide_dma_start(drive); 202} 203 204static int ns87415_dma_end(ide_drive_t *drive) 205{ 206 ide_hwif_t *hwif = drive->hwif; 207 u8 dma_stat = 0, dma_cmd = 0; 208 209 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif); 210 /* get DMA command mode */ 211 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 212 /* stop DMA */ 213 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); 214 /* from ERRATA: clear the INTR & ERROR bits */ 215 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 216 outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD); 217 218 ns87415_prepare_drive(drive, 0); 219 220 /* verify good DMA status */ 221 return (dma_stat & 7) != 4; 222} 223 224static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif) 225{ 226 struct pci_dev *dev = to_pci_dev(hwif->dev); 227 unsigned int ctrl, using_inta; 228 u8 progif; 229#ifdef __sparc_v9__ 230 int timeout; 231 u8 stat; 232#endif 233 234 /* 235 * We cannot probe for IRQ: both ports share common IRQ on INTA. 236 * Also, leave IRQ masked during drive probing, to prevent infinite 237 * interrupts from a potentially floating INTA.. 238 * 239 * IRQs get unmasked in selectproc when drive is first used. 240 */ 241 (void) pci_read_config_dword(dev, 0x40, &ctrl); 242 (void) pci_read_config_byte(dev, 0x09, &progif); 243 /* is irq in "native" mode? */ 244 using_inta = progif & (1 << (hwif->channel << 1)); 245 if (!using_inta) 246 using_inta = ctrl & (1 << (4 + hwif->channel)); 247 if (hwif->mate) { 248 hwif->select_data = hwif->mate->select_data; 249 } else { 250 hwif->select_data = (unsigned long) 251 &ns87415_control[ns87415_count++]; 252 ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */ 253 if (using_inta) 254 ctrl &= ~(1 << 6); /* unmask INTA */ 255 *((unsigned int *)hwif->select_data) = ctrl; 256 (void) pci_write_config_dword(dev, 0x40, ctrl); 257 258 /* 259 * Set prefetch size to 512 bytes for both ports, 260 * but don't turn on/off prefetching here. 261 */ 262 pci_write_config_byte(dev, 0x55, 0xee); 263 264#ifdef __sparc_v9__ 265 /* 266 * XXX: Reset the device, if we don't it will not respond to 267 * SELECT_DRIVE() properly during first ide_probe_port(). 268 */ 269 timeout = 10000; 270 outb(12, hwif->io_ports.ctl_addr); 271 udelay(10); 272 outb(8, hwif->io_ports.ctl_addr); 273 do { 274 udelay(50); 275 stat = hwif->tp_ops->read_status(hwif); 276 if (stat == 0xff) 277 break; 278 } while ((stat & ATA_BUSY) && --timeout); 279#endif 280 } 281 282 if (!using_inta) 283 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel); 284 285 if (!hwif->dma_base) 286 return; 287 288 outb(0x60, hwif->dma_base + ATA_DMA_STATUS); 289} 290 291static const struct ide_port_ops ns87415_port_ops = { 292 .selectproc = ns87415_selectproc, 293}; 294 295static const struct ide_dma_ops ns87415_dma_ops = { 296 .dma_host_set = ide_dma_host_set, 297 .dma_setup = ide_dma_setup, 298 .dma_start = ns87415_dma_start, 299 .dma_end = ns87415_dma_end, 300 .dma_test_irq = ide_dma_test_irq, 301 .dma_lost_irq = ide_dma_lost_irq, 302 .dma_timer_expiry = ide_dma_sff_timer_expiry, 303 .dma_sff_read_status = superio_dma_sff_read_status, 304}; 305 306static const struct ide_port_info ns87415_chipset __devinitdata = { 307 .name = DRV_NAME, 308 .init_hwif = init_hwif_ns87415, 309 .port_ops = &ns87415_port_ops, 310 .dma_ops = &ns87415_dma_ops, 311 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | 312 IDE_HFLAG_NO_ATAPI_DMA, 313}; 314 315static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id) 316{ 317 struct ide_port_info d = ns87415_chipset; 318 319#ifdef CONFIG_SUPERIO 320 if (PCI_SLOT(dev->devfn) == 0xE) { 321 /* Built-in - assume it's under superio. */ 322 d.init_iops = superio_init_iops; 323 d.tp_ops = &superio_tp_ops; 324 } 325#endif 326 return ide_pci_init_one(dev, &d, NULL); 327} 328 329static const struct pci_device_id ns87415_pci_tbl[] = { 330 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 }, 331 { 0, }, 332}; 333MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); 334 335static struct pci_driver ns87415_pci_driver = { 336 .name = "NS87415_IDE", 337 .id_table = ns87415_pci_tbl, 338 .probe = ns87415_init_one, 339 .remove = ide_pci_remove, 340 .suspend = ide_pci_suspend, 341 .resume = ide_pci_resume, 342}; 343 344static int __init ns87415_ide_init(void) 345{ 346 return ide_pci_register_driver(&ns87415_pci_driver); 347} 348 349static void __exit ns87415_ide_exit(void) 350{ 351 pci_unregister_driver(&ns87415_pci_driver); 352} 353 354module_init(ns87415_ide_init); 355module_exit(ns87415_ide_exit); 356 357MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick"); 358MODULE_DESCRIPTION("PCI driver module for NS87415 IDE"); 359MODULE_LICENSE("GPL"); 360