pmac.c revision d58b0c39e32f1b410af4d070f9d1a1416057c166
1/* 2 * Support for IDE interfaces on PowerMacs. 3 * 4 * These IDE interfaces are memory-mapped and have a DBDMA channel 5 * for doing DMA. 6 * 7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt 8 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 * Some code taken from drivers/ide/ide-dma.c: 16 * 17 * Copyright (c) 1995-1998 Mark Lord 18 * 19 * TODO: - Use pre-calculated (kauai) timing tables all the time and 20 * get rid of the "rounded" tables used previously, so we have the 21 * same table format for all controllers and can then just have one 22 * big table 23 * 24 */ 25#include <linux/types.h> 26#include <linux/kernel.h> 27#include <linux/init.h> 28#include <linux/delay.h> 29#include <linux/ide.h> 30#include <linux/notifier.h> 31#include <linux/reboot.h> 32#include <linux/pci.h> 33#include <linux/adb.h> 34#include <linux/pmu.h> 35#include <linux/scatterlist.h> 36 37#include <asm/prom.h> 38#include <asm/io.h> 39#include <asm/dbdma.h> 40#include <asm/ide.h> 41#include <asm/pci-bridge.h> 42#include <asm/machdep.h> 43#include <asm/pmac_feature.h> 44#include <asm/sections.h> 45#include <asm/irq.h> 46#include <asm/mediabay.h> 47 48#define DRV_NAME "ide-pmac" 49 50#undef IDE_PMAC_DEBUG 51 52#define DMA_WAIT_TIMEOUT 50 53 54typedef struct pmac_ide_hwif { 55 unsigned long regbase; 56 int irq; 57 int kind; 58 int aapl_bus_id; 59 unsigned broken_dma : 1; 60 unsigned broken_dma_warn : 1; 61 struct device_node* node; 62 struct macio_dev *mdev; 63 u32 timings[4]; 64 volatile u32 __iomem * *kauai_fcr; 65 ide_hwif_t *hwif; 66 67 /* Those fields are duplicating what is in hwif. We currently 68 * can't use the hwif ones because of some assumptions that are 69 * beeing done by the generic code about the kind of dma controller 70 * and format of the dma table. This will have to be fixed though. 71 */ 72 volatile struct dbdma_regs __iomem * dma_regs; 73 struct dbdma_cmd* dma_table_cpu; 74} pmac_ide_hwif_t; 75 76enum { 77 controller_ohare, /* OHare based */ 78 controller_heathrow, /* Heathrow/Paddington */ 79 controller_kl_ata3, /* KeyLargo ATA-3 */ 80 controller_kl_ata4, /* KeyLargo ATA-4 */ 81 controller_un_ata6, /* UniNorth2 ATA-6 */ 82 controller_k2_ata6, /* K2 ATA-6 */ 83 controller_sh_ata6, /* Shasta ATA-6 */ 84}; 85 86static const char* model_name[] = { 87 "OHare ATA", /* OHare based */ 88 "Heathrow ATA", /* Heathrow/Paddington */ 89 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */ 90 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */ 91 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */ 92 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */ 93 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */ 94}; 95 96/* 97 * Extra registers, both 32-bit little-endian 98 */ 99#define IDE_TIMING_CONFIG 0x200 100#define IDE_INTERRUPT 0x300 101 102/* Kauai (U2) ATA has different register setup */ 103#define IDE_KAUAI_PIO_CONFIG 0x200 104#define IDE_KAUAI_ULTRA_CONFIG 0x210 105#define IDE_KAUAI_POLL_CONFIG 0x220 106 107/* 108 * Timing configuration register definitions 109 */ 110 111/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */ 112#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS) 113#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS) 114#define IDE_SYSCLK_NS 30 /* 33Mhz cell */ 115#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */ 116 117/* 133Mhz cell, found in shasta. 118 * See comments about 100 Mhz Uninorth 2... 119 * Note that PIO_MASK and MDMA_MASK seem to overlap 120 */ 121#define TR_133_PIOREG_PIO_MASK 0xff000fff 122#define TR_133_PIOREG_MDMA_MASK 0x00fff800 123#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff 124#define TR_133_UDMAREG_UDMA_EN 0x00000001 125 126/* 100Mhz cell, found in Uninorth 2. I don't have much infos about 127 * this one yet, it appears as a pci device (106b/0033) on uninorth 128 * internal PCI bus and it's clock is controlled like gem or fw. It 129 * appears to be an evolution of keylargo ATA4 with a timing register 130 * extended to 2 32bits registers and a similar DBDMA channel. Other 131 * registers seem to exist but I can't tell much about them. 132 * 133 * So far, I'm using pre-calculated tables for this extracted from 134 * the values used by the MacOS X driver. 135 * 136 * The "PIO" register controls PIO and MDMA timings, the "ULTRA" 137 * register controls the UDMA timings. At least, it seems bit 0 138 * of this one enables UDMA vs. MDMA, and bits 4..7 are the 139 * cycle time in units of 10ns. Bits 8..15 are used by I don't 140 * know their meaning yet 141 */ 142#define TR_100_PIOREG_PIO_MASK 0xff000fff 143#define TR_100_PIOREG_MDMA_MASK 0x00fff000 144#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff 145#define TR_100_UDMAREG_UDMA_EN 0x00000001 146 147 148/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on 149 * 40 connector cable and to 4 on 80 connector one. 150 * Clock unit is 15ns (66Mhz) 151 * 152 * 3 Values can be programmed: 153 * - Write data setup, which appears to match the cycle time. They 154 * also call it DIOW setup. 155 * - Ready to pause time (from spec) 156 * - Address setup. That one is weird. I don't see where exactly 157 * it fits in UDMA cycles, I got it's name from an obscure piece 158 * of commented out code in Darwin. They leave it to 0, we do as 159 * well, despite a comment that would lead to think it has a 160 * min value of 45ns. 161 * Apple also add 60ns to the write data setup (or cycle time ?) on 162 * reads. 163 */ 164#define TR_66_UDMA_MASK 0xfff00000 165#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */ 166#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */ 167#define TR_66_UDMA_ADDRSETUP_SHIFT 29 168#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */ 169#define TR_66_UDMA_RDY2PAUS_SHIFT 25 170#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */ 171#define TR_66_UDMA_WRDATASETUP_SHIFT 21 172#define TR_66_MDMA_MASK 0x000ffc00 173#define TR_66_MDMA_RECOVERY_MASK 0x000f8000 174#define TR_66_MDMA_RECOVERY_SHIFT 15 175#define TR_66_MDMA_ACCESS_MASK 0x00007c00 176#define TR_66_MDMA_ACCESS_SHIFT 10 177#define TR_66_PIO_MASK 0x000003ff 178#define TR_66_PIO_RECOVERY_MASK 0x000003e0 179#define TR_66_PIO_RECOVERY_SHIFT 5 180#define TR_66_PIO_ACCESS_MASK 0x0000001f 181#define TR_66_PIO_ACCESS_SHIFT 0 182 183/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo 184 * Can do pio & mdma modes, clock unit is 30ns (33Mhz) 185 * 186 * The access time and recovery time can be programmed. Some older 187 * Darwin code base limit OHare to 150ns cycle time. I decided to do 188 * the same here fore safety against broken old hardware ;) 189 * The HalfTick bit, when set, adds half a clock (15ns) to the access 190 * time and removes one from recovery. It's not supported on KeyLargo 191 * implementation afaik. The E bit appears to be set for PIO mode 0 and 192 * is used to reach long timings used in this mode. 193 */ 194#define TR_33_MDMA_MASK 0x003ff800 195#define TR_33_MDMA_RECOVERY_MASK 0x001f0000 196#define TR_33_MDMA_RECOVERY_SHIFT 16 197#define TR_33_MDMA_ACCESS_MASK 0x0000f800 198#define TR_33_MDMA_ACCESS_SHIFT 11 199#define TR_33_MDMA_HALFTICK 0x00200000 200#define TR_33_PIO_MASK 0x000007ff 201#define TR_33_PIO_E 0x00000400 202#define TR_33_PIO_RECOVERY_MASK 0x000003e0 203#define TR_33_PIO_RECOVERY_SHIFT 5 204#define TR_33_PIO_ACCESS_MASK 0x0000001f 205#define TR_33_PIO_ACCESS_SHIFT 0 206 207/* 208 * Interrupt register definitions 209 */ 210#define IDE_INTR_DMA 0x80000000 211#define IDE_INTR_DEVICE 0x40000000 212 213/* 214 * FCR Register on Kauai. Not sure what bit 0x4 is ... 215 */ 216#define KAUAI_FCR_UATA_MAGIC 0x00000004 217#define KAUAI_FCR_UATA_RESET_N 0x00000002 218#define KAUAI_FCR_UATA_ENABLE 0x00000001 219 220/* Rounded Multiword DMA timings 221 * 222 * I gave up finding a generic formula for all controller 223 * types and instead, built tables based on timing values 224 * used by Apple in Darwin's implementation. 225 */ 226struct mdma_timings_t { 227 int accessTime; 228 int recoveryTime; 229 int cycleTime; 230}; 231 232struct mdma_timings_t mdma_timings_33[] = 233{ 234 { 240, 240, 480 }, 235 { 180, 180, 360 }, 236 { 135, 135, 270 }, 237 { 120, 120, 240 }, 238 { 105, 105, 210 }, 239 { 90, 90, 180 }, 240 { 75, 75, 150 }, 241 { 75, 45, 120 }, 242 { 0, 0, 0 } 243}; 244 245struct mdma_timings_t mdma_timings_33k[] = 246{ 247 { 240, 240, 480 }, 248 { 180, 180, 360 }, 249 { 150, 150, 300 }, 250 { 120, 120, 240 }, 251 { 90, 120, 210 }, 252 { 90, 90, 180 }, 253 { 90, 60, 150 }, 254 { 90, 30, 120 }, 255 { 0, 0, 0 } 256}; 257 258struct mdma_timings_t mdma_timings_66[] = 259{ 260 { 240, 240, 480 }, 261 { 180, 180, 360 }, 262 { 135, 135, 270 }, 263 { 120, 120, 240 }, 264 { 105, 105, 210 }, 265 { 90, 90, 180 }, 266 { 90, 75, 165 }, 267 { 75, 45, 120 }, 268 { 0, 0, 0 } 269}; 270 271/* KeyLargo ATA-4 Ultra DMA timings (rounded) */ 272struct { 273 int addrSetup; /* ??? */ 274 int rdy2pause; 275 int wrDataSetup; 276} kl66_udma_timings[] = 277{ 278 { 0, 180, 120 }, /* Mode 0 */ 279 { 0, 150, 90 }, /* 1 */ 280 { 0, 120, 60 }, /* 2 */ 281 { 0, 90, 45 }, /* 3 */ 282 { 0, 90, 30 } /* 4 */ 283}; 284 285/* UniNorth 2 ATA/100 timings */ 286struct kauai_timing { 287 int cycle_time; 288 u32 timing_reg; 289}; 290 291static struct kauai_timing kauai_pio_timings[] = 292{ 293 { 930 , 0x08000fff }, 294 { 600 , 0x08000a92 }, 295 { 383 , 0x0800060f }, 296 { 360 , 0x08000492 }, 297 { 330 , 0x0800048f }, 298 { 300 , 0x080003cf }, 299 { 270 , 0x080003cc }, 300 { 240 , 0x0800038b }, 301 { 239 , 0x0800030c }, 302 { 180 , 0x05000249 }, 303 { 120 , 0x04000148 }, 304 { 0 , 0 }, 305}; 306 307static struct kauai_timing kauai_mdma_timings[] = 308{ 309 { 1260 , 0x00fff000 }, 310 { 480 , 0x00618000 }, 311 { 360 , 0x00492000 }, 312 { 270 , 0x0038e000 }, 313 { 240 , 0x0030c000 }, 314 { 210 , 0x002cb000 }, 315 { 180 , 0x00249000 }, 316 { 150 , 0x00209000 }, 317 { 120 , 0x00148000 }, 318 { 0 , 0 }, 319}; 320 321static struct kauai_timing kauai_udma_timings[] = 322{ 323 { 120 , 0x000070c0 }, 324 { 90 , 0x00005d80 }, 325 { 60 , 0x00004a60 }, 326 { 45 , 0x00003a50 }, 327 { 30 , 0x00002a30 }, 328 { 20 , 0x00002921 }, 329 { 0 , 0 }, 330}; 331 332static struct kauai_timing shasta_pio_timings[] = 333{ 334 { 930 , 0x08000fff }, 335 { 600 , 0x0A000c97 }, 336 { 383 , 0x07000712 }, 337 { 360 , 0x040003cd }, 338 { 330 , 0x040003cd }, 339 { 300 , 0x040003cd }, 340 { 270 , 0x040003cd }, 341 { 240 , 0x040003cd }, 342 { 239 , 0x040003cd }, 343 { 180 , 0x0400028b }, 344 { 120 , 0x0400010a }, 345 { 0 , 0 }, 346}; 347 348static struct kauai_timing shasta_mdma_timings[] = 349{ 350 { 1260 , 0x00fff000 }, 351 { 480 , 0x00820800 }, 352 { 360 , 0x00820800 }, 353 { 270 , 0x00820800 }, 354 { 240 , 0x00820800 }, 355 { 210 , 0x00820800 }, 356 { 180 , 0x00820800 }, 357 { 150 , 0x0028b000 }, 358 { 120 , 0x001ca000 }, 359 { 0 , 0 }, 360}; 361 362static struct kauai_timing shasta_udma133_timings[] = 363{ 364 { 120 , 0x00035901, }, 365 { 90 , 0x000348b1, }, 366 { 60 , 0x00033881, }, 367 { 45 , 0x00033861, }, 368 { 30 , 0x00033841, }, 369 { 20 , 0x00033031, }, 370 { 15 , 0x00033021, }, 371 { 0 , 0 }, 372}; 373 374 375static inline u32 376kauai_lookup_timing(struct kauai_timing* table, int cycle_time) 377{ 378 int i; 379 380 for (i=0; table[i].cycle_time; i++) 381 if (cycle_time > table[i+1].cycle_time) 382 return table[i].timing_reg; 383 BUG(); 384 return 0; 385} 386 387/* allow up to 256 DBDMA commands per xfer */ 388#define MAX_DCMDS 256 389 390/* 391 * Wait 1s for disk to answer on IDE bus after a hard reset 392 * of the device (via GPIO/FCR). 393 * 394 * Some devices seem to "pollute" the bus even after dropping 395 * the BSY bit (typically some combo drives slave on the UDMA 396 * bus) after a hard reset. Since we hard reset all drives on 397 * KeyLargo ATA66, we have to keep that delay around. I may end 398 * up not hard resetting anymore on these and keep the delay only 399 * for older interfaces instead (we have to reset when coming 400 * from MacOS...) --BenH. 401 */ 402#define IDE_WAKEUP_DELAY (1*HZ) 403 404static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *); 405 406#define PMAC_IDE_REG(x) \ 407 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x))) 408 409/* 410 * Apply the timings of the proper unit (master/slave) to the shared 411 * timing register when selecting that unit. This version is for 412 * ASICs with a single timing register 413 */ 414static void pmac_ide_apply_timings(ide_drive_t *drive) 415{ 416 ide_hwif_t *hwif = drive->hwif; 417 pmac_ide_hwif_t *pmif = 418 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 419 420 if (drive->dn & 1) 421 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG)); 422 else 423 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG)); 424 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); 425} 426 427/* 428 * Apply the timings of the proper unit (master/slave) to the shared 429 * timing register when selecting that unit. This version is for 430 * ASICs with a dual timing register (Kauai) 431 */ 432static void pmac_ide_kauai_apply_timings(ide_drive_t *drive) 433{ 434 ide_hwif_t *hwif = drive->hwif; 435 pmac_ide_hwif_t *pmif = 436 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 437 438 if (drive->dn & 1) { 439 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); 440 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); 441 } else { 442 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); 443 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); 444 } 445 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); 446} 447 448/* 449 * Force an update of controller timing values for a given drive 450 */ 451static void 452pmac_ide_do_update_timings(ide_drive_t *drive) 453{ 454 ide_hwif_t *hwif = drive->hwif; 455 pmac_ide_hwif_t *pmif = 456 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 457 458 if (pmif->kind == controller_sh_ata6 || 459 pmif->kind == controller_un_ata6 || 460 pmif->kind == controller_k2_ata6) 461 pmac_ide_kauai_apply_timings(drive); 462 else 463 pmac_ide_apply_timings(drive); 464} 465 466static void pmac_dev_select(ide_drive_t *drive) 467{ 468 pmac_ide_apply_timings(drive); 469 470 writeb(drive->select | ATA_DEVICE_OBS, 471 (void __iomem *)drive->hwif->io_ports.device_addr); 472} 473 474static void pmac_kauai_dev_select(ide_drive_t *drive) 475{ 476 pmac_ide_kauai_apply_timings(drive); 477 478 writeb(drive->select | ATA_DEVICE_OBS, 479 (void __iomem *)drive->hwif->io_ports.device_addr); 480} 481 482static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd) 483{ 484 writeb(cmd, (void __iomem *)hwif->io_ports.command_addr); 485 (void)readl((void __iomem *)(hwif->io_ports.data_addr 486 + IDE_TIMING_CONFIG)); 487} 488 489static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl) 490{ 491 writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr); 492 (void)readl((void __iomem *)(hwif->io_ports.data_addr 493 + IDE_TIMING_CONFIG)); 494} 495 496/* 497 * Old tuning functions (called on hdparm -p), sets up drive PIO timings 498 */ 499static void 500pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio) 501{ 502 ide_hwif_t *hwif = drive->hwif; 503 pmac_ide_hwif_t *pmif = 504 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 505 struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio); 506 u32 *timings, t; 507 unsigned accessTicks, recTicks; 508 unsigned accessTime, recTime; 509 unsigned int cycle_time; 510 511 /* which drive is it ? */ 512 timings = &pmif->timings[drive->dn & 1]; 513 t = *timings; 514 515 cycle_time = ide_pio_cycle_time(drive, pio); 516 517 switch (pmif->kind) { 518 case controller_sh_ata6: { 519 /* 133Mhz cell */ 520 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time); 521 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr; 522 break; 523 } 524 case controller_un_ata6: 525 case controller_k2_ata6: { 526 /* 100Mhz cell */ 527 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time); 528 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr; 529 break; 530 } 531 case controller_kl_ata4: 532 /* 66Mhz cell */ 533 recTime = cycle_time - tim->active - tim->setup; 534 recTime = max(recTime, 150U); 535 accessTime = tim->active; 536 accessTime = max(accessTime, 150U); 537 accessTicks = SYSCLK_TICKS_66(accessTime); 538 accessTicks = min(accessTicks, 0x1fU); 539 recTicks = SYSCLK_TICKS_66(recTime); 540 recTicks = min(recTicks, 0x1fU); 541 t = (t & ~TR_66_PIO_MASK) | 542 (accessTicks << TR_66_PIO_ACCESS_SHIFT) | 543 (recTicks << TR_66_PIO_RECOVERY_SHIFT); 544 break; 545 default: { 546 /* 33Mhz cell */ 547 int ebit = 0; 548 recTime = cycle_time - tim->active - tim->setup; 549 recTime = max(recTime, 150U); 550 accessTime = tim->active; 551 accessTime = max(accessTime, 150U); 552 accessTicks = SYSCLK_TICKS(accessTime); 553 accessTicks = min(accessTicks, 0x1fU); 554 accessTicks = max(accessTicks, 4U); 555 recTicks = SYSCLK_TICKS(recTime); 556 recTicks = min(recTicks, 0x1fU); 557 recTicks = max(recTicks, 5U) - 4; 558 if (recTicks > 9) { 559 recTicks--; /* guess, but it's only for PIO0, so... */ 560 ebit = 1; 561 } 562 t = (t & ~TR_33_PIO_MASK) | 563 (accessTicks << TR_33_PIO_ACCESS_SHIFT) | 564 (recTicks << TR_33_PIO_RECOVERY_SHIFT); 565 if (ebit) 566 t |= TR_33_PIO_E; 567 break; 568 } 569 } 570 571#ifdef IDE_PMAC_DEBUG 572 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n", 573 drive->name, pio, *timings); 574#endif 575 576 *timings = t; 577 pmac_ide_do_update_timings(drive); 578} 579 580/* 581 * Calculate KeyLargo ATA/66 UDMA timings 582 */ 583static int 584set_timings_udma_ata4(u32 *timings, u8 speed) 585{ 586 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks; 587 588 if (speed > XFER_UDMA_4) 589 return 1; 590 591 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause); 592 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup); 593 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup); 594 595 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) | 596 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) | 597 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) | 598 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) | 599 TR_66_UDMA_EN; 600#ifdef IDE_PMAC_DEBUG 601 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n", 602 speed & 0xf, *timings); 603#endif 604 605 return 0; 606} 607 608/* 609 * Calculate Kauai ATA/100 UDMA timings 610 */ 611static int 612set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed) 613{ 614 struct ide_timing *t = ide_timing_find_mode(speed); 615 u32 tr; 616 617 if (speed > XFER_UDMA_5 || t == NULL) 618 return 1; 619 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma); 620 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr; 621 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN; 622 623 return 0; 624} 625 626/* 627 * Calculate Shasta ATA/133 UDMA timings 628 */ 629static int 630set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed) 631{ 632 struct ide_timing *t = ide_timing_find_mode(speed); 633 u32 tr; 634 635 if (speed > XFER_UDMA_6 || t == NULL) 636 return 1; 637 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma); 638 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr; 639 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN; 640 641 return 0; 642} 643 644/* 645 * Calculate MDMA timings for all cells 646 */ 647static void 648set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, 649 u8 speed) 650{ 651 u16 *id = drive->id; 652 int cycleTime, accessTime = 0, recTime = 0; 653 unsigned accessTicks, recTicks; 654 struct mdma_timings_t* tm = NULL; 655 int i; 656 657 /* Get default cycle time for mode */ 658 switch(speed & 0xf) { 659 case 0: cycleTime = 480; break; 660 case 1: cycleTime = 150; break; 661 case 2: cycleTime = 120; break; 662 default: 663 BUG(); 664 break; 665 } 666 667 /* Check if drive provides explicit DMA cycle time */ 668 if ((id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_DMA_TIME]) 669 cycleTime = max_t(int, id[ATA_ID_EIDE_DMA_TIME], cycleTime); 670 671 /* OHare limits according to some old Apple sources */ 672 if ((intf_type == controller_ohare) && (cycleTime < 150)) 673 cycleTime = 150; 674 /* Get the proper timing array for this controller */ 675 switch(intf_type) { 676 case controller_sh_ata6: 677 case controller_un_ata6: 678 case controller_k2_ata6: 679 break; 680 case controller_kl_ata4: 681 tm = mdma_timings_66; 682 break; 683 case controller_kl_ata3: 684 tm = mdma_timings_33k; 685 break; 686 default: 687 tm = mdma_timings_33; 688 break; 689 } 690 if (tm != NULL) { 691 /* Lookup matching access & recovery times */ 692 i = -1; 693 for (;;) { 694 if (tm[i+1].cycleTime < cycleTime) 695 break; 696 i++; 697 } 698 cycleTime = tm[i].cycleTime; 699 accessTime = tm[i].accessTime; 700 recTime = tm[i].recoveryTime; 701 702#ifdef IDE_PMAC_DEBUG 703 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n", 704 drive->name, cycleTime, accessTime, recTime); 705#endif 706 } 707 switch(intf_type) { 708 case controller_sh_ata6: { 709 /* 133Mhz cell */ 710 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime); 711 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr; 712 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN; 713 } 714 case controller_un_ata6: 715 case controller_k2_ata6: { 716 /* 100Mhz cell */ 717 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime); 718 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr; 719 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN; 720 } 721 break; 722 case controller_kl_ata4: 723 /* 66Mhz cell */ 724 accessTicks = SYSCLK_TICKS_66(accessTime); 725 accessTicks = min(accessTicks, 0x1fU); 726 accessTicks = max(accessTicks, 0x1U); 727 recTicks = SYSCLK_TICKS_66(recTime); 728 recTicks = min(recTicks, 0x1fU); 729 recTicks = max(recTicks, 0x3U); 730 /* Clear out mdma bits and disable udma */ 731 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) | 732 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) | 733 (recTicks << TR_66_MDMA_RECOVERY_SHIFT); 734 break; 735 case controller_kl_ata3: 736 /* 33Mhz cell on KeyLargo */ 737 accessTicks = SYSCLK_TICKS(accessTime); 738 accessTicks = max(accessTicks, 1U); 739 accessTicks = min(accessTicks, 0x1fU); 740 accessTime = accessTicks * IDE_SYSCLK_NS; 741 recTicks = SYSCLK_TICKS(recTime); 742 recTicks = max(recTicks, 1U); 743 recTicks = min(recTicks, 0x1fU); 744 *timings = ((*timings) & ~TR_33_MDMA_MASK) | 745 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) | 746 (recTicks << TR_33_MDMA_RECOVERY_SHIFT); 747 break; 748 default: { 749 /* 33Mhz cell on others */ 750 int halfTick = 0; 751 int origAccessTime = accessTime; 752 int origRecTime = recTime; 753 754 accessTicks = SYSCLK_TICKS(accessTime); 755 accessTicks = max(accessTicks, 1U); 756 accessTicks = min(accessTicks, 0x1fU); 757 accessTime = accessTicks * IDE_SYSCLK_NS; 758 recTicks = SYSCLK_TICKS(recTime); 759 recTicks = max(recTicks, 2U) - 1; 760 recTicks = min(recTicks, 0x1fU); 761 recTime = (recTicks + 1) * IDE_SYSCLK_NS; 762 if ((accessTicks > 1) && 763 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) && 764 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) { 765 halfTick = 1; 766 accessTicks--; 767 } 768 *timings = ((*timings) & ~TR_33_MDMA_MASK) | 769 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) | 770 (recTicks << TR_33_MDMA_RECOVERY_SHIFT); 771 if (halfTick) 772 *timings |= TR_33_MDMA_HALFTICK; 773 } 774 } 775#ifdef IDE_PMAC_DEBUG 776 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n", 777 drive->name, speed & 0xf, *timings); 778#endif 779} 780 781static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed) 782{ 783 ide_hwif_t *hwif = drive->hwif; 784 pmac_ide_hwif_t *pmif = 785 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 786 int ret = 0; 787 u32 *timings, *timings2, tl[2]; 788 u8 unit = drive->dn & 1; 789 790 timings = &pmif->timings[unit]; 791 timings2 = &pmif->timings[unit+2]; 792 793 /* Copy timings to local image */ 794 tl[0] = *timings; 795 tl[1] = *timings2; 796 797 if (speed >= XFER_UDMA_0) { 798 if (pmif->kind == controller_kl_ata4) 799 ret = set_timings_udma_ata4(&tl[0], speed); 800 else if (pmif->kind == controller_un_ata6 801 || pmif->kind == controller_k2_ata6) 802 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed); 803 else if (pmif->kind == controller_sh_ata6) 804 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed); 805 else 806 ret = -1; 807 } else 808 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed); 809 810 if (ret) 811 return; 812 813 /* Apply timings to controller */ 814 *timings = tl[0]; 815 *timings2 = tl[1]; 816 817 pmac_ide_do_update_timings(drive); 818} 819 820/* 821 * Blast some well known "safe" values to the timing registers at init or 822 * wakeup from sleep time, before we do real calculation 823 */ 824static void 825sanitize_timings(pmac_ide_hwif_t *pmif) 826{ 827 unsigned int value, value2 = 0; 828 829 switch(pmif->kind) { 830 case controller_sh_ata6: 831 value = 0x0a820c97; 832 value2 = 0x00033031; 833 break; 834 case controller_un_ata6: 835 case controller_k2_ata6: 836 value = 0x08618a92; 837 value2 = 0x00002921; 838 break; 839 case controller_kl_ata4: 840 value = 0x0008438c; 841 break; 842 case controller_kl_ata3: 843 value = 0x00084526; 844 break; 845 case controller_heathrow: 846 case controller_ohare: 847 default: 848 value = 0x00074526; 849 break; 850 } 851 pmif->timings[0] = pmif->timings[1] = value; 852 pmif->timings[2] = pmif->timings[3] = value2; 853} 854 855static int on_media_bay(pmac_ide_hwif_t *pmif) 856{ 857 return pmif->mdev && pmif->mdev->media_bay != NULL; 858} 859 860/* Suspend call back, should be called after the child devices 861 * have actually been suspended 862 */ 863static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif) 864{ 865 /* We clear the timings */ 866 pmif->timings[0] = 0; 867 pmif->timings[1] = 0; 868 869 disable_irq(pmif->irq); 870 871 /* The media bay will handle itself just fine */ 872 if (on_media_bay(pmif)) 873 return 0; 874 875 /* Kauai has bus control FCRs directly here */ 876 if (pmif->kauai_fcr) { 877 u32 fcr = readl(pmif->kauai_fcr); 878 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE); 879 writel(fcr, pmif->kauai_fcr); 880 } 881 882 /* Disable the bus on older machines and the cell on kauai */ 883 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 884 0); 885 886 return 0; 887} 888 889/* Resume call back, should be called before the child devices 890 * are resumed 891 */ 892static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif) 893{ 894 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */ 895 if (!on_media_bay(pmif)) { 896 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1); 897 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1); 898 msleep(10); 899 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0); 900 901 /* Kauai has it different */ 902 if (pmif->kauai_fcr) { 903 u32 fcr = readl(pmif->kauai_fcr); 904 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE; 905 writel(fcr, pmif->kauai_fcr); 906 } 907 908 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY)); 909 } 910 911 /* Sanitize drive timings */ 912 sanitize_timings(pmif); 913 914 enable_irq(pmif->irq); 915 916 return 0; 917} 918 919static u8 pmac_ide_cable_detect(ide_hwif_t *hwif) 920{ 921 pmac_ide_hwif_t *pmif = 922 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 923 struct device_node *np = pmif->node; 924 const char *cable = of_get_property(np, "cable-type", NULL); 925 struct device_node *root = of_find_node_by_path("/"); 926 const char *model = of_get_property(root, "model", NULL); 927 928 /* Get cable type from device-tree. */ 929 if (cable && !strncmp(cable, "80-", 3)) { 930 /* Some drives fail to detect 80c cable in PowerBook */ 931 /* These machine use proprietary short IDE cable anyway */ 932 if (!strncmp(model, "PowerBook", 9)) 933 return ATA_CBL_PATA40_SHORT; 934 else 935 return ATA_CBL_PATA80; 936 } 937 938 /* 939 * G5's seem to have incorrect cable type in device-tree. 940 * Let's assume they have a 80 conductor cable, this seem 941 * to be always the case unless the user mucked around. 942 */ 943 if (of_device_is_compatible(np, "K2-UATA") || 944 of_device_is_compatible(np, "shasta-ata")) 945 return ATA_CBL_PATA80; 946 947 return ATA_CBL_PATA40; 948} 949 950static void pmac_ide_init_dev(ide_drive_t *drive) 951{ 952 ide_hwif_t *hwif = drive->hwif; 953 pmac_ide_hwif_t *pmif = 954 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 955 956 if (on_media_bay(pmif)) { 957 if (check_media_bay(pmif->mdev->media_bay) == MB_CD) { 958 drive->dev_flags &= ~IDE_DFLAG_NOPROBE; 959 return; 960 } 961 drive->dev_flags |= IDE_DFLAG_NOPROBE; 962 } 963} 964 965static const struct ide_tp_ops pmac_tp_ops = { 966 .exec_command = pmac_exec_command, 967 .read_status = ide_read_status, 968 .read_altstatus = ide_read_altstatus, 969 .write_devctl = pmac_write_devctl, 970 971 .dev_select = pmac_dev_select, 972 .tf_load = ide_tf_load, 973 .tf_read = ide_tf_read, 974 975 .input_data = ide_input_data, 976 .output_data = ide_output_data, 977}; 978 979static const struct ide_tp_ops pmac_ata6_tp_ops = { 980 .exec_command = pmac_exec_command, 981 .read_status = ide_read_status, 982 .read_altstatus = ide_read_altstatus, 983 .write_devctl = pmac_write_devctl, 984 985 .dev_select = pmac_kauai_dev_select, 986 .tf_load = ide_tf_load, 987 .tf_read = ide_tf_read, 988 989 .input_data = ide_input_data, 990 .output_data = ide_output_data, 991}; 992 993static const struct ide_port_ops pmac_ide_ata4_port_ops = { 994 .init_dev = pmac_ide_init_dev, 995 .set_pio_mode = pmac_ide_set_pio_mode, 996 .set_dma_mode = pmac_ide_set_dma_mode, 997 .cable_detect = pmac_ide_cable_detect, 998}; 999 1000static const struct ide_port_ops pmac_ide_port_ops = { 1001 .init_dev = pmac_ide_init_dev, 1002 .set_pio_mode = pmac_ide_set_pio_mode, 1003 .set_dma_mode = pmac_ide_set_dma_mode, 1004}; 1005 1006static const struct ide_dma_ops pmac_dma_ops; 1007 1008static const struct ide_port_info pmac_port_info = { 1009 .name = DRV_NAME, 1010 .init_dma = pmac_ide_init_dma, 1011 .chipset = ide_pmac, 1012 .tp_ops = &pmac_tp_ops, 1013 .port_ops = &pmac_ide_port_ops, 1014 .dma_ops = &pmac_dma_ops, 1015 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA | 1016 IDE_HFLAG_POST_SET_MODE | 1017 IDE_HFLAG_MMIO | 1018 IDE_HFLAG_UNMASK_IRQS, 1019 .pio_mask = ATA_PIO4, 1020 .mwdma_mask = ATA_MWDMA2, 1021}; 1022 1023/* 1024 * Setup, register & probe an IDE channel driven by this driver, this is 1025 * called by one of the 2 probe functions (macio or PCI). 1026 */ 1027static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif, 1028 struct ide_hw *hw) 1029{ 1030 struct device_node *np = pmif->node; 1031 const int *bidp; 1032 struct ide_host *host; 1033 ide_hwif_t *hwif; 1034 struct ide_hw *hws[] = { hw }; 1035 struct ide_port_info d = pmac_port_info; 1036 int rc; 1037 1038 pmif->broken_dma = pmif->broken_dma_warn = 0; 1039 if (of_device_is_compatible(np, "shasta-ata")) { 1040 pmif->kind = controller_sh_ata6; 1041 d.tp_ops = &pmac_ata6_tp_ops; 1042 d.port_ops = &pmac_ide_ata4_port_ops; 1043 d.udma_mask = ATA_UDMA6; 1044 } else if (of_device_is_compatible(np, "kauai-ata")) { 1045 pmif->kind = controller_un_ata6; 1046 d.tp_ops = &pmac_ata6_tp_ops; 1047 d.port_ops = &pmac_ide_ata4_port_ops; 1048 d.udma_mask = ATA_UDMA5; 1049 } else if (of_device_is_compatible(np, "K2-UATA")) { 1050 pmif->kind = controller_k2_ata6; 1051 d.tp_ops = &pmac_ata6_tp_ops; 1052 d.port_ops = &pmac_ide_ata4_port_ops; 1053 d.udma_mask = ATA_UDMA5; 1054 } else if (of_device_is_compatible(np, "keylargo-ata")) { 1055 if (strcmp(np->name, "ata-4") == 0) { 1056 pmif->kind = controller_kl_ata4; 1057 d.port_ops = &pmac_ide_ata4_port_ops; 1058 d.udma_mask = ATA_UDMA4; 1059 } else 1060 pmif->kind = controller_kl_ata3; 1061 } else if (of_device_is_compatible(np, "heathrow-ata")) { 1062 pmif->kind = controller_heathrow; 1063 } else { 1064 pmif->kind = controller_ohare; 1065 pmif->broken_dma = 1; 1066 } 1067 1068 bidp = of_get_property(np, "AAPL,bus-id", NULL); 1069 pmif->aapl_bus_id = bidp ? *bidp : 0; 1070 1071 /* On Kauai-type controllers, we make sure the FCR is correct */ 1072 if (pmif->kauai_fcr) 1073 writel(KAUAI_FCR_UATA_MAGIC | 1074 KAUAI_FCR_UATA_RESET_N | 1075 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr); 1076 1077 /* Make sure we have sane timings */ 1078 sanitize_timings(pmif); 1079 1080 /* If we are on a media bay, wait for it to settle and lock it */ 1081 if (pmif->mdev) 1082 lock_media_bay(pmif->mdev->media_bay); 1083 1084 host = ide_host_alloc(&d, hws, 1); 1085 if (host == NULL) { 1086 rc = -ENOMEM; 1087 goto bail; 1088 } 1089 hwif = pmif->hwif = host->ports[0]; 1090 1091 if (on_media_bay(pmif)) { 1092 /* Fixup bus ID for media bay */ 1093 if (!bidp) 1094 pmif->aapl_bus_id = 1; 1095 } else if (pmif->kind == controller_ohare) { 1096 /* The code below is having trouble on some ohare machines 1097 * (timing related ?). Until I can put my hand on one of these 1098 * units, I keep the old way 1099 */ 1100 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1); 1101 } else { 1102 /* This is necessary to enable IDE when net-booting */ 1103 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1); 1104 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1); 1105 msleep(10); 1106 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0); 1107 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY)); 1108 } 1109 1110 printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), " 1111 "bus ID %d%s, irq %d\n", model_name[pmif->kind], 1112 pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id, 1113 on_media_bay(pmif) ? " (mediabay)" : "", hw->irq); 1114 1115 rc = ide_host_register(host, &d, hws); 1116 if (rc) 1117 pmif->hwif = NULL; 1118 1119 if (pmif->mdev) 1120 unlock_media_bay(pmif->mdev->media_bay); 1121 1122 bail: 1123 if (rc && host) 1124 ide_host_free(host); 1125 return rc; 1126} 1127 1128static void __devinit pmac_ide_init_ports(struct ide_hw *hw, unsigned long base) 1129{ 1130 int i; 1131 1132 for (i = 0; i < 8; ++i) 1133 hw->io_ports_array[i] = base + i * 0x10; 1134 1135 hw->io_ports.ctl_addr = base + 0x160; 1136} 1137 1138/* 1139 * Attach to a macio probed interface 1140 */ 1141static int __devinit 1142pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match) 1143{ 1144 void __iomem *base; 1145 unsigned long regbase; 1146 pmac_ide_hwif_t *pmif; 1147 int irq, rc; 1148 struct ide_hw hw; 1149 1150 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL); 1151 if (pmif == NULL) 1152 return -ENOMEM; 1153 1154 if (macio_resource_count(mdev) == 0) { 1155 printk(KERN_WARNING "ide-pmac: no address for %s\n", 1156 mdev->ofdev.node->full_name); 1157 rc = -ENXIO; 1158 goto out_free_pmif; 1159 } 1160 1161 /* Request memory resource for IO ports */ 1162 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) { 1163 printk(KERN_ERR "ide-pmac: can't request MMIO resource for " 1164 "%s!\n", mdev->ofdev.node->full_name); 1165 rc = -EBUSY; 1166 goto out_free_pmif; 1167 } 1168 1169 /* XXX This is bogus. Should be fixed in the registry by checking 1170 * the kind of host interrupt controller, a bit like gatwick 1171 * fixes in irq.c. That works well enough for the single case 1172 * where that happens though... 1173 */ 1174 if (macio_irq_count(mdev) == 0) { 1175 printk(KERN_WARNING "ide-pmac: no intrs for device %s, using " 1176 "13\n", mdev->ofdev.node->full_name); 1177 irq = irq_create_mapping(NULL, 13); 1178 } else 1179 irq = macio_irq(mdev, 0); 1180 1181 base = ioremap(macio_resource_start(mdev, 0), 0x400); 1182 regbase = (unsigned long) base; 1183 1184 pmif->mdev = mdev; 1185 pmif->node = mdev->ofdev.node; 1186 pmif->regbase = regbase; 1187 pmif->irq = irq; 1188 pmif->kauai_fcr = NULL; 1189 1190 if (macio_resource_count(mdev) >= 2) { 1191 if (macio_request_resource(mdev, 1, "ide-pmac (dma)")) 1192 printk(KERN_WARNING "ide-pmac: can't request DMA " 1193 "resource for %s!\n", 1194 mdev->ofdev.node->full_name); 1195 else 1196 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000); 1197 } else 1198 pmif->dma_regs = NULL; 1199 1200 dev_set_drvdata(&mdev->ofdev.dev, pmif); 1201 1202 memset(&hw, 0, sizeof(hw)); 1203 pmac_ide_init_ports(&hw, pmif->regbase); 1204 hw.irq = irq; 1205 hw.dev = &mdev->bus->pdev->dev; 1206 hw.parent = &mdev->ofdev.dev; 1207 1208 rc = pmac_ide_setup_device(pmif, &hw); 1209 if (rc != 0) { 1210 /* The inteface is released to the common IDE layer */ 1211 dev_set_drvdata(&mdev->ofdev.dev, NULL); 1212 iounmap(base); 1213 if (pmif->dma_regs) { 1214 iounmap(pmif->dma_regs); 1215 macio_release_resource(mdev, 1); 1216 } 1217 macio_release_resource(mdev, 0); 1218 kfree(pmif); 1219 } 1220 1221 return rc; 1222 1223out_free_pmif: 1224 kfree(pmif); 1225 return rc; 1226} 1227 1228static int 1229pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg) 1230{ 1231 pmac_ide_hwif_t *pmif = 1232 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); 1233 int rc = 0; 1234 1235 if (mesg.event != mdev->ofdev.dev.power.power_state.event 1236 && (mesg.event & PM_EVENT_SLEEP)) { 1237 rc = pmac_ide_do_suspend(pmif); 1238 if (rc == 0) 1239 mdev->ofdev.dev.power.power_state = mesg; 1240 } 1241 1242 return rc; 1243} 1244 1245static int 1246pmac_ide_macio_resume(struct macio_dev *mdev) 1247{ 1248 pmac_ide_hwif_t *pmif = 1249 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); 1250 int rc = 0; 1251 1252 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) { 1253 rc = pmac_ide_do_resume(pmif); 1254 if (rc == 0) 1255 mdev->ofdev.dev.power.power_state = PMSG_ON; 1256 } 1257 1258 return rc; 1259} 1260 1261/* 1262 * Attach to a PCI probed interface 1263 */ 1264static int __devinit 1265pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id) 1266{ 1267 struct device_node *np; 1268 pmac_ide_hwif_t *pmif; 1269 void __iomem *base; 1270 unsigned long rbase, rlen; 1271 int rc; 1272 struct ide_hw hw; 1273 1274 np = pci_device_to_OF_node(pdev); 1275 if (np == NULL) { 1276 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n"); 1277 return -ENODEV; 1278 } 1279 1280 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL); 1281 if (pmif == NULL) 1282 return -ENOMEM; 1283 1284 if (pci_enable_device(pdev)) { 1285 printk(KERN_WARNING "ide-pmac: Can't enable PCI device for " 1286 "%s\n", np->full_name); 1287 rc = -ENXIO; 1288 goto out_free_pmif; 1289 } 1290 pci_set_master(pdev); 1291 1292 if (pci_request_regions(pdev, "Kauai ATA")) { 1293 printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for " 1294 "%s\n", np->full_name); 1295 rc = -ENXIO; 1296 goto out_free_pmif; 1297 } 1298 1299 pmif->mdev = NULL; 1300 pmif->node = np; 1301 1302 rbase = pci_resource_start(pdev, 0); 1303 rlen = pci_resource_len(pdev, 0); 1304 1305 base = ioremap(rbase, rlen); 1306 pmif->regbase = (unsigned long) base + 0x2000; 1307 pmif->dma_regs = base + 0x1000; 1308 pmif->kauai_fcr = base; 1309 pmif->irq = pdev->irq; 1310 1311 pci_set_drvdata(pdev, pmif); 1312 1313 memset(&hw, 0, sizeof(hw)); 1314 pmac_ide_init_ports(&hw, pmif->regbase); 1315 hw.irq = pdev->irq; 1316 hw.dev = &pdev->dev; 1317 1318 rc = pmac_ide_setup_device(pmif, &hw); 1319 if (rc != 0) { 1320 /* The inteface is released to the common IDE layer */ 1321 pci_set_drvdata(pdev, NULL); 1322 iounmap(base); 1323 pci_release_regions(pdev); 1324 kfree(pmif); 1325 } 1326 1327 return rc; 1328 1329out_free_pmif: 1330 kfree(pmif); 1331 return rc; 1332} 1333 1334static int 1335pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg) 1336{ 1337 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev); 1338 int rc = 0; 1339 1340 if (mesg.event != pdev->dev.power.power_state.event 1341 && (mesg.event & PM_EVENT_SLEEP)) { 1342 rc = pmac_ide_do_suspend(pmif); 1343 if (rc == 0) 1344 pdev->dev.power.power_state = mesg; 1345 } 1346 1347 return rc; 1348} 1349 1350static int 1351pmac_ide_pci_resume(struct pci_dev *pdev) 1352{ 1353 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev); 1354 int rc = 0; 1355 1356 if (pdev->dev.power.power_state.event != PM_EVENT_ON) { 1357 rc = pmac_ide_do_resume(pmif); 1358 if (rc == 0) 1359 pdev->dev.power.power_state = PMSG_ON; 1360 } 1361 1362 return rc; 1363} 1364 1365#ifdef CONFIG_PMAC_MEDIABAY 1366static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state) 1367{ 1368 pmac_ide_hwif_t *pmif = 1369 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); 1370 1371 switch(mb_state) { 1372 case MB_CD: 1373 if (!pmif->hwif->present) 1374 ide_port_scan(pmif->hwif); 1375 break; 1376 default: 1377 if (pmif->hwif->present) 1378 ide_port_unregister_devices(pmif->hwif); 1379 } 1380} 1381#endif /* CONFIG_PMAC_MEDIABAY */ 1382 1383 1384static struct of_device_id pmac_ide_macio_match[] = 1385{ 1386 { 1387 .name = "IDE", 1388 }, 1389 { 1390 .name = "ATA", 1391 }, 1392 { 1393 .type = "ide", 1394 }, 1395 { 1396 .type = "ata", 1397 }, 1398 {}, 1399}; 1400 1401static struct macio_driver pmac_ide_macio_driver = 1402{ 1403 .name = "ide-pmac", 1404 .match_table = pmac_ide_macio_match, 1405 .probe = pmac_ide_macio_attach, 1406 .suspend = pmac_ide_macio_suspend, 1407 .resume = pmac_ide_macio_resume, 1408#ifdef CONFIG_PMAC_MEDIABAY 1409 .mediabay_event = pmac_ide_macio_mb_event, 1410#endif 1411}; 1412 1413static const struct pci_device_id pmac_ide_pci_match[] = { 1414 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 }, 1415 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 }, 1416 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 }, 1417 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 }, 1418 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 }, 1419 {}, 1420}; 1421 1422static struct pci_driver pmac_ide_pci_driver = { 1423 .name = "ide-pmac", 1424 .id_table = pmac_ide_pci_match, 1425 .probe = pmac_ide_pci_attach, 1426 .suspend = pmac_ide_pci_suspend, 1427 .resume = pmac_ide_pci_resume, 1428}; 1429MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match); 1430 1431int __init pmac_ide_probe(void) 1432{ 1433 int error; 1434 1435 if (!machine_is(powermac)) 1436 return -ENODEV; 1437 1438#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST 1439 error = pci_register_driver(&pmac_ide_pci_driver); 1440 if (error) 1441 goto out; 1442 error = macio_register_driver(&pmac_ide_macio_driver); 1443 if (error) { 1444 pci_unregister_driver(&pmac_ide_pci_driver); 1445 goto out; 1446 } 1447#else 1448 error = macio_register_driver(&pmac_ide_macio_driver); 1449 if (error) 1450 goto out; 1451 error = pci_register_driver(&pmac_ide_pci_driver); 1452 if (error) { 1453 macio_unregister_driver(&pmac_ide_macio_driver); 1454 goto out; 1455 } 1456#endif 1457out: 1458 return error; 1459} 1460 1461/* 1462 * pmac_ide_build_dmatable builds the DBDMA command list 1463 * for a transfer and sets the DBDMA channel to point to it. 1464 */ 1465static int pmac_ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd) 1466{ 1467 ide_hwif_t *hwif = drive->hwif; 1468 pmac_ide_hwif_t *pmif = 1469 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 1470 struct dbdma_cmd *table; 1471 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; 1472 struct scatterlist *sg; 1473 int wr = !!(cmd->tf_flags & IDE_TFLAG_WRITE); 1474 int i = cmd->sg_nents, count = 0; 1475 1476 /* DMA table is already aligned */ 1477 table = (struct dbdma_cmd *) pmif->dma_table_cpu; 1478 1479 /* Make sure DMA controller is stopped (necessary ?) */ 1480 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control); 1481 while (readl(&dma->status) & RUN) 1482 udelay(1); 1483 1484 /* Build DBDMA commands list */ 1485 sg = hwif->sg_table; 1486 while (i && sg_dma_len(sg)) { 1487 u32 cur_addr; 1488 u32 cur_len; 1489 1490 cur_addr = sg_dma_address(sg); 1491 cur_len = sg_dma_len(sg); 1492 1493 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) { 1494 if (pmif->broken_dma_warn == 0) { 1495 printk(KERN_WARNING "%s: DMA on non aligned address, " 1496 "switching to PIO on Ohare chipset\n", drive->name); 1497 pmif->broken_dma_warn = 1; 1498 } 1499 return 0; 1500 } 1501 while (cur_len) { 1502 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; 1503 1504 if (count++ >= MAX_DCMDS) { 1505 printk(KERN_WARNING "%s: DMA table too small\n", 1506 drive->name); 1507 return 0; 1508 } 1509 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE); 1510 st_le16(&table->req_count, tc); 1511 st_le32(&table->phy_addr, cur_addr); 1512 table->cmd_dep = 0; 1513 table->xfer_status = 0; 1514 table->res_count = 0; 1515 cur_addr += tc; 1516 cur_len -= tc; 1517 ++table; 1518 } 1519 sg = sg_next(sg); 1520 i--; 1521 } 1522 1523 /* convert the last command to an input/output last command */ 1524 if (count) { 1525 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST); 1526 /* add the stop command to the end of the list */ 1527 memset(table, 0, sizeof(struct dbdma_cmd)); 1528 st_le16(&table->command, DBDMA_STOP); 1529 mb(); 1530 writel(hwif->dmatable_dma, &dma->cmdptr); 1531 return 1; 1532 } 1533 1534 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name); 1535 1536 return 0; /* revert to PIO for this request */ 1537} 1538 1539/* 1540 * Prepare a DMA transfer. We build the DMA table, adjust the timings for 1541 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion 1542 */ 1543static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) 1544{ 1545 ide_hwif_t *hwif = drive->hwif; 1546 pmac_ide_hwif_t *pmif = 1547 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 1548 u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4); 1549 u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE); 1550 1551 if (pmac_ide_build_dmatable(drive, cmd) == 0) 1552 return 1; 1553 1554 /* Apple adds 60ns to wrDataSetup on reads */ 1555 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) { 1556 writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL), 1557 PMAC_IDE_REG(IDE_TIMING_CONFIG)); 1558 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); 1559 } 1560 1561 return 0; 1562} 1563 1564/* 1565 * Kick the DMA controller into life after the DMA command has been issued 1566 * to the drive. 1567 */ 1568static void 1569pmac_ide_dma_start(ide_drive_t *drive) 1570{ 1571 ide_hwif_t *hwif = drive->hwif; 1572 pmac_ide_hwif_t *pmif = 1573 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 1574 volatile struct dbdma_regs __iomem *dma; 1575 1576 dma = pmif->dma_regs; 1577 1578 writel((RUN << 16) | RUN, &dma->control); 1579 /* Make sure it gets to the controller right now */ 1580 (void)readl(&dma->control); 1581} 1582 1583/* 1584 * After a DMA transfer, make sure the controller is stopped 1585 */ 1586static int 1587pmac_ide_dma_end (ide_drive_t *drive) 1588{ 1589 ide_hwif_t *hwif = drive->hwif; 1590 pmac_ide_hwif_t *pmif = 1591 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 1592 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; 1593 u32 dstat; 1594 1595 dstat = readl(&dma->status); 1596 writel(((RUN|WAKE|DEAD) << 16), &dma->control); 1597 1598 /* verify good dma status. we don't check for ACTIVE beeing 0. We should... 1599 * in theory, but with ATAPI decices doing buffer underruns, that would 1600 * cause us to disable DMA, which isn't what we want 1601 */ 1602 return (dstat & (RUN|DEAD)) != RUN; 1603} 1604 1605/* 1606 * Check out that the interrupt we got was for us. We can't always know this 1607 * for sure with those Apple interfaces (well, we could on the recent ones but 1608 * that's not implemented yet), on the other hand, we don't have shared interrupts 1609 * so it's not really a problem 1610 */ 1611static int 1612pmac_ide_dma_test_irq (ide_drive_t *drive) 1613{ 1614 ide_hwif_t *hwif = drive->hwif; 1615 pmac_ide_hwif_t *pmif = 1616 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 1617 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; 1618 unsigned long status, timeout; 1619 1620 /* We have to things to deal with here: 1621 * 1622 * - The dbdma won't stop if the command was started 1623 * but completed with an error without transferring all 1624 * datas. This happens when bad blocks are met during 1625 * a multi-block transfer. 1626 * 1627 * - The dbdma fifo hasn't yet finished flushing to 1628 * to system memory when the disk interrupt occurs. 1629 * 1630 */ 1631 1632 /* If ACTIVE is cleared, the STOP command have passed and 1633 * transfer is complete. 1634 */ 1635 status = readl(&dma->status); 1636 if (!(status & ACTIVE)) 1637 return 1; 1638 1639 /* If dbdma didn't execute the STOP command yet, the 1640 * active bit is still set. We consider that we aren't 1641 * sharing interrupts (which is hopefully the case with 1642 * those controllers) and so we just try to flush the 1643 * channel for pending data in the fifo 1644 */ 1645 udelay(1); 1646 writel((FLUSH << 16) | FLUSH, &dma->control); 1647 timeout = 0; 1648 for (;;) { 1649 udelay(1); 1650 status = readl(&dma->status); 1651 if ((status & FLUSH) == 0) 1652 break; 1653 if (++timeout > 100) { 1654 printk(KERN_WARNING "ide%d, ide_dma_test_irq \ 1655 timeout flushing channel\n", hwif->index); 1656 break; 1657 } 1658 } 1659 return 1; 1660} 1661 1662static void pmac_ide_dma_host_set(ide_drive_t *drive, int on) 1663{ 1664} 1665 1666static void 1667pmac_ide_dma_lost_irq (ide_drive_t *drive) 1668{ 1669 ide_hwif_t *hwif = drive->hwif; 1670 pmac_ide_hwif_t *pmif = 1671 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 1672 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; 1673 unsigned long status = readl(&dma->status); 1674 1675 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status); 1676} 1677 1678static const struct ide_dma_ops pmac_dma_ops = { 1679 .dma_host_set = pmac_ide_dma_host_set, 1680 .dma_setup = pmac_ide_dma_setup, 1681 .dma_start = pmac_ide_dma_start, 1682 .dma_end = pmac_ide_dma_end, 1683 .dma_test_irq = pmac_ide_dma_test_irq, 1684 .dma_lost_irq = pmac_ide_dma_lost_irq, 1685}; 1686 1687/* 1688 * Allocate the data structures needed for using DMA with an interface 1689 * and fill the proper list of functions pointers 1690 */ 1691static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif, 1692 const struct ide_port_info *d) 1693{ 1694 pmac_ide_hwif_t *pmif = 1695 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 1696 struct pci_dev *dev = to_pci_dev(hwif->dev); 1697 1698 /* We won't need pci_dev if we switch to generic consistent 1699 * DMA routines ... 1700 */ 1701 if (dev == NULL || pmif->dma_regs == 0) 1702 return -ENODEV; 1703 /* 1704 * Allocate space for the DBDMA commands. 1705 * The +2 is +1 for the stop command and +1 to allow for 1706 * aligning the start address to a multiple of 16 bytes. 1707 */ 1708 pmif->dma_table_cpu = pci_alloc_consistent( 1709 dev, 1710 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd), 1711 &hwif->dmatable_dma); 1712 if (pmif->dma_table_cpu == NULL) { 1713 printk(KERN_ERR "%s: unable to allocate DMA command list\n", 1714 hwif->name); 1715 return -ENOMEM; 1716 } 1717 1718 hwif->sg_max_nents = MAX_DCMDS; 1719 1720 return 0; 1721} 1722 1723module_init(pmac_ide_probe); 1724 1725MODULE_LICENSE("GPL"); 1726