q40ide.c revision 9f36d31437922354d104a2db407f397e79e4027e 
1/*
2 *  Q40 I/O port IDE Driver
3 *
4 *     (c) Richard Zidlicky
5 *
6 *  This file is subject to the terms and conditions of the GNU General Public
7 *  License.  See the file COPYING in the main directory of this archive for
8 *  more details.
9 *
10 *
11 */
12
13#include <linux/types.h>
14#include <linux/mm.h>
15#include <linux/interrupt.h>
16#include <linux/blkdev.h>
17#include <linux/ide.h>
18
19#include <asm/ide.h>
20
21    /*
22     *  Bases of the IDE interfaces
23     */
24
25#define Q40IDE_NUM_HWIFS	2
26
27#define PCIDE_BASE1	0x1f0
28#define PCIDE_BASE2	0x170
29#define PCIDE_BASE3	0x1e8
30#define PCIDE_BASE4	0x168
31#define PCIDE_BASE5	0x1e0
32#define PCIDE_BASE6	0x160
33
34static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
35    PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4  , PCIDE_BASE5,
36    PCIDE_BASE6 */
37};
38
39static int q40ide_default_irq(unsigned long base)
40{
41           switch (base) {
42	            case 0x1f0: return 14;
43		    case 0x170: return 15;
44		    case 0x1e8: return 11;
45		    default:
46			return 0;
47	   }
48}
49
50
51/*
52 * Addresses are pretranslated for Q40 ISA access.
53 */
54static void q40_ide_setup_ports(struct ide_hw *hw, unsigned long base,
55			ide_ack_intr_t *ack_intr,
56			int irq)
57{
58	memset(hw, 0, sizeof(*hw));
59	/* BIG FAT WARNING:
60	   assumption: only DATA port is ever used in 16 bit mode */
61	hw->io_ports.data_addr = Q40_ISA_IO_W(base);
62	hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
63	hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
64	hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
65	hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
66	hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
67	hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
68	hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
69	hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
70
71	hw->irq = irq;
72	hw->ack_intr = ack_intr;
73}
74
75static void q40ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
76			      void *buf, unsigned int len)
77{
78	unsigned long data_addr = drive->hwif->io_ports.data_addr;
79
80	if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
81		__ide_mm_insw(data_addr, buf, (len + 1) / 2);
82		return;
83	}
84
85	raw_insw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
86}
87
88static void q40ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
89			       void *buf, unsigned int len)
90{
91	unsigned long data_addr = drive->hwif->io_ports.data_addr;
92
93	if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
94		__ide_mm_outsw(data_addr, buf, (len + 1) / 2);
95		return;
96	}
97
98	raw_outsw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
99}
100
101/* Q40 has a byte-swapped IDE interface */
102static const struct ide_tp_ops q40ide_tp_ops = {
103	.exec_command		= ide_exec_command,
104	.read_status		= ide_read_status,
105	.read_altstatus		= ide_read_altstatus,
106	.write_devctl		= ide_write_devctl,
107
108	.dev_select		= ide_dev_select,
109	.tf_load		= ide_tf_load,
110	.tf_read		= ide_tf_read,
111
112	.input_data		= q40ide_input_data,
113	.output_data		= q40ide_output_data,
114};
115
116static const struct ide_port_info q40ide_port_info = {
117	.tp_ops			= &q40ide_tp_ops,
118	.host_flags		= IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA,
119	.irq_flags		= IRQF_SHARED,
120	.chipset		= ide_generic,
121};
122
123/*
124 * the static array is needed to have the name reported in /proc/ioports,
125 * hwif->name unfortunately isn't available yet
126 */
127static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
128	"ide0", "ide1"
129};
130
131/*
132 *  Probe for Q40 IDE interfaces
133 */
134
135static int __init q40ide_init(void)
136{
137    int i;
138    struct ide_hw hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL };
139
140    if (!MACH_IS_Q40)
141      return -ENODEV;
142
143    printk(KERN_INFO "ide: Q40 IDE controller\n");
144
145    for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
146	const char *name = q40_ide_names[i];
147
148	if (!request_region(pcide_bases[i], 8, name)) {
149		printk("could not reserve ports %lx-%lx for %s\n",
150		       pcide_bases[i],pcide_bases[i]+8,name);
151		continue;
152	}
153	if (!request_region(pcide_bases[i]+0x206, 1, name)) {
154		printk("could not reserve port %lx for %s\n",
155		       pcide_bases[i]+0x206,name);
156		release_region(pcide_bases[i], 8);
157		continue;
158	}
159	q40_ide_setup_ports(&hw[i], pcide_bases[i], NULL,
160			q40ide_default_irq(pcide_bases[i]));
161
162	hws[i] = &hw[i];
163    }
164
165    return ide_host_add(&q40ide_port_info, hws, Q40IDE_NUM_HWIFS, NULL);
166}
167
168module_init(q40ide_init);
169
170MODULE_LICENSE("GPL");
171