scc_pata.c revision 745483f10c6cefb303007c6873e2bfce54efa8ed
1/* 2 * Support for IDE interfaces on Celleb platform 3 * 4 * (C) Copyright 2006 TOSHIBA CORPORATION 5 * 6 * This code is based on drivers/ide/pci/siimage.c: 7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> 8 * Copyright (C) 2003 Red Hat 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 23 */ 24 25#include <linux/types.h> 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/delay.h> 29#include <linux/ide.h> 30#include <linux/init.h> 31 32#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 33 34#define SCC_PATA_NAME "scc IDE" 35 36#define TDVHSEL_MASTER 0x00000001 37#define TDVHSEL_SLAVE 0x00000004 38 39#define MODE_JCUSFEN 0x00000080 40 41#define CCKCTRL_ATARESET 0x00040000 42#define CCKCTRL_BUFCNT 0x00020000 43#define CCKCTRL_CRST 0x00010000 44#define CCKCTRL_OCLKEN 0x00000100 45#define CCKCTRL_ATACLKOEN 0x00000002 46#define CCKCTRL_LCLKEN 0x00000001 47 48#define QCHCD_IOS_SS 0x00000001 49 50#define QCHSD_STPDIAG 0x00020000 51 52#define INTMASK_MSK 0xD1000012 53#define INTSTS_SERROR 0x80000000 54#define INTSTS_PRERR 0x40000000 55#define INTSTS_RERR 0x10000000 56#define INTSTS_ICERR 0x01000000 57#define INTSTS_BMSINT 0x00000010 58#define INTSTS_BMHE 0x00000008 59#define INTSTS_IOIRQS 0x00000004 60#define INTSTS_INTRQ 0x00000002 61#define INTSTS_ACTEINT 0x00000001 62 63#define ECMODE_VALUE 0x01 64 65static struct scc_ports { 66 unsigned long ctl, dma; 67 struct ide_host *host; /* for removing port from system */ 68} scc_ports[MAX_HWIFS]; 69 70/* PIO transfer mode table */ 71/* JCHST */ 72static unsigned long JCHSTtbl[2][7] = { 73 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */ 74 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */ 75}; 76 77/* JCHHT */ 78static unsigned long JCHHTtbl[2][7] = { 79 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */ 80 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */ 81}; 82 83/* JCHCT */ 84static unsigned long JCHCTtbl[2][7] = { 85 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */ 86 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */ 87}; 88 89 90/* DMA transfer mode table */ 91/* JCHDCTM/JCHDCTS */ 92static unsigned long JCHDCTxtbl[2][7] = { 93 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */ 94 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */ 95}; 96 97/* JCSTWTM/JCSTWTS */ 98static unsigned long JCSTWTxtbl[2][7] = { 99 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */ 100 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ 101}; 102 103/* JCTSS */ 104static unsigned long JCTSStbl[2][7] = { 105 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */ 106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */ 107}; 108 109/* JCENVT */ 110static unsigned long JCENVTtbl[2][7] = { 111 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */ 112 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ 113}; 114 115/* JCACTSELS/JCACTSELM */ 116static unsigned long JCACTSELtbl[2][7] = { 117 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */ 118 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */ 119}; 120 121 122static u8 scc_ide_inb(unsigned long port) 123{ 124 u32 data = in_be32((void*)port); 125 return (u8)data; 126} 127 128static void scc_exec_command(ide_hwif_t *hwif, u8 cmd) 129{ 130 out_be32((void *)hwif->io_ports.command_addr, cmd); 131 eieio(); 132 in_be32((void *)(hwif->dma_base + 0x01c)); 133 eieio(); 134} 135 136static u8 scc_read_status(ide_hwif_t *hwif) 137{ 138 return (u8)in_be32((void *)hwif->io_ports.status_addr); 139} 140 141static u8 scc_read_altstatus(ide_hwif_t *hwif) 142{ 143 return (u8)in_be32((void *)hwif->io_ports.ctl_addr); 144} 145 146static u8 scc_dma_sff_read_status(ide_hwif_t *hwif) 147{ 148 return (u8)in_be32((void *)(hwif->dma_base + 4)); 149} 150 151static void scc_write_devctl(ide_hwif_t *hwif, u8 ctl) 152{ 153 out_be32((void *)hwif->io_ports.ctl_addr, ctl); 154 eieio(); 155 in_be32((void *)(hwif->dma_base + 0x01c)); 156 eieio(); 157} 158 159static void scc_ide_insw(unsigned long port, void *addr, u32 count) 160{ 161 u16 *ptr = (u16 *)addr; 162 while (count--) { 163 *ptr++ = le16_to_cpu(in_be32((void*)port)); 164 } 165} 166 167static void scc_ide_insl(unsigned long port, void *addr, u32 count) 168{ 169 u16 *ptr = (u16 *)addr; 170 while (count--) { 171 *ptr++ = le16_to_cpu(in_be32((void*)port)); 172 *ptr++ = le16_to_cpu(in_be32((void*)port)); 173 } 174} 175 176static void scc_ide_outb(u8 addr, unsigned long port) 177{ 178 out_be32((void*)port, addr); 179} 180 181static void 182scc_ide_outsw(unsigned long port, void *addr, u32 count) 183{ 184 u16 *ptr = (u16 *)addr; 185 while (count--) { 186 out_be32((void*)port, cpu_to_le16(*ptr++)); 187 } 188} 189 190static void 191scc_ide_outsl(unsigned long port, void *addr, u32 count) 192{ 193 u16 *ptr = (u16 *)addr; 194 while (count--) { 195 out_be32((void*)port, cpu_to_le16(*ptr++)); 196 out_be32((void*)port, cpu_to_le16(*ptr++)); 197 } 198} 199 200/** 201 * scc_set_pio_mode - set host controller for PIO mode 202 * @drive: drive 203 * @pio: PIO mode number 204 * 205 * Load the timing settings for this device mode into the 206 * controller. 207 */ 208 209static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio) 210{ 211 ide_hwif_t *hwif = drive->hwif; 212 struct scc_ports *ports = ide_get_hwifdata(hwif); 213 unsigned long ctl_base = ports->ctl; 214 unsigned long cckctrl_port = ctl_base + 0xff0; 215 unsigned long piosht_port = ctl_base + 0x000; 216 unsigned long pioct_port = ctl_base + 0x004; 217 unsigned long reg; 218 int offset; 219 220 reg = in_be32((void __iomem *)cckctrl_port); 221 if (reg & CCKCTRL_ATACLKOEN) { 222 offset = 1; /* 133MHz */ 223 } else { 224 offset = 0; /* 100MHz */ 225 } 226 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio]; 227 out_be32((void __iomem *)piosht_port, reg); 228 reg = JCHCTtbl[offset][pio]; 229 out_be32((void __iomem *)pioct_port, reg); 230} 231 232/** 233 * scc_set_dma_mode - set host controller for DMA mode 234 * @drive: drive 235 * @speed: DMA mode 236 * 237 * Load the timing settings for this device mode into the 238 * controller. 239 */ 240 241static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed) 242{ 243 ide_hwif_t *hwif = drive->hwif; 244 struct scc_ports *ports = ide_get_hwifdata(hwif); 245 unsigned long ctl_base = ports->ctl; 246 unsigned long cckctrl_port = ctl_base + 0xff0; 247 unsigned long mdmact_port = ctl_base + 0x008; 248 unsigned long mcrcst_port = ctl_base + 0x00c; 249 unsigned long sdmact_port = ctl_base + 0x010; 250 unsigned long scrcst_port = ctl_base + 0x014; 251 unsigned long udenvt_port = ctl_base + 0x018; 252 unsigned long tdvhsel_port = ctl_base + 0x020; 253 int is_slave = drive->dn & 1; 254 int offset, idx; 255 unsigned long reg; 256 unsigned long jcactsel; 257 258 reg = in_be32((void __iomem *)cckctrl_port); 259 if (reg & CCKCTRL_ATACLKOEN) { 260 offset = 1; /* 133MHz */ 261 } else { 262 offset = 0; /* 100MHz */ 263 } 264 265 idx = speed - XFER_UDMA_0; 266 267 jcactsel = JCACTSELtbl[offset][idx]; 268 if (is_slave) { 269 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]); 270 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]); 271 jcactsel = jcactsel << 2; 272 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel); 273 } else { 274 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]); 275 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]); 276 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel); 277 } 278 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]; 279 out_be32((void __iomem *)udenvt_port, reg); 280} 281 282static void scc_dma_host_set(ide_drive_t *drive, int on) 283{ 284 ide_hwif_t *hwif = drive->hwif; 285 u8 unit = drive->dn & 1; 286 u8 dma_stat = scc_dma_sff_read_status(hwif); 287 288 if (on) 289 dma_stat |= (1 << (5 + unit)); 290 else 291 dma_stat &= ~(1 << (5 + unit)); 292 293 scc_ide_outb(dma_stat, hwif->dma_base + 4); 294} 295 296/** 297 * scc_dma_setup - begin a DMA phase 298 * @drive: target device 299 * @cmd: command 300 * 301 * Build an IDE DMA PRD (IDE speak for scatter gather table) 302 * and then set up the DMA transfer registers. 303 * 304 * Returns 0 on success. If a PIO fallback is required then 1 305 * is returned. 306 */ 307 308static int scc_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) 309{ 310 ide_hwif_t *hwif = drive->hwif; 311 u32 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR; 312 u8 dma_stat; 313 314 /* fall back to pio! */ 315 if (ide_build_dmatable(drive, cmd) == 0) 316 return 1; 317 318 /* PRD table */ 319 out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma); 320 321 /* specify r/w */ 322 out_be32((void __iomem *)hwif->dma_base, rw); 323 324 /* read DMA status for INTR & ERROR flags */ 325 dma_stat = scc_dma_sff_read_status(hwif); 326 327 /* clear INTR & ERROR flags */ 328 out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6); 329 330 return 0; 331} 332 333static void scc_dma_start(ide_drive_t *drive) 334{ 335 ide_hwif_t *hwif = drive->hwif; 336 u8 dma_cmd = scc_ide_inb(hwif->dma_base); 337 338 /* start DMA */ 339 scc_ide_outb(dma_cmd | 1, hwif->dma_base); 340} 341 342static int __scc_dma_end(ide_drive_t *drive) 343{ 344 ide_hwif_t *hwif = drive->hwif; 345 u8 dma_stat, dma_cmd; 346 347 /* get DMA command mode */ 348 dma_cmd = scc_ide_inb(hwif->dma_base); 349 /* stop DMA */ 350 scc_ide_outb(dma_cmd & ~1, hwif->dma_base); 351 /* get DMA status */ 352 dma_stat = scc_dma_sff_read_status(hwif); 353 /* clear the INTR & ERROR bits */ 354 scc_ide_outb(dma_stat | 6, hwif->dma_base + 4); 355 /* verify good DMA status */ 356 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; 357} 358 359/** 360 * scc_dma_end - Stop DMA 361 * @drive: IDE drive 362 * 363 * Check and clear INT Status register. 364 * Then call __scc_dma_end(). 365 */ 366 367static int scc_dma_end(ide_drive_t *drive) 368{ 369 ide_hwif_t *hwif = drive->hwif; 370 void __iomem *dma_base = (void __iomem *)hwif->dma_base; 371 unsigned long intsts_port = hwif->dma_base + 0x014; 372 u32 reg; 373 int dma_stat, data_loss = 0; 374 static int retry = 0; 375 376 /* errata A308 workaround: Step5 (check data loss) */ 377 /* We don't check non ide_disk because it is limited to UDMA4 */ 378 if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr) 379 & ATA_ERR) && 380 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) { 381 reg = in_be32((void __iomem *)intsts_port); 382 if (!(reg & INTSTS_ACTEINT)) { 383 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n", 384 drive->name); 385 data_loss = 1; 386 if (retry++) { 387 struct request *rq = hwif->rq; 388 ide_drive_t *drive; 389 int i; 390 391 /* ERROR_RESET and drive->crc_count are needed 392 * to reduce DMA transfer mode in retry process. 393 */ 394 if (rq) 395 rq->errors |= ERROR_RESET; 396 397 ide_port_for_each_dev(i, drive, hwif) 398 drive->crc_count++; 399 } 400 } 401 } 402 403 while (1) { 404 reg = in_be32((void __iomem *)intsts_port); 405 406 if (reg & INTSTS_SERROR) { 407 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME); 408 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT); 409 410 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); 411 continue; 412 } 413 414 if (reg & INTSTS_PRERR) { 415 u32 maea0, maec0; 416 unsigned long ctl_base = hwif->config_data; 417 418 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50)); 419 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54)); 420 421 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0); 422 423 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT); 424 425 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); 426 continue; 427 } 428 429 if (reg & INTSTS_RERR) { 430 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME); 431 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT); 432 433 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); 434 continue; 435 } 436 437 if (reg & INTSTS_ICERR) { 438 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); 439 440 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME); 441 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT); 442 continue; 443 } 444 445 if (reg & INTSTS_BMSINT) { 446 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME); 447 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT); 448 449 ide_do_reset(drive); 450 continue; 451 } 452 453 if (reg & INTSTS_BMHE) { 454 out_be32((void __iomem *)intsts_port, INTSTS_BMHE); 455 continue; 456 } 457 458 if (reg & INTSTS_ACTEINT) { 459 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT); 460 continue; 461 } 462 463 if (reg & INTSTS_IOIRQS) { 464 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS); 465 continue; 466 } 467 break; 468 } 469 470 dma_stat = __scc_dma_end(drive); 471 if (data_loss) 472 dma_stat |= 2; /* emulate DMA error (to retry command) */ 473 return dma_stat; 474} 475 476/* returns 1 if dma irq issued, 0 otherwise */ 477static int scc_dma_test_irq(ide_drive_t *drive) 478{ 479 ide_hwif_t *hwif = drive->hwif; 480 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014); 481 482 /* SCC errata A252,A308 workaround: Step4 */ 483 if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr) 484 & ATA_ERR) && 485 (int_stat & INTSTS_INTRQ)) 486 return 1; 487 488 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */ 489 if (int_stat & INTSTS_IOIRQS) 490 return 1; 491 492 return 0; 493} 494 495static u8 scc_udma_filter(ide_drive_t *drive) 496{ 497 ide_hwif_t *hwif = drive->hwif; 498 u8 mask = hwif->ultra_mask; 499 500 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */ 501 if ((drive->media != ide_disk) && (mask & 0xE0)) { 502 printk(KERN_INFO "%s: limit %s to UDMA4\n", 503 SCC_PATA_NAME, drive->name); 504 mask = ATA_UDMA4; 505 } 506 507 return mask; 508} 509 510/** 511 * setup_mmio_scc - map CTRL/BMID region 512 * @dev: PCI device we are configuring 513 * @name: device name 514 * 515 */ 516 517static int setup_mmio_scc (struct pci_dev *dev, const char *name) 518{ 519 void __iomem *ctl_addr; 520 void __iomem *dma_addr; 521 int i, ret; 522 523 for (i = 0; i < MAX_HWIFS; i++) { 524 if (scc_ports[i].ctl == 0) 525 break; 526 } 527 if (i >= MAX_HWIFS) 528 return -ENOMEM; 529 530 ret = pci_request_selected_regions(dev, (1 << 2) - 1, name); 531 if (ret < 0) { 532 printk(KERN_ERR "%s: can't reserve resources\n", name); 533 return ret; 534 } 535 536 ctl_addr = pci_ioremap_bar(dev, 0); 537 if (!ctl_addr) 538 goto fail_0; 539 540 dma_addr = pci_ioremap_bar(dev, 1); 541 if (!dma_addr) 542 goto fail_1; 543 544 pci_set_master(dev); 545 scc_ports[i].ctl = (unsigned long)ctl_addr; 546 scc_ports[i].dma = (unsigned long)dma_addr; 547 pci_set_drvdata(dev, (void *) &scc_ports[i]); 548 549 return 1; 550 551 fail_1: 552 iounmap(ctl_addr); 553 fail_0: 554 return -ENOMEM; 555} 556 557static int scc_ide_setup_pci_device(struct pci_dev *dev, 558 const struct ide_port_info *d) 559{ 560 struct scc_ports *ports = pci_get_drvdata(dev); 561 struct ide_host *host; 562 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; 563 int i, rc; 564 565 memset(&hw, 0, sizeof(hw)); 566 for (i = 0; i <= 8; i++) 567 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4; 568 hw.irq = dev->irq; 569 hw.dev = &dev->dev; 570 hw.chipset = ide_pci; 571 572 rc = ide_host_add(d, hws, &host); 573 if (rc) 574 return rc; 575 576 ports->host = host; 577 578 return 0; 579} 580 581/** 582 * init_setup_scc - set up an SCC PATA Controller 583 * @dev: PCI device 584 * @d: IDE port info 585 * 586 * Perform the initial set up for this device. 587 */ 588 589static int __devinit init_setup_scc(struct pci_dev *dev, 590 const struct ide_port_info *d) 591{ 592 unsigned long ctl_base; 593 unsigned long dma_base; 594 unsigned long cckctrl_port; 595 unsigned long intmask_port; 596 unsigned long mode_port; 597 unsigned long ecmode_port; 598 u32 reg = 0; 599 struct scc_ports *ports; 600 int rc; 601 602 rc = pci_enable_device(dev); 603 if (rc) 604 goto end; 605 606 rc = setup_mmio_scc(dev, d->name); 607 if (rc < 0) 608 goto end; 609 610 ports = pci_get_drvdata(dev); 611 ctl_base = ports->ctl; 612 dma_base = ports->dma; 613 cckctrl_port = ctl_base + 0xff0; 614 intmask_port = dma_base + 0x010; 615 mode_port = ctl_base + 0x024; 616 ecmode_port = ctl_base + 0xf00; 617 618 /* controller initialization */ 619 reg = 0; 620 out_be32((void*)cckctrl_port, reg); 621 reg |= CCKCTRL_ATACLKOEN; 622 out_be32((void*)cckctrl_port, reg); 623 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN; 624 out_be32((void*)cckctrl_port, reg); 625 reg |= CCKCTRL_CRST; 626 out_be32((void*)cckctrl_port, reg); 627 628 for (;;) { 629 reg = in_be32((void*)cckctrl_port); 630 if (reg & CCKCTRL_CRST) 631 break; 632 udelay(5000); 633 } 634 635 reg |= CCKCTRL_ATARESET; 636 out_be32((void*)cckctrl_port, reg); 637 638 out_be32((void*)ecmode_port, ECMODE_VALUE); 639 out_be32((void*)mode_port, MODE_JCUSFEN); 640 out_be32((void*)intmask_port, INTMASK_MSK); 641 642 rc = scc_ide_setup_pci_device(dev, d); 643 644 end: 645 return rc; 646} 647 648static void scc_tf_load(ide_drive_t *drive, struct ide_cmd *cmd) 649{ 650 struct ide_io_ports *io_ports = &drive->hwif->io_ports; 651 struct ide_taskfile *tf = &cmd->hob; 652 u8 valid = cmd->valid.out.hob; 653 u8 HIHI = (cmd->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF; 654 655 if (cmd->ftf_flags & IDE_FTFLAG_FLAGGED) 656 HIHI = 0xFF; 657 658 if (valid & IDE_VALID_FEATURE) 659 scc_ide_outb(tf->feature, io_ports->feature_addr); 660 if (valid & IDE_VALID_NSECT) 661 scc_ide_outb(tf->nsect, io_ports->nsect_addr); 662 if (valid & IDE_VALID_LBAL) 663 scc_ide_outb(tf->lbal, io_ports->lbal_addr); 664 if (valid & IDE_VALID_LBAM) 665 scc_ide_outb(tf->lbam, io_ports->lbam_addr); 666 if (valid & IDE_VALID_LBAH) 667 scc_ide_outb(tf->lbah, io_ports->lbah_addr); 668 669 tf = &cmd->tf; 670 valid = cmd->valid.out.tf; 671 672 if (valid & IDE_VALID_FEATURE) 673 scc_ide_outb(tf->feature, io_ports->feature_addr); 674 if (valid & IDE_VALID_NSECT) 675 scc_ide_outb(tf->nsect, io_ports->nsect_addr); 676 if (valid & IDE_VALID_LBAL) 677 scc_ide_outb(tf->lbal, io_ports->lbal_addr); 678 if (valid & IDE_VALID_LBAM) 679 scc_ide_outb(tf->lbam, io_ports->lbam_addr); 680 if (valid & IDE_VALID_LBAH) 681 scc_ide_outb(tf->lbah, io_ports->lbah_addr); 682 683 if (valid & IDE_VALID_DEVICE) 684 scc_ide_outb((tf->device & HIHI) | drive->select, 685 io_ports->device_addr); 686} 687 688static void scc_tf_read(ide_drive_t *drive, struct ide_cmd *cmd) 689{ 690 struct ide_io_ports *io_ports = &drive->hwif->io_ports; 691 struct ide_taskfile *tf = &cmd->tf; 692 u8 valid = cmd->valid.in.tf; 693 694 /* be sure we're looking at the low order bits */ 695 scc_ide_outb(ATA_DEVCTL_OBS, io_ports->ctl_addr); 696 697 if (valid & IDE_VALID_ERROR) 698 tf->error = scc_ide_inb(io_ports->feature_addr); 699 if (valid & IDE_VALID_NSECT) 700 tf->nsect = scc_ide_inb(io_ports->nsect_addr); 701 if (valid & IDE_VALID_LBAL) 702 tf->lbal = scc_ide_inb(io_ports->lbal_addr); 703 if (valid & IDE_VALID_LBAM) 704 tf->lbam = scc_ide_inb(io_ports->lbam_addr); 705 if (valid & IDE_VALID_LBAH) 706 tf->lbah = scc_ide_inb(io_ports->lbah_addr); 707 if (valid & IDE_VALID_DEVICE) 708 tf->device = scc_ide_inb(io_ports->device_addr); 709 710 if (cmd->tf_flags & IDE_TFLAG_LBA48) { 711 scc_ide_outb(ATA_HOB | ATA_DEVCTL_OBS, io_ports->ctl_addr); 712 713 tf = &cmd->hob; 714 valid = cmd->valid.in.hob; 715 716 if (valid & IDE_VALID_ERROR) 717 tf->error = scc_ide_inb(io_ports->feature_addr); 718 if (valid & IDE_VALID_NSECT) 719 tf->nsect = scc_ide_inb(io_ports->nsect_addr); 720 if (valid & IDE_VALID_LBAL) 721 tf->lbal = scc_ide_inb(io_ports->lbal_addr); 722 if (valid & IDE_VALID_LBAM) 723 tf->lbam = scc_ide_inb(io_ports->lbam_addr); 724 if (valid & IDE_VALID_LBAH) 725 tf->lbah = scc_ide_inb(io_ports->lbah_addr); 726 } 727} 728 729static void scc_input_data(ide_drive_t *drive, struct ide_cmd *cmd, 730 void *buf, unsigned int len) 731{ 732 unsigned long data_addr = drive->hwif->io_ports.data_addr; 733 734 len++; 735 736 if (drive->io_32bit) { 737 scc_ide_insl(data_addr, buf, len / 4); 738 739 if ((len & 3) >= 2) 740 scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1); 741 } else 742 scc_ide_insw(data_addr, buf, len / 2); 743} 744 745static void scc_output_data(ide_drive_t *drive, struct ide_cmd *cmd, 746 void *buf, unsigned int len) 747{ 748 unsigned long data_addr = drive->hwif->io_ports.data_addr; 749 750 len++; 751 752 if (drive->io_32bit) { 753 scc_ide_outsl(data_addr, buf, len / 4); 754 755 if ((len & 3) >= 2) 756 scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1); 757 } else 758 scc_ide_outsw(data_addr, buf, len / 2); 759} 760 761/** 762 * init_mmio_iops_scc - set up the iops for MMIO 763 * @hwif: interface to set up 764 * 765 */ 766 767static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif) 768{ 769 struct pci_dev *dev = to_pci_dev(hwif->dev); 770 struct scc_ports *ports = pci_get_drvdata(dev); 771 unsigned long dma_base = ports->dma; 772 773 ide_set_hwifdata(hwif, ports); 774 775 hwif->dma_base = dma_base; 776 hwif->config_data = ports->ctl; 777} 778 779/** 780 * init_iops_scc - set up iops 781 * @hwif: interface to set up 782 * 783 * Do the basic setup for the SCC hardware interface 784 * and then do the MMIO setup. 785 */ 786 787static void __devinit init_iops_scc(ide_hwif_t *hwif) 788{ 789 struct pci_dev *dev = to_pci_dev(hwif->dev); 790 791 hwif->hwif_data = NULL; 792 if (pci_get_drvdata(dev) == NULL) 793 return; 794 init_mmio_iops_scc(hwif); 795} 796 797static int __devinit scc_init_dma(ide_hwif_t *hwif, 798 const struct ide_port_info *d) 799{ 800 return ide_allocate_dma_engine(hwif); 801} 802 803static u8 scc_cable_detect(ide_hwif_t *hwif) 804{ 805 return ATA_CBL_PATA80; 806} 807 808/** 809 * init_hwif_scc - set up hwif 810 * @hwif: interface to set up 811 * 812 * We do the basic set up of the interface structure. The SCC 813 * requires several custom handlers so we override the default 814 * ide DMA handlers appropriately. 815 */ 816 817static void __devinit init_hwif_scc(ide_hwif_t *hwif) 818{ 819 /* PTERADD */ 820 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); 821 822 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) 823 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */ 824 else 825 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */ 826} 827 828static const struct ide_tp_ops scc_tp_ops = { 829 .exec_command = scc_exec_command, 830 .read_status = scc_read_status, 831 .read_altstatus = scc_read_altstatus, 832 .write_devctl = scc_write_devctl, 833 834 .dev_select = ide_dev_select, 835 .tf_load = scc_tf_load, 836 .tf_read = scc_tf_read, 837 838 .input_data = scc_input_data, 839 .output_data = scc_output_data, 840}; 841 842static const struct ide_port_ops scc_port_ops = { 843 .set_pio_mode = scc_set_pio_mode, 844 .set_dma_mode = scc_set_dma_mode, 845 .udma_filter = scc_udma_filter, 846 .cable_detect = scc_cable_detect, 847}; 848 849static const struct ide_dma_ops scc_dma_ops = { 850 .dma_host_set = scc_dma_host_set, 851 .dma_setup = scc_dma_setup, 852 .dma_start = scc_dma_start, 853 .dma_end = scc_dma_end, 854 .dma_test_irq = scc_dma_test_irq, 855 .dma_lost_irq = ide_dma_lost_irq, 856 .dma_timer_expiry = ide_dma_sff_timer_expiry, 857 .dma_sff_read_status = scc_dma_sff_read_status, 858}; 859 860static const struct ide_port_info scc_chipset __devinitdata = { 861 .name = "sccIDE", 862 .init_iops = init_iops_scc, 863 .init_dma = scc_init_dma, 864 .init_hwif = init_hwif_scc, 865 .tp_ops = &scc_tp_ops, 866 .port_ops = &scc_port_ops, 867 .dma_ops = &scc_dma_ops, 868 .host_flags = IDE_HFLAG_SINGLE, 869 .irq_flags = IRQF_SHARED, 870 .pio_mask = ATA_PIO4, 871}; 872 873/** 874 * scc_init_one - pci layer discovery entry 875 * @dev: PCI device 876 * @id: ident table entry 877 * 878 * Called by the PCI code when it finds an SCC PATA controller. 879 * We then use the IDE PCI generic helper to do most of the work. 880 */ 881 882static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id) 883{ 884 return init_setup_scc(dev, &scc_chipset); 885} 886 887/** 888 * scc_remove - pci layer remove entry 889 * @dev: PCI device 890 * 891 * Called by the PCI code when it removes an SCC PATA controller. 892 */ 893 894static void __devexit scc_remove(struct pci_dev *dev) 895{ 896 struct scc_ports *ports = pci_get_drvdata(dev); 897 struct ide_host *host = ports->host; 898 899 ide_host_remove(host); 900 901 iounmap((void*)ports->dma); 902 iounmap((void*)ports->ctl); 903 pci_release_selected_regions(dev, (1 << 2) - 1); 904 memset(ports, 0, sizeof(*ports)); 905} 906 907static const struct pci_device_id scc_pci_tbl[] = { 908 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 }, 909 { 0, }, 910}; 911MODULE_DEVICE_TABLE(pci, scc_pci_tbl); 912 913static struct pci_driver scc_pci_driver = { 914 .name = "SCC IDE", 915 .id_table = scc_pci_tbl, 916 .probe = scc_init_one, 917 .remove = __devexit_p(scc_remove), 918}; 919 920static int scc_ide_init(void) 921{ 922 return ide_pci_register_driver(&scc_pci_driver); 923} 924 925module_init(scc_ide_init); 926/* -- No exit code? 927static void scc_ide_exit(void) 928{ 929 ide_pci_unregister_driver(&scc_pci_driver); 930} 931module_exit(scc_ide_exit); 932 */ 933 934 935MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE"); 936MODULE_LICENSE("GPL"); 937