serverworks.c revision e7593af6e5c24e323217c12d011ad7e43742ca6f
1/* 2 * Copyright (C) 1998-2000 Michel Aubry 3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz 4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 5 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz 6 * Portions copyright (c) 2001 Sun Microsystems 7 * 8 * 9 * RCC/ServerWorks IDE driver for Linux 10 * 11 * OSB4: `Open South Bridge' IDE Interface (fn 1) 12 * supports UDMA mode 2 (33 MB/s) 13 * 14 * CSB5: `Champion South Bridge' IDE Interface (fn 1) 15 * all revisions support UDMA mode 4 (66 MB/s) 16 * revision A2.0 and up support UDMA mode 5 (100 MB/s) 17 * 18 * *** The CSB5 does not provide ANY register *** 19 * *** to detect 80-conductor cable presence. *** 20 * 21 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) 22 * 23 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE 24 * controller same as the CSB6. Single channel ATA100 only. 25 * 26 * Documentation: 27 * Available under NDA only. Errata info very hard to get. 28 * 29 */ 30 31#include <linux/types.h> 32#include <linux/module.h> 33#include <linux/kernel.h> 34#include <linux/pci.h> 35#include <linux/ide.h> 36#include <linux/init.h> 37 38#include <asm/io.h> 39 40#define DRV_NAME "serverworks" 41 42#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ 43#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ 44 45/* Seagate Barracuda ATA IV Family drives in UDMA mode 5 46 * can overrun their FIFOs when used with the CSB5 */ 47static const char *svwks_bad_ata100[] = { 48 "ST320011A", 49 "ST340016A", 50 "ST360021A", 51 "ST380021A", 52 NULL 53}; 54 55static int check_in_drive_lists (ide_drive_t *drive, const char **list) 56{ 57 char *m = (char *)&drive->id[ATA_ID_PROD]; 58 59 while (*list) 60 if (!strcmp(*list++, m)) 61 return 1; 62 return 0; 63} 64 65static u8 svwks_udma_filter(ide_drive_t *drive) 66{ 67 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 68 69 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { 70 return 0x1f; 71 } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) { 72 return 0x07; 73 } else { 74 u8 btr = 0, mode, mask; 75 76 pci_read_config_byte(dev, 0x5A, &btr); 77 mode = btr & 0x3; 78 79 /* If someone decides to do UDMA133 on CSB5 the same 80 issue will bite so be inclusive */ 81 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100)) 82 mode = 2; 83 84 switch(mode) { 85 case 3: mask = 0x3f; break; 86 case 2: mask = 0x1f; break; 87 case 1: mask = 0x07; break; 88 default: mask = 0x00; break; 89 } 90 91 return mask; 92 } 93} 94 95static u8 svwks_csb_check (struct pci_dev *dev) 96{ 97 switch (dev->device) { 98 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 99 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: 100 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: 101 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: 102 return 1; 103 default: 104 break; 105 } 106 return 0; 107} 108 109static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio) 110{ 111 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 112 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 }; 113 114 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 115 116 pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]); 117 118 if (svwks_csb_check(dev)) { 119 u16 csb_pio = 0; 120 121 pci_read_config_word(dev, 0x4a, &csb_pio); 122 123 csb_pio &= ~(0x0f << (4 * drive->dn)); 124 csb_pio |= (pio << (4 * drive->dn)); 125 126 pci_write_config_word(dev, 0x4a, csb_pio); 127 } 128} 129 130static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed) 131{ 132 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 }; 133 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 }; 134 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 }; 135 136 ide_hwif_t *hwif = drive->hwif; 137 struct pci_dev *dev = to_pci_dev(hwif->dev); 138 u8 unit = drive->dn & 1; 139 140 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0; 141 142 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing); 143 pci_read_config_byte(dev, 0x54, &ultra_enable); 144 145 ultra_timing &= ~(0x0F << (4*unit)); 146 ultra_enable &= ~(0x01 << drive->dn); 147 148 if (speed >= XFER_UDMA_0) { 149 dma_timing |= dma_modes[2]; 150 ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit)); 151 ultra_enable |= (0x01 << drive->dn); 152 } else if (speed >= XFER_MW_DMA_0) 153 dma_timing |= dma_modes[speed - XFER_MW_DMA_0]; 154 155 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing); 156 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing); 157 pci_write_config_byte(dev, 0x54, ultra_enable); 158} 159 160static int init_chipset_svwks(struct pci_dev *dev) 161{ 162 unsigned int reg; 163 u8 btr; 164 165 /* force Master Latency Timer value to 64 PCICLKs */ 166 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); 167 168 /* OSB4 : South Bridge and IDE */ 169 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { 170 struct pci_dev *isa_dev = 171 pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 172 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); 173 if (isa_dev) { 174 pci_read_config_dword(isa_dev, 0x64, ®); 175 reg &= ~0x00002000; /* disable 600ns interrupt mask */ 176 if(!(reg & 0x00004000)) 177 printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS " 178 "enabled.\n", pci_name(dev)); 179 reg |= 0x00004000; /* enable UDMA/33 support */ 180 pci_write_config_dword(isa_dev, 0x64, reg); 181 } 182 } 183 184 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ 185 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || 186 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || 187 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { 188 189 /* Third Channel Test */ 190 if (!(PCI_FUNC(dev->devfn) & 1)) { 191 struct pci_dev * findev = NULL; 192 u32 reg4c = 0; 193 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 194 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); 195 if (findev) { 196 pci_read_config_dword(findev, 0x4C, ®4c); 197 reg4c &= ~0x000007FF; 198 reg4c |= 0x00000040; 199 reg4c |= 0x00000020; 200 pci_write_config_dword(findev, 0x4C, reg4c); 201 pci_dev_put(findev); 202 } 203 outb_p(0x06, 0x0c00); 204 dev->irq = inb_p(0x0c01); 205 } else { 206 struct pci_dev * findev = NULL; 207 u8 reg41 = 0; 208 209 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 210 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); 211 if (findev) { 212 pci_read_config_byte(findev, 0x41, ®41); 213 reg41 &= ~0x40; 214 pci_write_config_byte(findev, 0x41, reg41); 215 pci_dev_put(findev); 216 } 217 /* 218 * This is a device pin issue on CSB6. 219 * Since there will be a future raid mode, 220 * early versions of the chipset require the 221 * interrupt pin to be set, and it is a compatibility 222 * mode issue. 223 */ 224 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) 225 dev->irq = 0; 226 } 227// pci_read_config_dword(dev, 0x40, &pioreg) 228// pci_write_config_dword(dev, 0x40, 0x99999999); 229// pci_read_config_dword(dev, 0x44, &dmareg); 230// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF); 231 /* setup the UDMA Control register 232 * 233 * 1. clear bit 6 to enable DMA 234 * 2. enable DMA modes with bits 0-1 235 * 00 : legacy 236 * 01 : udma2 237 * 10 : udma2/udma4 238 * 11 : udma2/udma4/udma5 239 */ 240 pci_read_config_byte(dev, 0x5A, &btr); 241 btr &= ~0x40; 242 if (!(PCI_FUNC(dev->devfn) & 1)) 243 btr |= 0x2; 244 else 245 btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; 246 pci_write_config_byte(dev, 0x5A, btr); 247 } 248 /* Setup HT1000 SouthBridge Controller - Single Channel Only */ 249 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { 250 pci_read_config_byte(dev, 0x5A, &btr); 251 btr &= ~0x40; 252 btr |= 0x3; 253 pci_write_config_byte(dev, 0x5A, btr); 254 } 255 256 return 0; 257} 258 259static u8 ata66_svwks_svwks(ide_hwif_t *hwif) 260{ 261 return ATA_CBL_PATA80; 262} 263 264/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits 265 * of the subsystem device ID indicate presence of an 80-pin cable. 266 * Bit 15 clear = secondary IDE channel does not have 80-pin cable. 267 * Bit 15 set = secondary IDE channel has 80-pin cable. 268 * Bit 14 clear = primary IDE channel does not have 80-pin cable. 269 * Bit 14 set = primary IDE channel has 80-pin cable. 270 */ 271static u8 ata66_svwks_dell(ide_hwif_t *hwif) 272{ 273 struct pci_dev *dev = to_pci_dev(hwif->dev); 274 275 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL && 276 dev->vendor == PCI_VENDOR_ID_SERVERWORKS && 277 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE || 278 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE)) 279 return ((1 << (hwif->channel + 14)) & 280 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; 281 return ATA_CBL_PATA40; 282} 283 284/* Sun Cobalt Alpine hardware avoids the 80-pin cable 285 * detect issue by attaching the drives directly to the board. 286 * This check follows the Dell precedent (how scary is that?!) 287 * 288 * WARNING: this only works on Alpine hardware! 289 */ 290static u8 ata66_svwks_cobalt(ide_hwif_t *hwif) 291{ 292 struct pci_dev *dev = to_pci_dev(hwif->dev); 293 294 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN && 295 dev->vendor == PCI_VENDOR_ID_SERVERWORKS && 296 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) 297 return ((1 << (hwif->channel + 14)) & 298 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; 299 return ATA_CBL_PATA40; 300} 301 302static u8 svwks_cable_detect(ide_hwif_t *hwif) 303{ 304 struct pci_dev *dev = to_pci_dev(hwif->dev); 305 306 /* Server Works */ 307 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS) 308 return ata66_svwks_svwks (hwif); 309 310 /* Dell PowerEdge */ 311 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL) 312 return ata66_svwks_dell (hwif); 313 314 /* Cobalt Alpine */ 315 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN) 316 return ata66_svwks_cobalt (hwif); 317 318 /* Per Specified Design by OEM, and ASIC Architect */ 319 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || 320 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) 321 return ATA_CBL_PATA80; 322 323 return ATA_CBL_PATA40; 324} 325 326static const struct ide_port_ops osb4_port_ops = { 327 .set_pio_mode = svwks_set_pio_mode, 328 .set_dma_mode = svwks_set_dma_mode, 329}; 330 331static const struct ide_port_ops svwks_port_ops = { 332 .set_pio_mode = svwks_set_pio_mode, 333 .set_dma_mode = svwks_set_dma_mode, 334 .udma_filter = svwks_udma_filter, 335 .cable_detect = svwks_cable_detect, 336}; 337 338static const struct ide_port_info serverworks_chipsets[] __devinitdata = { 339 { /* 0: OSB4 */ 340 .name = DRV_NAME, 341 .init_chipset = init_chipset_svwks, 342 .port_ops = &osb4_port_ops, 343 .pio_mask = ATA_PIO4, 344 .mwdma_mask = ATA_MWDMA2, 345 .udma_mask = 0x00, /* UDMA is problematic on OSB4 */ 346 }, 347 { /* 1: CSB5 */ 348 .name = DRV_NAME, 349 .init_chipset = init_chipset_svwks, 350 .port_ops = &svwks_port_ops, 351 .pio_mask = ATA_PIO4, 352 .mwdma_mask = ATA_MWDMA2, 353 .udma_mask = ATA_UDMA5, 354 }, 355 { /* 2: CSB6 */ 356 .name = DRV_NAME, 357 .init_chipset = init_chipset_svwks, 358 .port_ops = &svwks_port_ops, 359 .pio_mask = ATA_PIO4, 360 .mwdma_mask = ATA_MWDMA2, 361 .udma_mask = ATA_UDMA5, 362 }, 363 { /* 3: CSB6-2 */ 364 .name = DRV_NAME, 365 .init_chipset = init_chipset_svwks, 366 .port_ops = &svwks_port_ops, 367 .host_flags = IDE_HFLAG_SINGLE, 368 .pio_mask = ATA_PIO4, 369 .mwdma_mask = ATA_MWDMA2, 370 .udma_mask = ATA_UDMA5, 371 }, 372 { /* 4: HT1000 */ 373 .name = DRV_NAME, 374 .init_chipset = init_chipset_svwks, 375 .port_ops = &svwks_port_ops, 376 .host_flags = IDE_HFLAG_SINGLE, 377 .pio_mask = ATA_PIO4, 378 .mwdma_mask = ATA_MWDMA2, 379 .udma_mask = ATA_UDMA5, 380 } 381}; 382 383/** 384 * svwks_init_one - called when a OSB/CSB is found 385 * @dev: the svwks device 386 * @id: the matching pci id 387 * 388 * Called when the PCI registration layer (or the IDE initialization) 389 * finds a device matching our IDE device tables. 390 */ 391 392static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id) 393{ 394 struct ide_port_info d; 395 u8 idx = id->driver_data; 396 397 d = serverworks_chipsets[idx]; 398 399 if (idx == 1) 400 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX; 401 else if (idx == 2 || idx == 3) { 402 if ((PCI_FUNC(dev->devfn) & 1) == 0) { 403 if (pci_resource_start(dev, 0) != 0x01f1) 404 d.host_flags |= IDE_HFLAG_NON_BOOTABLE; 405 d.host_flags |= IDE_HFLAG_SINGLE; 406 } else 407 d.host_flags &= ~IDE_HFLAG_SINGLE; 408 } 409 410 return ide_pci_init_one(dev, &d, NULL); 411} 412 413static const struct pci_device_id svwks_pci_tbl[] = { 414 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 }, 415 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 }, 416 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 }, 417 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 }, 418 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 }, 419 { 0, }, 420}; 421MODULE_DEVICE_TABLE(pci, svwks_pci_tbl); 422 423static struct pci_driver svwks_pci_driver = { 424 .name = "Serverworks_IDE", 425 .id_table = svwks_pci_tbl, 426 .probe = svwks_init_one, 427 .remove = ide_pci_remove, 428 .suspend = ide_pci_suspend, 429 .resume = ide_pci_resume, 430}; 431 432static int __init svwks_ide_init(void) 433{ 434 return ide_pci_register_driver(&svwks_pci_driver); 435} 436 437static void __exit svwks_ide_exit(void) 438{ 439 pci_unregister_driver(&svwks_pci_driver); 440} 441 442module_init(svwks_ide_init); 443module_exit(svwks_ide_exit); 444 445MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz"); 446MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE"); 447MODULE_LICENSE("GPL"); 448