setup-pci.c revision 8acf28c090f0e5e049f56b27bdd7cf1fb40c6b98
1/* 2 * linux/drivers/ide/setup-pci.c Version 1.10 2002/08/19 3 * 4 * Copyright (c) 1998-2000 Andre Hedrick <andre@linux-ide.org> 5 * 6 * Copyright (c) 1995-1998 Mark Lord 7 * May be copied or modified under the terms of the GNU General Public License 8 */ 9 10/* 11 * This module provides support for automatic detection and 12 * configuration of all PCI IDE interfaces present in a system. 13 */ 14 15#include <linux/module.h> 16#include <linux/types.h> 17#include <linux/kernel.h> 18#include <linux/pci.h> 19#include <linux/init.h> 20#include <linux/timer.h> 21#include <linux/mm.h> 22#include <linux/interrupt.h> 23#include <linux/ide.h> 24#include <linux/dma-mapping.h> 25 26#include <asm/io.h> 27#include <asm/irq.h> 28 29 30/** 31 * ide_match_hwif - match a PCI IDE against an ide_hwif 32 * @io_base: I/O base of device 33 * @bootable: set if its bootable 34 * @name: name of device 35 * 36 * Match a PCI IDE port against an entry in ide_hwifs[], 37 * based on io_base port if possible. Return the matching hwif, 38 * or a new hwif. If we find an error (clashing, out of devices, etc) 39 * return NULL 40 * 41 * FIXME: we need to handle mmio matches here too 42 */ 43 44static ide_hwif_t *ide_match_hwif(unsigned long io_base, u8 bootable, const char *name) 45{ 46 int h; 47 ide_hwif_t *hwif; 48 49 /* 50 * Look for a hwif with matching io_base specified using 51 * parameters to ide_setup(). 52 */ 53 for (h = 0; h < MAX_HWIFS; ++h) { 54 hwif = &ide_hwifs[h]; 55 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) { 56 if (hwif->chipset == ide_forced) 57 return hwif; /* a perfect match */ 58 } 59 } 60 /* 61 * Look for a hwif with matching io_base default value. 62 * If chipset is "ide_unknown", then claim that hwif slot. 63 * Otherwise, some other chipset has already claimed it.. :( 64 */ 65 for (h = 0; h < MAX_HWIFS; ++h) { 66 hwif = &ide_hwifs[h]; 67 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) { 68 if (hwif->chipset == ide_unknown) 69 return hwif; /* match */ 70 printk(KERN_ERR "%s: port 0x%04lx already claimed by %s\n", 71 name, io_base, hwif->name); 72 return NULL; /* already claimed */ 73 } 74 } 75 /* 76 * Okay, there is no hwif matching our io_base, 77 * so we'll just claim an unassigned slot. 78 * Give preference to claiming other slots before claiming ide0/ide1, 79 * just in case there's another interface yet-to-be-scanned 80 * which uses ports 1f0/170 (the ide0/ide1 defaults). 81 * 82 * Unless there is a bootable card that does not use the standard 83 * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag. 84 */ 85 if (bootable) { 86 for (h = 0; h < MAX_HWIFS; ++h) { 87 hwif = &ide_hwifs[h]; 88 if (hwif->chipset == ide_unknown) 89 return hwif; /* pick an unused entry */ 90 } 91 } else { 92 for (h = 2; h < MAX_HWIFS; ++h) { 93 hwif = ide_hwifs + h; 94 if (hwif->chipset == ide_unknown) 95 return hwif; /* pick an unused entry */ 96 } 97 } 98 for (h = 0; h < 2 && h < MAX_HWIFS; ++h) { 99 hwif = ide_hwifs + h; 100 if (hwif->chipset == ide_unknown) 101 return hwif; /* pick an unused entry */ 102 } 103 printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", name); 104 return NULL; 105} 106 107/** 108 * ide_setup_pci_baseregs - place a PCI IDE controller native 109 * @dev: PCI device of interface to switch native 110 * @name: Name of interface 111 * 112 * We attempt to place the PCI interface into PCI native mode. If 113 * we succeed the BARs are ok and the controller is in PCI mode. 114 * Returns 0 on success or an errno code. 115 * 116 * FIXME: if we program the interface and then fail to set the BARS 117 * we don't switch it back to legacy mode. Do we actually care ?? 118 */ 119 120static int ide_setup_pci_baseregs (struct pci_dev *dev, const char *name) 121{ 122 u8 progif = 0; 123 124 /* 125 * Place both IDE interfaces into PCI "native" mode: 126 */ 127 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 128 (progif & 5) != 5) { 129 if ((progif & 0xa) != 0xa) { 130 printk(KERN_INFO "%s: device not capable of full " 131 "native PCI mode\n", name); 132 return -EOPNOTSUPP; 133 } 134 printk("%s: placing both ports into native PCI mode\n", name); 135 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 136 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 137 (progif & 5) != 5) { 138 printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted " 139 "0x%04x, got 0x%04x\n", 140 name, progif|5, progif); 141 return -EOPNOTSUPP; 142 } 143 } 144 return 0; 145} 146 147#ifdef CONFIG_BLK_DEV_IDEDMA_PCI 148/** 149 * ide_get_or_set_dma_base - setup BMIBA 150 * @d: IDE pci device data 151 * @hwif: Interface 152 * 153 * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space. 154 * Where a device has a partner that is already in DMA mode we check 155 * and enforce IDE simplex rules. 156 */ 157 158static unsigned long ide_get_or_set_dma_base(ide_pci_device_t *d, ide_hwif_t *hwif) 159{ 160 unsigned long dma_base = 0; 161 struct pci_dev *dev = hwif->pci_dev; 162 163 if (hwif->mmio) 164 return hwif->dma_base; 165 166 if (hwif->mate && hwif->mate->dma_base) { 167 dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8); 168 } else { 169 u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4; 170 171 dma_base = pci_resource_start(dev, baridx); 172 173 if (dma_base == 0) 174 printk(KERN_ERR "%s: DMA base is invalid\n", d->name); 175 } 176 177 if ((d->host_flags & IDE_HFLAG_CS5520) == 0 && dma_base) { 178 u8 simplex_stat = 0; 179 dma_base += hwif->channel ? 8 : 0; 180 181 switch(dev->device) { 182 case PCI_DEVICE_ID_AL_M5219: 183 case PCI_DEVICE_ID_AL_M5229: 184 case PCI_DEVICE_ID_AMD_VIPER_7409: 185 case PCI_DEVICE_ID_CMD_643: 186 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 187 case PCI_DEVICE_ID_REVOLUTION: 188 simplex_stat = inb(dma_base + 2); 189 outb(simplex_stat & 0x60, dma_base + 2); 190 simplex_stat = inb(dma_base + 2); 191 if (simplex_stat & 0x80) { 192 printk(KERN_INFO "%s: simplex device: " 193 "DMA forced\n", 194 d->name); 195 } 196 break; 197 default: 198 /* 199 * If the device claims "simplex" DMA, 200 * this means only one of the two interfaces 201 * can be trusted with DMA at any point in time. 202 * So we should enable DMA only on one of the 203 * two interfaces. 204 */ 205 simplex_stat = hwif->INB(dma_base + 2); 206 if (simplex_stat & 0x80) { 207 /* simplex device? */ 208/* 209 * At this point we haven't probed the drives so we can't make the 210 * appropriate decision. Really we should defer this problem 211 * until we tune the drive then try to grab DMA ownership if we want 212 * to be the DMA end. This has to be become dynamic to handle hot 213 * plug. 214 */ 215 if (hwif->mate && hwif->mate->dma_base) { 216 printk(KERN_INFO "%s: simplex device: " 217 "DMA disabled\n", 218 d->name); 219 dma_base = 0; 220 } 221 } 222 } 223 } 224 return dma_base; 225} 226#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ 227 228void ide_setup_pci_noise (struct pci_dev *dev, ide_pci_device_t *d) 229{ 230 printk(KERN_INFO "%s: IDE controller at PCI slot %s\n", 231 d->name, pci_name(dev)); 232} 233 234EXPORT_SYMBOL_GPL(ide_setup_pci_noise); 235 236 237/** 238 * ide_pci_enable - do PCI enables 239 * @dev: PCI device 240 * @d: IDE pci device data 241 * 242 * Enable the IDE PCI device. We attempt to enable the device in full 243 * but if that fails then we only need BAR4 so we will enable that. 244 * 245 * Returns zero on success or an error code 246 */ 247 248static int ide_pci_enable(struct pci_dev *dev, ide_pci_device_t *d) 249{ 250 int ret; 251 252 if (pci_enable_device(dev)) { 253 ret = pci_enable_device_bars(dev, 1 << 4); 254 if (ret < 0) { 255 printk(KERN_WARNING "%s: (ide_setup_pci_device:) " 256 "Could not enable device.\n", d->name); 257 goto out; 258 } 259 printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name); 260 } 261 262 /* 263 * assume all devices can do 32-bit dma for now. we can add a 264 * dma mask field to the ide_pci_device_t if we need it (or let 265 * lower level driver set the dma mask) 266 */ 267 ret = pci_set_dma_mask(dev, DMA_32BIT_MASK); 268 if (ret < 0) { 269 printk(KERN_ERR "%s: can't set dma mask\n", d->name); 270 goto out; 271 } 272 273 /* FIXME: Temporary - until we put in the hotplug interface logic 274 Check that the bits we want are not in use by someone else. */ 275 ret = pci_request_region(dev, 4, "ide_tmp"); 276 if (ret < 0) 277 goto out; 278 279 pci_release_region(dev, 4); 280out: 281 return ret; 282} 283 284/** 285 * ide_pci_configure - configure an unconfigured device 286 * @dev: PCI device 287 * @d: IDE pci device data 288 * 289 * Enable and configure the PCI device we have been passed. 290 * Returns zero on success or an error code. 291 */ 292 293static int ide_pci_configure(struct pci_dev *dev, ide_pci_device_t *d) 294{ 295 u16 pcicmd = 0; 296 /* 297 * PnP BIOS was *supposed* to have setup this device, but we 298 * can do it ourselves, so long as the BIOS has assigned an IRQ 299 * (or possibly the device is using a "legacy header" for IRQs). 300 * Maybe the user deliberately *disabled* the device, 301 * but we'll eventually ignore it again if no drives respond. 302 */ 303 if (ide_setup_pci_baseregs(dev, d->name) || pci_write_config_word(dev, PCI_COMMAND, pcicmd|PCI_COMMAND_IO)) 304 { 305 printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name); 306 return -ENODEV; 307 } 308 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { 309 printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); 310 return -EIO; 311 } 312 if (!(pcicmd & PCI_COMMAND_IO)) { 313 printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name); 314 return -ENXIO; 315 } 316 return 0; 317} 318 319/** 320 * ide_pci_check_iomem - check a register is I/O 321 * @dev: pci device 322 * @d: ide_pci_device 323 * @bar: bar number 324 * 325 * Checks if a BAR is configured and points to MMIO space. If so 326 * print an error and return an error code. Otherwise return 0 327 */ 328 329static int ide_pci_check_iomem(struct pci_dev *dev, ide_pci_device_t *d, int bar) 330{ 331 ulong flags = pci_resource_flags(dev, bar); 332 333 /* Unconfigured ? */ 334 if (!flags || pci_resource_len(dev, bar) == 0) 335 return 0; 336 337 /* I/O space */ 338 if(flags & PCI_BASE_ADDRESS_IO_MASK) 339 return 0; 340 341 /* Bad */ 342 printk(KERN_ERR "%s: IO baseregs (BIOS) are reported " 343 "as MEM, report to " 344 "<andre@linux-ide.org>.\n", d->name); 345 return -EINVAL; 346} 347 348/** 349 * ide_hwif_configure - configure an IDE interface 350 * @dev: PCI device holding interface 351 * @d: IDE pci data 352 * @mate: Paired interface if any 353 * 354 * Perform the initial set up for the hardware interface structure. This 355 * is done per interface port rather than per PCI device. There may be 356 * more than one port per device. 357 * 358 * Returns the new hardware interface structure, or NULL on a failure 359 */ 360 361static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *mate, int port, int irq) 362{ 363 unsigned long ctl = 0, base = 0; 364 ide_hwif_t *hwif; 365 u8 bootable = (d->host_flags & IDE_HFLAG_BOOTABLE) ? 1 : 0; 366 367 if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) { 368 /* Possibly we should fail if these checks report true */ 369 ide_pci_check_iomem(dev, d, 2*port); 370 ide_pci_check_iomem(dev, d, 2*port+1); 371 372 ctl = pci_resource_start(dev, 2*port+1); 373 base = pci_resource_start(dev, 2*port); 374 if ((ctl && !base) || (base && !ctl)) { 375 printk(KERN_ERR "%s: inconsistent baseregs (BIOS) " 376 "for port %d, skipping\n", d->name, port); 377 return NULL; 378 } 379 } 380 if (!ctl) 381 { 382 /* Use default values */ 383 ctl = port ? 0x374 : 0x3f4; 384 base = port ? 0x170 : 0x1f0; 385 } 386 if ((hwif = ide_match_hwif(base, bootable, d->name)) == NULL) 387 return NULL; /* no room in ide_hwifs[] */ 388 if (hwif->io_ports[IDE_DATA_OFFSET] != base || 389 hwif->io_ports[IDE_CONTROL_OFFSET] != (ctl | 2)) { 390 memset(&hwif->hw, 0, sizeof(hwif->hw)); 391#ifndef IDE_ARCH_OBSOLETE_INIT 392 ide_std_init_ports(&hwif->hw, base, (ctl | 2)); 393 hwif->hw.io_ports[IDE_IRQ_OFFSET] = 0; 394#else 395 ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL); 396#endif 397 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports)); 398 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET]; 399 } 400 hwif->chipset = d->chipset ? d->chipset : ide_pci; 401 hwif->pci_dev = dev; 402 hwif->cds = (struct ide_pci_device_s *) d; 403 hwif->channel = port; 404 405 if (!hwif->irq) 406 hwif->irq = irq; 407 if (mate) { 408 hwif->mate = mate; 409 mate->mate = hwif; 410 } 411 return hwif; 412} 413 414/** 415 * ide_hwif_setup_dma - configure DMA interface 416 * @dev: PCI device 417 * @d: IDE pci data 418 * @hwif: Hardware interface we are configuring 419 * 420 * Set up the DMA base for the interface. Enable the master bits as 421 * necessary and attempt to bring the device DMA into a ready to use 422 * state 423 */ 424 425#ifndef CONFIG_BLK_DEV_IDEDMA_PCI 426static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif) 427{ 428} 429#else 430static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif) 431{ 432 u16 pcicmd; 433 434 pci_read_config_word(dev, PCI_COMMAND, &pcicmd); 435 436 if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 || 437 ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && 438 (dev->class & 0x80))) { 439 unsigned long dma_base = ide_get_or_set_dma_base(d, hwif); 440 if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) { 441 /* 442 * Set up BM-DMA capability 443 * (PnP BIOS should have done this) 444 */ 445 pci_set_master(dev); 446 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) { 447 printk(KERN_ERR "%s: %s error updating PCICMD\n", 448 hwif->name, d->name); 449 dma_base = 0; 450 } 451 } 452 if (dma_base) { 453 if (d->init_dma) { 454 d->init_dma(hwif, dma_base); 455 } else { 456 ide_setup_dma(hwif, dma_base, 8); 457 } 458 } else { 459 printk(KERN_INFO "%s: %s Bus-Master DMA disabled " 460 "(BIOS)\n", hwif->name, d->name); 461 } 462 } 463} 464#endif /* CONFIG_BLK_DEV_IDEDMA_PCI*/ 465 466/** 467 * ide_setup_pci_controller - set up IDE PCI 468 * @dev: PCI device 469 * @d: IDE PCI data 470 * @noisy: verbose flag 471 * @config: returned as 1 if we configured the hardware 472 * 473 * Set up the PCI and controller side of the IDE interface. This brings 474 * up the PCI side of the device, checks that the device is enabled 475 * and enables it if need be 476 */ 477 478static int ide_setup_pci_controller(struct pci_dev *dev, ide_pci_device_t *d, int noisy, int *config) 479{ 480 int ret; 481 u16 pcicmd; 482 483 if (noisy) 484 ide_setup_pci_noise(dev, d); 485 486 ret = ide_pci_enable(dev, d); 487 if (ret < 0) 488 goto out; 489 490 ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd); 491 if (ret < 0) { 492 printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); 493 goto out; 494 } 495 if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ 496 ret = ide_pci_configure(dev, d); 497 if (ret < 0) 498 goto out; 499 *config = 1; 500 printk(KERN_INFO "%s: device enabled (Linux)\n", d->name); 501 } 502 503 if (noisy) 504 printk(KERN_INFO "%s: chipset revision %d\n", 505 d->name, dev->revision); 506out: 507 return ret; 508} 509 510/** 511 * ide_pci_setup_ports - configure ports/devices on PCI IDE 512 * @dev: PCI device 513 * @d: IDE pci device info 514 * @pciirq: IRQ line 515 * @index: ata index to update 516 * 517 * Scan the interfaces attached to this device and do any 518 * necessary per port setup. Attach the devices and ask the 519 * generic DMA layer to do its work for us. 520 * 521 * Normally called automaticall from do_ide_pci_setup_device, 522 * but is also used directly as a helper function by some controllers 523 * where the chipset setup is not the default PCI IDE one. 524 */ 525 526void ide_pci_setup_ports(struct pci_dev *dev, ide_pci_device_t *d, int pciirq, ata_index_t *index) 527{ 528 int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port; 529 ide_hwif_t *hwif, *mate = NULL; 530 u8 tmp; 531 532 index->all = 0xf0f0; 533 534 /* 535 * Set up the IDE ports 536 */ 537 538 for (port = 0; port < channels; ++port) { 539 ide_pci_enablebit_t *e = &(d->enablebits[port]); 540 541 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || 542 (tmp & e->mask) != e->val)) { 543 printk(KERN_INFO "%s: IDE port disabled\n", d->name); 544 continue; /* port not enabled */ 545 } 546 547 if ((hwif = ide_hwif_configure(dev, d, mate, port, pciirq)) == NULL) 548 continue; 549 550 /* setup proper ancestral information */ 551 hwif->gendev.parent = &dev->dev; 552 553 if (hwif->channel) { 554 index->b.high = hwif->index; 555 } else { 556 index->b.low = hwif->index; 557 } 558 559 560 if (d->init_iops) 561 d->init_iops(hwif); 562 563 if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) 564 ide_hwif_setup_dma(dev, d, hwif); 565 566 if ((!hwif->irq && (d->host_flags & IDE_HFLAG_LEGACY_IRQS)) || 567 (d->host_flags & IDE_HFLAG_FORCE_LEGACY_IRQS)) 568 hwif->irq = port ? 15 : 14; 569 570 hwif->host_flags = d->host_flags; 571 hwif->pio_mask = d->pio_mask; 572 573 if ((d->host_flags & IDE_HFLAG_SERIALIZE) && hwif->mate) 574 hwif->mate->serialized = hwif->serialized = 1; 575 576 if (hwif->dma_base) { 577 hwif->swdma_mask = d->swdma_mask; 578 hwif->mwdma_mask = d->mwdma_mask; 579 hwif->ultra_mask = d->udma_mask; 580 } 581 582 hwif->drives[0].autotune = 1; 583 hwif->drives[1].autotune = 1; 584 585 if (d->init_hwif) 586 /* Call chipset-specific routine 587 * for each enabled hwif 588 */ 589 d->init_hwif(hwif); 590 591 mate = hwif; 592 } 593} 594 595EXPORT_SYMBOL_GPL(ide_pci_setup_ports); 596 597/* 598 * ide_setup_pci_device() looks at the primary/secondary interfaces 599 * on a PCI IDE device and, if they are enabled, prepares the IDE driver 600 * for use with them. This generic code works for most PCI chipsets. 601 * 602 * One thing that is not standardized is the location of the 603 * primary/secondary interface "enable/disable" bits. For chipsets that 604 * we "know" about, this information is in the ide_pci_device_t struct; 605 * for all other chipsets, we just assume both interfaces are enabled. 606 */ 607static int do_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d, 608 ata_index_t *index, u8 noisy) 609{ 610 static ata_index_t ata_index = { .b = { .low = 0xff, .high = 0xff } }; 611 int tried_config = 0; 612 int pciirq, ret; 613 614 ret = ide_setup_pci_controller(dev, d, noisy, &tried_config); 615 if (ret < 0) 616 goto out; 617 618 /* 619 * Can we trust the reported IRQ? 620 */ 621 pciirq = dev->irq; 622 623 /* Is it an "IDE storage" device in non-PCI mode? */ 624 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) { 625 if (noisy) 626 printk(KERN_INFO "%s: not 100%% native mode: " 627 "will probe irqs later\n", d->name); 628 /* 629 * This allows offboard ide-pci cards the enable a BIOS, 630 * verify interrupt settings of split-mirror pci-config 631 * space, place chipset into init-mode, and/or preserve 632 * an interrupt if the card is not native ide support. 633 */ 634 ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0; 635 if (ret < 0) 636 goto out; 637 pciirq = ret; 638 } else if (tried_config) { 639 if (noisy) 640 printk(KERN_INFO "%s: will probe irqs later\n", d->name); 641 pciirq = 0; 642 } else if (!pciirq) { 643 if (noisy) 644 printk(KERN_WARNING "%s: bad irq (%d): will probe later\n", 645 d->name, pciirq); 646 pciirq = 0; 647 } else { 648 if (d->init_chipset) { 649 ret = d->init_chipset(dev, d->name); 650 if (ret < 0) 651 goto out; 652 } 653 if (noisy) 654 printk(KERN_INFO "%s: 100%% native mode on irq %d\n", 655 d->name, pciirq); 656 } 657 658 /* FIXME: silent failure can happen */ 659 660 *index = ata_index; 661 ide_pci_setup_ports(dev, d, pciirq, index); 662out: 663 return ret; 664} 665 666int ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d) 667{ 668 ide_hwif_t *hwif = NULL, *mate = NULL; 669 ata_index_t index_list; 670 int ret; 671 672 ret = do_ide_setup_pci_device(dev, d, &index_list, 1); 673 if (ret < 0) 674 goto out; 675 676 if ((index_list.b.low & 0xf0) != 0xf0) 677 hwif = &ide_hwifs[index_list.b.low]; 678 if ((index_list.b.high & 0xf0) != 0xf0) 679 mate = &ide_hwifs[index_list.b.high]; 680 681 if (hwif) 682 probe_hwif_init_with_fixup(hwif, d->fixup); 683 if (mate) 684 probe_hwif_init_with_fixup(mate, d->fixup); 685 686 if (hwif) 687 ide_proc_register_port(hwif); 688 if (mate) 689 ide_proc_register_port(mate); 690out: 691 return ret; 692} 693 694EXPORT_SYMBOL_GPL(ide_setup_pci_device); 695 696int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2, 697 ide_pci_device_t *d) 698{ 699 struct pci_dev *pdev[] = { dev1, dev2 }; 700 ata_index_t index_list[2]; 701 int ret, i; 702 703 for (i = 0; i < 2; i++) { 704 ret = do_ide_setup_pci_device(pdev[i], d, index_list + i, !i); 705 /* 706 * FIXME: Mom, mom, they stole me the helper function to undo 707 * do_ide_setup_pci_device() on the first device! 708 */ 709 if (ret < 0) 710 goto out; 711 } 712 713 for (i = 0; i < 2; i++) { 714 u8 idx[2] = { index_list[i].b.low, index_list[i].b.high }; 715 int j; 716 717 for (j = 0; j < 2; j++) { 718 if ((idx[j] & 0xf0) != 0xf0) 719 probe_hwif_init(ide_hwifs + idx[j]); 720 } 721 } 722 723 for (i = 0; i < 2; i++) { 724 u8 idx[2] = { index_list[i].b.low, index_list[i].b.high }; 725 int j; 726 727 for (j = 0; j < 2; j++) { 728 if ((idx[j] & 0xf0) != 0xf0) 729 ide_proc_register_port(ide_hwifs + idx[j]); 730 } 731 } 732out: 733 return ret; 734} 735 736EXPORT_SYMBOL_GPL(ide_setup_pci_devices); 737 738#ifdef CONFIG_IDEPCI_PCIBUS_ORDER 739/* 740 * Module interfaces 741 */ 742 743static int pre_init = 1; /* Before first ordered IDE scan */ 744static LIST_HEAD(ide_pci_drivers); 745 746/* 747 * __ide_pci_register_driver - attach IDE driver 748 * @driver: pci driver 749 * @module: owner module of the driver 750 * 751 * Registers a driver with the IDE layer. The IDE layer arranges that 752 * boot time setup is done in the expected device order and then 753 * hands the controllers off to the core PCI code to do the rest of 754 * the work. 755 * 756 * The driver_data of the driver table must point to an ide_pci_device_t 757 * describing the interface. 758 * 759 * Returns are the same as for pci_register_driver 760 */ 761 762int __ide_pci_register_driver(struct pci_driver *driver, struct module *module, 763 const char *mod_name) 764{ 765 if(!pre_init) 766 return __pci_register_driver(driver, module, mod_name); 767 driver->driver.owner = module; 768 list_add_tail(&driver->node, &ide_pci_drivers); 769 return 0; 770} 771 772EXPORT_SYMBOL_GPL(__ide_pci_register_driver); 773 774/** 775 * ide_scan_pcidev - find an IDE driver for a device 776 * @dev: PCI device to check 777 * 778 * Look for an IDE driver to handle the device we are considering. 779 * This is only used during boot up to get the ordering correct. After 780 * boot up the pci layer takes over the job. 781 */ 782 783static int __init ide_scan_pcidev(struct pci_dev *dev) 784{ 785 struct list_head *l; 786 struct pci_driver *d; 787 788 list_for_each(l, &ide_pci_drivers) { 789 d = list_entry(l, struct pci_driver, node); 790 if (d->id_table) { 791 const struct pci_device_id *id = pci_match_id(d->id_table, 792 dev); 793 if (id != NULL && d->probe(dev, id) >= 0) { 794 dev->driver = d; 795 pci_dev_get(dev); 796 return 1; 797 } 798 } 799 } 800 return 0; 801} 802 803/** 804 * ide_scan_pcibus - perform the initial IDE driver scan 805 * @scan_direction: set for reverse order scanning 806 * 807 * Perform the initial bus rather than driver ordered scan of the 808 * PCI drivers. After this all IDE pci handling becomes standard 809 * module ordering not traditionally ordered. 810 */ 811 812void __init ide_scan_pcibus (int scan_direction) 813{ 814 struct pci_dev *dev = NULL; 815 struct pci_driver *d; 816 struct list_head *l, *n; 817 818 pre_init = 0; 819 if (!scan_direction) 820 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) 821 ide_scan_pcidev(dev); 822 else 823 while ((dev = pci_get_device_reverse(PCI_ANY_ID, PCI_ANY_ID, dev)) 824 != NULL) 825 ide_scan_pcidev(dev); 826 827 /* 828 * Hand the drivers over to the PCI layer now we 829 * are post init. 830 */ 831 832 list_for_each_safe(l, n, &ide_pci_drivers) { 833 list_del(l); 834 d = list_entry(l, struct pci_driver, node); 835 if (__pci_register_driver(d, d->driver.owner, d->driver.mod_name)) 836 printk(KERN_ERR "%s: failed to register driver for %s\n", 837 __FUNCTION__, d->driver.mod_name); 838 } 839} 840#endif 841