siimage.c revision c9ef59ff01b6bd1c7360a64fcc8556a1193c2ed0
1/* 2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> 3 * Copyright (C) 2003 Red Hat 4 * Copyright (C) 2007-2008 MontaVista Software, Inc. 5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz 6 * 7 * May be copied or modified under the terms of the GNU General Public License 8 * 9 * Documentation for CMD680: 10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 11 * 12 * Documentation for SiI 3112: 13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 14 * 15 * Errata and other documentation only available under NDA. 16 * 17 * 18 * FAQ Items: 19 * If you are using Marvell SATA-IDE adapters with Maxtor drives 20 * ensure the system is set up for ATA100/UDMA5, not UDMA6. 21 * 22 * If you are using WD drives with SATA bridges you must set the 23 * drive to "Single". "Master" will hang. 24 * 25 * If you have strange problems with nVidia chipset systems please 26 * see the SI support documentation and update your system BIOS 27 * if necessary 28 * 29 * The Dell DRAC4 has some interesting features including effectively hot 30 * unplugging/replugging the virtual CD interface when the DRAC is reset. 31 * This often causes drivers/ide/siimage to panic but is ok with the rather 32 * smarter code in libata. 33 * 34 * TODO: 35 * - VDMA support 36 */ 37 38#include <linux/types.h> 39#include <linux/module.h> 40#include <linux/pci.h> 41#include <linux/ide.h> 42#include <linux/init.h> 43#include <linux/io.h> 44 45#define DRV_NAME "siimage" 46 47/** 48 * pdev_is_sata - check if device is SATA 49 * @pdev: PCI device to check 50 * 51 * Returns true if this is a SATA controller 52 */ 53 54static int pdev_is_sata(struct pci_dev *pdev) 55{ 56#ifdef CONFIG_BLK_DEV_IDE_SATA 57 switch (pdev->device) { 58 case PCI_DEVICE_ID_SII_3112: 59 case PCI_DEVICE_ID_SII_1210SA: 60 return 1; 61 case PCI_DEVICE_ID_SII_680: 62 return 0; 63 } 64 BUG(); 65#endif 66 return 0; 67} 68 69/** 70 * is_sata - check if hwif is SATA 71 * @hwif: interface to check 72 * 73 * Returns true if this is a SATA controller 74 */ 75 76static inline int is_sata(ide_hwif_t *hwif) 77{ 78 return pdev_is_sata(to_pci_dev(hwif->dev)); 79} 80 81/** 82 * siimage_selreg - return register base 83 * @hwif: interface 84 * @r: config offset 85 * 86 * Turn a config register offset into the right address in either 87 * PCI space or MMIO space to access the control register in question 88 * Thankfully this is a configuration operation, so isn't performance 89 * critical. 90 */ 91 92static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) 93{ 94 unsigned long base = (unsigned long)hwif->hwif_data; 95 96 base += 0xA0 + r; 97 if (hwif->host_flags & IDE_HFLAG_MMIO) 98 base += hwif->channel << 6; 99 else 100 base += hwif->channel << 4; 101 return base; 102} 103 104/** 105 * siimage_seldev - return register base 106 * @hwif: interface 107 * @r: config offset 108 * 109 * Turn a config register offset into the right address in either 110 * PCI space or MMIO space to access the control register in question 111 * including accounting for the unit shift. 112 */ 113 114static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) 115{ 116 ide_hwif_t *hwif = drive->hwif; 117 unsigned long base = (unsigned long)hwif->hwif_data; 118 u8 unit = drive->dn & 1; 119 120 base += 0xA0 + r; 121 if (hwif->host_flags & IDE_HFLAG_MMIO) 122 base += hwif->channel << 6; 123 else 124 base += hwif->channel << 4; 125 base |= unit << unit; 126 return base; 127} 128 129static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr) 130{ 131 struct ide_host *host = pci_get_drvdata(dev); 132 u8 tmp = 0; 133 134 if (host->host_priv) 135 tmp = readb((void __iomem *)addr); 136 else 137 pci_read_config_byte(dev, addr, &tmp); 138 139 return tmp; 140} 141 142static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr) 143{ 144 struct ide_host *host = pci_get_drvdata(dev); 145 u16 tmp = 0; 146 147 if (host->host_priv) 148 tmp = readw((void __iomem *)addr); 149 else 150 pci_read_config_word(dev, addr, &tmp); 151 152 return tmp; 153} 154 155static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr) 156{ 157 struct ide_host *host = pci_get_drvdata(dev); 158 159 if (host->host_priv) 160 writeb(val, (void __iomem *)addr); 161 else 162 pci_write_config_byte(dev, addr, val); 163} 164 165static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr) 166{ 167 struct ide_host *host = pci_get_drvdata(dev); 168 169 if (host->host_priv) 170 writew(val, (void __iomem *)addr); 171 else 172 pci_write_config_word(dev, addr, val); 173} 174 175static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr) 176{ 177 struct ide_host *host = pci_get_drvdata(dev); 178 179 if (host->host_priv) 180 writel(val, (void __iomem *)addr); 181 else 182 pci_write_config_dword(dev, addr, val); 183} 184 185/** 186 * sil_udma_filter - compute UDMA mask 187 * @drive: IDE device 188 * 189 * Compute the available UDMA speeds for the device on the interface. 190 * 191 * For the CMD680 this depends on the clocking mode (scsc), for the 192 * SI3112 SATA controller life is a bit simpler. 193 */ 194 195static u8 sil_pata_udma_filter(ide_drive_t *drive) 196{ 197 ide_hwif_t *hwif = drive->hwif; 198 struct pci_dev *dev = to_pci_dev(hwif->dev); 199 unsigned long base = (unsigned long)hwif->hwif_data; 200 u8 scsc, mask = 0; 201 202 base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A; 203 204 scsc = sil_ioread8(dev, base); 205 206 switch (scsc & 0x30) { 207 case 0x10: /* 133 */ 208 mask = ATA_UDMA6; 209 break; 210 case 0x20: /* 2xPCI */ 211 mask = ATA_UDMA6; 212 break; 213 case 0x00: /* 100 */ 214 mask = ATA_UDMA5; 215 break; 216 default: /* Disabled ? */ 217 BUG(); 218 } 219 220 return mask; 221} 222 223static u8 sil_sata_udma_filter(ide_drive_t *drive) 224{ 225 char *m = (char *)&drive->id[ATA_ID_PROD]; 226 227 return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6; 228} 229 230/** 231 * sil_set_pio_mode - set host controller for PIO mode 232 * @drive: drive 233 * @pio: PIO mode number 234 * 235 * Load the timing settings for this device mode into the 236 * controller. 237 */ 238 239static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) 240{ 241 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; 242 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 243 244 ide_hwif_t *hwif = drive->hwif; 245 struct pci_dev *dev = to_pci_dev(hwif->dev); 246 ide_drive_t *pair = ide_get_pair_dev(drive); 247 u32 speedt = 0; 248 u16 speedp = 0; 249 unsigned long addr = siimage_seldev(drive, 0x04); 250 unsigned long tfaddr = siimage_selreg(hwif, 0x02); 251 unsigned long base = (unsigned long)hwif->hwif_data; 252 u8 tf_pio = pio; 253 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 254 u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) 255 : (mmio ? 0xB4 : 0x80); 256 u8 mode = 0; 257 u8 unit = drive->dn & 1; 258 259 /* trim *taskfile* PIO to the slowest of the master/slave */ 260 if (pair) { 261 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); 262 263 if (pair_pio < tf_pio) 264 tf_pio = pair_pio; 265 } 266 267 /* cheat for now and use the docs */ 268 speedp = data_speed[pio]; 269 speedt = tf_speed[tf_pio]; 270 271 sil_iowrite16(dev, speedp, addr); 272 sil_iowrite16(dev, speedt, tfaddr); 273 274 /* now set up IORDY */ 275 speedp = sil_ioread16(dev, tfaddr - 2); 276 speedp &= ~0x200; 277 278 mode = sil_ioread8(dev, base + addr_mask); 279 mode &= ~(unit ? 0x30 : 0x03); 280 281 if (ide_pio_need_iordy(drive, pio)) { 282 speedp |= 0x200; 283 mode |= unit ? 0x10 : 0x01; 284 } 285 286 sil_iowrite16(dev, speedp, tfaddr - 2); 287 sil_iowrite8(dev, mode, base + addr_mask); 288} 289 290/** 291 * sil_set_dma_mode - set host controller for DMA mode 292 * @drive: drive 293 * @speed: DMA mode 294 * 295 * Tune the SiI chipset for the desired DMA mode. 296 */ 297 298static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) 299{ 300 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; 301 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; 302 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; 303 304 ide_hwif_t *hwif = drive->hwif; 305 struct pci_dev *dev = to_pci_dev(hwif->dev); 306 unsigned long base = (unsigned long)hwif->hwif_data; 307 u16 ultra = 0, multi = 0; 308 u8 mode = 0, unit = drive->dn & 1; 309 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; 310 u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) 311 : (mmio ? 0xB4 : 0x80); 312 unsigned long ma = siimage_seldev(drive, 0x08); 313 unsigned long ua = siimage_seldev(drive, 0x0C); 314 315 scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A)); 316 mode = sil_ioread8 (dev, base + addr_mask); 317 multi = sil_ioread16(dev, ma); 318 ultra = sil_ioread16(dev, ua); 319 320 mode &= ~(unit ? 0x30 : 0x03); 321 ultra &= ~0x3F; 322 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; 323 324 scsc = is_sata(hwif) ? 1 : scsc; 325 326 if (speed >= XFER_UDMA_0) { 327 multi = dma[2]; 328 ultra |= scsc ? ultra6[speed - XFER_UDMA_0] : 329 ultra5[speed - XFER_UDMA_0]; 330 mode |= unit ? 0x30 : 0x03; 331 } else { 332 multi = dma[speed - XFER_MW_DMA_0]; 333 mode |= unit ? 0x20 : 0x02; 334 } 335 336 sil_iowrite8 (dev, mode, base + addr_mask); 337 sil_iowrite16(dev, multi, ma); 338 sil_iowrite16(dev, ultra, ua); 339} 340 341/* returns 1 if dma irq issued, 0 otherwise */ 342static int siimage_io_dma_test_irq(ide_drive_t *drive) 343{ 344 ide_hwif_t *hwif = drive->hwif; 345 struct pci_dev *dev = to_pci_dev(hwif->dev); 346 u8 dma_altstat = 0; 347 unsigned long addr = siimage_selreg(hwif, 1); 348 349 /* return 1 if INTR asserted */ 350 if (inb(hwif->dma_base + ATA_DMA_STATUS) & 4) 351 return 1; 352 353 /* return 1 if Device INTR asserted */ 354 pci_read_config_byte(dev, addr, &dma_altstat); 355 if (dma_altstat & 8) 356 return 0; /* return 1; */ 357 358 return 0; 359} 360 361/** 362 * siimage_mmio_dma_test_irq - check we caused an IRQ 363 * @drive: drive we are testing 364 * 365 * Check if we caused an IDE DMA interrupt. We may also have caused 366 * SATA status interrupts, if so we clean them up and continue. 367 */ 368 369static int siimage_mmio_dma_test_irq(ide_drive_t *drive) 370{ 371 ide_hwif_t *hwif = drive->hwif; 372 unsigned long addr = siimage_selreg(hwif, 0x1); 373 void __iomem *sata_error_addr 374 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET]; 375 376 if (sata_error_addr) { 377 unsigned long base = (unsigned long)hwif->hwif_data; 378 u32 ext_stat = readl((void __iomem *)(base + 0x10)); 379 u8 watchdog = 0; 380 381 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { 382 u32 sata_error = readl(sata_error_addr); 383 384 writel(sata_error, sata_error_addr); 385 watchdog = (sata_error & 0x00680000) ? 1 : 0; 386 printk(KERN_WARNING "%s: sata_error = 0x%08x, " 387 "watchdog = %d, %s\n", 388 drive->name, sata_error, watchdog, __func__); 389 } else 390 watchdog = (ext_stat & 0x8000) ? 1 : 0; 391 392 ext_stat >>= 16; 393 if (!(ext_stat & 0x0404) && !watchdog) 394 return 0; 395 } 396 397 /* return 1 if INTR asserted */ 398 if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4) 399 return 1; 400 401 /* return 1 if Device INTR asserted */ 402 if (readb((void __iomem *)addr) & 8) 403 return 0; /* return 1; */ 404 405 return 0; 406} 407 408static int siimage_dma_test_irq(ide_drive_t *drive) 409{ 410 if (drive->hwif->host_flags & IDE_HFLAG_MMIO) 411 return siimage_mmio_dma_test_irq(drive); 412 else 413 return siimage_io_dma_test_irq(drive); 414} 415 416/** 417 * sil_sata_reset_poll - wait for SATA reset 418 * @drive: drive we are resetting 419 * 420 * Poll the SATA phy and see whether it has come back from the dead 421 * yet. 422 */ 423 424static int sil_sata_reset_poll(ide_drive_t *drive) 425{ 426 ide_hwif_t *hwif = drive->hwif; 427 void __iomem *sata_status_addr 428 = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET]; 429 430 if (sata_status_addr) { 431 /* SATA Status is available only when in MMIO mode */ 432 u32 sata_stat = readl(sata_status_addr); 433 434 if ((sata_stat & 0x03) != 0x03) { 435 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", 436 hwif->name, sata_stat); 437 return -ENXIO; 438 } 439 } 440 441 return 0; 442} 443 444/** 445 * sil_sata_pre_reset - reset hook 446 * @drive: IDE device being reset 447 * 448 * For the SATA devices we need to handle recalibration/geometry 449 * differently 450 */ 451 452static void sil_sata_pre_reset(ide_drive_t *drive) 453{ 454 if (drive->media == ide_disk) { 455 drive->special_flags &= 456 ~(IDE_SFLAG_SET_GEOMETRY | IDE_SFLAG_RECALIBRATE); 457 } 458} 459 460/** 461 * init_chipset_siimage - set up an SI device 462 * @dev: PCI device 463 * 464 * Perform the initial PCI set up for this device. Attempt to switch 465 * to 133 MHz clocking if the system isn't already set up to do it. 466 */ 467 468static int init_chipset_siimage(struct pci_dev *dev) 469{ 470 struct ide_host *host = pci_get_drvdata(dev); 471 void __iomem *ioaddr = host->host_priv; 472 unsigned long base, scsc_addr; 473 u8 rev = dev->revision, tmp; 474 475 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); 476 477 if (ioaddr) 478 pci_set_master(dev); 479 480 base = (unsigned long)ioaddr; 481 482 if (ioaddr && pdev_is_sata(dev)) { 483 u32 tmp32, irq_mask; 484 485 /* make sure IDE0/1 interrupts are not masked */ 486 irq_mask = (1 << 22) | (1 << 23); 487 tmp32 = readl(ioaddr + 0x48); 488 if (tmp32 & irq_mask) { 489 tmp32 &= ~irq_mask; 490 writel(tmp32, ioaddr + 0x48); 491 readl(ioaddr + 0x48); /* flush */ 492 } 493 writel(0, ioaddr + 0x148); 494 writel(0, ioaddr + 0x1C8); 495 } 496 497 sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80); 498 sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84); 499 500 scsc_addr = base ? (base + 0x4A) : 0x8A; 501 tmp = sil_ioread8(dev, scsc_addr); 502 503 switch (tmp & 0x30) { 504 case 0x00: 505 /* On 100 MHz clocking, try and switch to 133 MHz */ 506 sil_iowrite8(dev, tmp | 0x10, scsc_addr); 507 break; 508 case 0x30: 509 /* Clocking is disabled, attempt to force 133MHz clocking. */ 510 sil_iowrite8(dev, tmp & ~0x20, scsc_addr); 511 case 0x10: 512 /* On 133Mhz clocking. */ 513 break; 514 case 0x20: 515 /* On PCIx2 clocking. */ 516 break; 517 } 518 519 tmp = sil_ioread8(dev, scsc_addr); 520 521 sil_iowrite8 (dev, 0x72, base + 0xA1); 522 sil_iowrite16(dev, 0x328A, base + 0xA2); 523 sil_iowrite32(dev, 0x62DD62DD, base + 0xA4); 524 sil_iowrite32(dev, 0x43924392, base + 0xA8); 525 sil_iowrite32(dev, 0x40094009, base + 0xAC); 526 sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1); 527 sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2); 528 sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4); 529 sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8); 530 sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC); 531 532 if (base && pdev_is_sata(dev)) { 533 writel(0xFFFF0000, ioaddr + 0x108); 534 writel(0xFFFF0000, ioaddr + 0x188); 535 writel(0x00680000, ioaddr + 0x148); 536 writel(0x00680000, ioaddr + 0x1C8); 537 } 538 539 /* report the clocking mode of the controller */ 540 if (!pdev_is_sata(dev)) { 541 static const char *clk_str[] = 542 { "== 100", "== 133", "== 2X PCI", "DISABLED!" }; 543 544 tmp >>= 4; 545 printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n", 546 pci_name(dev), clk_str[tmp & 3]); 547 } 548 549 return 0; 550} 551 552/** 553 * init_mmio_iops_siimage - set up the iops for MMIO 554 * @hwif: interface to set up 555 * 556 * The basic setup here is fairly simple, we can use standard MMIO 557 * operations. However we do have to set the taskfile register offsets 558 * by hand as there isn't a standard defined layout for them this time. 559 * 560 * The hardware supports buffered taskfiles and also some rather nice 561 * extended PRD tables. For better SI3112 support use the libata driver 562 */ 563 564static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) 565{ 566 struct pci_dev *dev = to_pci_dev(hwif->dev); 567 struct ide_host *host = pci_get_drvdata(dev); 568 void *addr = host->host_priv; 569 u8 ch = hwif->channel; 570 struct ide_io_ports *io_ports = &hwif->io_ports; 571 unsigned long base; 572 573 /* 574 * Fill in the basic hwif bits 575 */ 576 hwif->host_flags |= IDE_HFLAG_MMIO; 577 578 hwif->hwif_data = addr; 579 580 /* 581 * Now set up the hw. We have to do this ourselves as the 582 * MMIO layout isn't the same as the standard port based I/O. 583 */ 584 memset(io_ports, 0, sizeof(*io_ports)); 585 586 base = (unsigned long)addr; 587 if (ch) 588 base += 0xC0; 589 else 590 base += 0x80; 591 592 /* 593 * The buffered task file doesn't have status/control, so we 594 * can't currently use it sanely since we want to use LBA48 mode. 595 */ 596 io_ports->data_addr = base; 597 io_ports->error_addr = base + 1; 598 io_ports->nsect_addr = base + 2; 599 io_ports->lbal_addr = base + 3; 600 io_ports->lbam_addr = base + 4; 601 io_ports->lbah_addr = base + 5; 602 io_ports->device_addr = base + 6; 603 io_ports->status_addr = base + 7; 604 io_ports->ctl_addr = base + 10; 605 606 if (pdev_is_sata(dev)) { 607 base = (unsigned long)addr; 608 if (ch) 609 base += 0x80; 610 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; 611 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; 612 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; 613 } 614 615 hwif->irq = dev->irq; 616 617 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00); 618} 619 620static int is_dev_seagate_sata(ide_drive_t *drive) 621{ 622 const char *s = (const char *)&drive->id[ATA_ID_PROD]; 623 unsigned len = strnlen(s, ATA_ID_PROD_LEN); 624 625 if ((len > 4) && (!memcmp(s, "ST", 2))) 626 if ((!memcmp(s + len - 2, "AS", 2)) || 627 (!memcmp(s + len - 3, "ASL", 3))) { 628 printk(KERN_INFO "%s: applying pessimistic Seagate " 629 "errata fix\n", drive->name); 630 return 1; 631 } 632 633 return 0; 634} 635 636/** 637 * sil_quirkproc - post probe fixups 638 * @drive: drive 639 * 640 * Called after drive probe we use this to decide whether the 641 * Seagate fixup must be applied. This used to be in init_iops but 642 * that can occur before we know what drives are present. 643 */ 644 645static void sil_quirkproc(ide_drive_t *drive) 646{ 647 ide_hwif_t *hwif = drive->hwif; 648 649 /* Try and rise the rqsize */ 650 if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) 651 hwif->rqsize = 128; 652} 653 654/** 655 * init_iops_siimage - set up iops 656 * @hwif: interface to set up 657 * 658 * Do the basic setup for the SIIMAGE hardware interface 659 * and then do the MMIO setup if we can. This is the first 660 * look in we get for setting up the hwif so that we 661 * can get the iops right before using them. 662 */ 663 664static void __devinit init_iops_siimage(ide_hwif_t *hwif) 665{ 666 struct pci_dev *dev = to_pci_dev(hwif->dev); 667 struct ide_host *host = pci_get_drvdata(dev); 668 669 hwif->hwif_data = NULL; 670 671 /* Pessimal until we finish probing */ 672 hwif->rqsize = 15; 673 674 if (host->host_priv) 675 init_mmio_iops_siimage(hwif); 676} 677 678/** 679 * sil_cable_detect - cable detection 680 * @hwif: interface to check 681 * 682 * Check for the presence of an ATA66 capable cable on the interface. 683 */ 684 685static u8 sil_cable_detect(ide_hwif_t *hwif) 686{ 687 struct pci_dev *dev = to_pci_dev(hwif->dev); 688 unsigned long addr = siimage_selreg(hwif, 0); 689 u8 ata66 = sil_ioread8(dev, addr); 690 691 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; 692} 693 694static const struct ide_port_ops sil_pata_port_ops = { 695 .set_pio_mode = sil_set_pio_mode, 696 .set_dma_mode = sil_set_dma_mode, 697 .quirkproc = sil_quirkproc, 698 .udma_filter = sil_pata_udma_filter, 699 .cable_detect = sil_cable_detect, 700}; 701 702static const struct ide_port_ops sil_sata_port_ops = { 703 .set_pio_mode = sil_set_pio_mode, 704 .set_dma_mode = sil_set_dma_mode, 705 .reset_poll = sil_sata_reset_poll, 706 .pre_reset = sil_sata_pre_reset, 707 .quirkproc = sil_quirkproc, 708 .udma_filter = sil_sata_udma_filter, 709 .cable_detect = sil_cable_detect, 710}; 711 712static const struct ide_dma_ops sil_dma_ops = { 713 .dma_host_set = ide_dma_host_set, 714 .dma_setup = ide_dma_setup, 715 .dma_start = ide_dma_start, 716 .dma_end = ide_dma_end, 717 .dma_test_irq = siimage_dma_test_irq, 718 .dma_timer_expiry = ide_dma_sff_timer_expiry, 719 .dma_lost_irq = ide_dma_lost_irq, 720 .dma_sff_read_status = ide_dma_sff_read_status, 721}; 722 723#define DECLARE_SII_DEV(p_ops) \ 724 { \ 725 .name = DRV_NAME, \ 726 .init_chipset = init_chipset_siimage, \ 727 .init_iops = init_iops_siimage, \ 728 .port_ops = p_ops, \ 729 .dma_ops = &sil_dma_ops, \ 730 .pio_mask = ATA_PIO4, \ 731 .mwdma_mask = ATA_MWDMA2, \ 732 .udma_mask = ATA_UDMA6, \ 733 } 734 735static const struct ide_port_info siimage_chipsets[] __devinitdata = { 736 /* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops), 737 /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops) 738}; 739 740/** 741 * siimage_init_one - PCI layer discovery entry 742 * @dev: PCI device 743 * @id: ident table entry 744 * 745 * Called by the PCI code when it finds an SiI680 or SiI3112 controller. 746 * We then use the IDE PCI generic helper to do most of the work. 747 */ 748 749static int __devinit siimage_init_one(struct pci_dev *dev, 750 const struct pci_device_id *id) 751{ 752 void __iomem *ioaddr = NULL; 753 resource_size_t bar5 = pci_resource_start(dev, 5); 754 unsigned long barsize = pci_resource_len(dev, 5); 755 int rc; 756 struct ide_port_info d; 757 u8 idx = id->driver_data; 758 u8 BA5_EN; 759 760 d = siimage_chipsets[idx]; 761 762 if (idx) { 763 static int first = 1; 764 765 if (first) { 766 printk(KERN_INFO DRV_NAME ": For full SATA support you " 767 "should use the libata sata_sil module.\n"); 768 first = 0; 769 } 770 771 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA; 772 } 773 774 rc = pci_enable_device(dev); 775 if (rc) 776 return rc; 777 778 pci_read_config_byte(dev, 0x8A, &BA5_EN); 779 if ((BA5_EN & 0x01) || bar5) { 780 /* 781 * Drop back to PIO if we can't map the MMIO. Some systems 782 * seem to get terminally confused in the PCI spaces. 783 */ 784 if (!request_mem_region(bar5, barsize, d.name)) { 785 printk(KERN_WARNING DRV_NAME " %s: MMIO ports not " 786 "available\n", pci_name(dev)); 787 } else { 788 ioaddr = pci_ioremap_bar(dev, 5); 789 if (ioaddr == NULL) 790 release_mem_region(bar5, barsize); 791 } 792 } 793 794 rc = ide_pci_init_one(dev, &d, ioaddr); 795 if (rc) { 796 if (ioaddr) { 797 iounmap(ioaddr); 798 release_mem_region(bar5, barsize); 799 } 800 pci_disable_device(dev); 801 } 802 803 return rc; 804} 805 806static void __devexit siimage_remove(struct pci_dev *dev) 807{ 808 struct ide_host *host = pci_get_drvdata(dev); 809 void __iomem *ioaddr = host->host_priv; 810 811 ide_pci_remove(dev); 812 813 if (ioaddr) { 814 resource_size_t bar5 = pci_resource_start(dev, 5); 815 unsigned long barsize = pci_resource_len(dev, 5); 816 817 iounmap(ioaddr); 818 release_mem_region(bar5, barsize); 819 } 820 821 pci_disable_device(dev); 822} 823 824static const struct pci_device_id siimage_pci_tbl[] = { 825 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 }, 826#ifdef CONFIG_BLK_DEV_IDE_SATA 827 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 }, 828 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 }, 829#endif 830 { 0, }, 831}; 832MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); 833 834static struct pci_driver siimage_pci_driver = { 835 .name = "SiI_IDE", 836 .id_table = siimage_pci_tbl, 837 .probe = siimage_init_one, 838 .remove = __devexit_p(siimage_remove), 839 .suspend = ide_pci_suspend, 840 .resume = ide_pci_resume, 841}; 842 843static int __init siimage_ide_init(void) 844{ 845 return ide_pci_register_driver(&siimage_pci_driver); 846} 847 848static void __exit siimage_ide_exit(void) 849{ 850 pci_unregister_driver(&siimage_pci_driver); 851} 852 853module_init(siimage_ide_init); 854module_exit(siimage_ide_exit); 855 856MODULE_AUTHOR("Andre Hedrick, Alan Cox"); 857MODULE_DESCRIPTION("PCI driver module for SiI IDE"); 858MODULE_LICENSE("GPL"); 859