sl82c105.c revision e085b3cae85af47eb0a3eda3186bd898310fb322 
1/*
2 * SL82C105/Winbond 553 IDE driver
3 *
4 * Maintainer unknown.
5 *
6 * Drive tuning added from Rebel.com's kernel sources
7 *  -- Russell King (15/11/98) linux@arm.linux.org.uk
8 *
9 * Merge in Russell's HW workarounds, fix various problems
10 * with the timing registers setup.
11 *  -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
12 *
13 * Copyright (C) 2006-2007,2009 MontaVista Software, Inc. <source@mvista.com>
14 * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
15 */
16
17#include <linux/types.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/ide.h>
22
23#include <asm/io.h>
24
25#define DRV_NAME "sl82c105"
26
27/*
28 * SL82C105 PCI config register 0x40 bits.
29 */
30#define CTRL_IDE_IRQB   (1 << 30)
31#define CTRL_IDE_IRQA   (1 << 28)
32#define CTRL_LEGIRQ     (1 << 11)
33#define CTRL_P1F16      (1 << 5)
34#define CTRL_P1EN       (1 << 4)
35#define CTRL_P0F16      (1 << 1)
36#define CTRL_P0EN       (1 << 0)
37
38/*
39 * Convert a PIO mode and cycle time to the required on/off times
40 * for the interface.  This has protection against runaway timings.
41 */
42static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
43{
44	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
45	unsigned int cmd_on, cmd_off;
46	u8 iordy = 0;
47
48	cmd_on  = (t->active + 29) / 30;
49	cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
50
51	if (cmd_on == 0)
52		cmd_on = 1;
53
54	if (cmd_off == 0)
55		cmd_off = 1;
56
57	if (ide_pio_need_iordy(drive, pio))
58		iordy = 0x40;
59
60	return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
61}
62
63/*
64 * Configure the chipset for PIO mode.
65 */
66static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
67{
68	struct pci_dev *dev	= to_pci_dev(hwif->dev);
69	unsigned long timings	= (unsigned long)ide_get_drivedata(drive);
70	int reg			= 0x44 + drive->dn * 4;
71	u16 drv_ctrl;
72	const u8 pio		= drive->pio_mode - XFER_PIO_0;
73
74	drv_ctrl = get_pio_timings(drive, pio);
75
76	/*
77	 * Store the PIO timings so that we can restore them
78	 * in case DMA will be turned off...
79	 */
80	timings &= 0xffff0000;
81	timings |= drv_ctrl;
82	ide_set_drivedata(drive, (void *)timings);
83
84	pci_write_config_word(dev, reg,  drv_ctrl);
85	pci_read_config_word (dev, reg, &drv_ctrl);
86
87	printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
88			  ide_xfer_verbose(pio + XFER_PIO_0),
89			  ide_pio_cycle_time(drive, pio), drv_ctrl);
90}
91
92/*
93 * Configure the chipset for DMA mode.
94 */
95static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
96{
97	static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
98	unsigned long timings = (unsigned long)ide_get_drivedata(drive);
99	u16 drv_ctrl;
100
101	drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
102
103	/*
104	 * Store the DMA timings so that we can actually program
105	 * them when DMA will be turned on...
106	 */
107	timings &= 0x0000ffff;
108	timings |= (unsigned long)drv_ctrl << 16;
109	ide_set_drivedata(drive, (void *)timings);
110}
111
112static int sl82c105_test_irq(ide_hwif_t *hwif)
113{
114	struct pci_dev *dev	= to_pci_dev(hwif->dev);
115	u32 val, mask		= hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
116
117	pci_read_config_dword(dev, 0x40, &val);
118
119	return (val & mask) ? 1 : 0;
120}
121
122/*
123 * The SL82C105 holds off all IDE interrupts while in DMA mode until
124 * all DMA activity is completed.  Sometimes this causes problems (eg,
125 * when the drive wants to report an error condition).
126 *
127 * 0x7e is a "chip testing" register.  Bit 2 resets the DMA controller
128 * state machine.  We need to kick this to work around various bugs.
129 */
130static inline void sl82c105_reset_host(struct pci_dev *dev)
131{
132	u16 val;
133
134	pci_read_config_word(dev, 0x7e, &val);
135	pci_write_config_word(dev, 0x7e, val | (1 << 2));
136	pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
137}
138
139/*
140 * If we get an IRQ timeout, it might be that the DMA state machine
141 * got confused.  Fix from Todd Inglett.  Details from Winbond.
142 *
143 * This function is called when the IDE timer expires, the drive
144 * indicates that it is READY, and we were waiting for DMA to complete.
145 */
146static void sl82c105_dma_lost_irq(ide_drive_t *drive)
147{
148	ide_hwif_t *hwif	= drive->hwif;
149	struct pci_dev *dev	= to_pci_dev(hwif->dev);
150	u32 val, mask		= hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
151	u8 dma_cmd;
152
153	printk(KERN_WARNING "sl82c105: lost IRQ, resetting host\n");
154
155	/*
156	 * Check the raw interrupt from the drive.
157	 */
158	pci_read_config_dword(dev, 0x40, &val);
159	if (val & mask)
160		printk(KERN_INFO "sl82c105: drive was requesting IRQ, "
161		       "but host lost it\n");
162
163	/*
164	 * Was DMA enabled?  If so, disable it - we're resetting the
165	 * host.  The IDE layer will be handling the drive for us.
166	 */
167	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
168	if (dma_cmd & 1) {
169		outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
170		printk(KERN_INFO "sl82c105: DMA was enabled\n");
171	}
172
173	sl82c105_reset_host(dev);
174}
175
176/*
177 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
178 * Winbond recommend that the DMA state machine is reset prior to
179 * setting the bus master DMA enable bit.
180 *
181 * The generic IDE core will have disabled the BMEN bit before this
182 * function is called.
183 */
184static void sl82c105_dma_start(ide_drive_t *drive)
185{
186	ide_hwif_t *hwif	= drive->hwif;
187	struct pci_dev *dev	= to_pci_dev(hwif->dev);
188	int reg 		= 0x44 + drive->dn * 4;
189
190	pci_write_config_word(dev, reg,
191			      (unsigned long)ide_get_drivedata(drive) >> 16);
192
193	sl82c105_reset_host(dev);
194	ide_dma_start(drive);
195}
196
197static void sl82c105_dma_clear(ide_drive_t *drive)
198{
199	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
200
201	sl82c105_reset_host(dev);
202}
203
204static int sl82c105_dma_end(ide_drive_t *drive)
205{
206	struct pci_dev *dev	= to_pci_dev(drive->hwif->dev);
207	int reg 		= 0x44 + drive->dn * 4;
208	int ret			= ide_dma_end(drive);
209
210	pci_write_config_word(dev, reg,
211			      (unsigned long)ide_get_drivedata(drive));
212
213	return ret;
214}
215
216/*
217 * ATA reset will clear the 16 bits mode in the control
218 * register, we need to reprogram it
219 */
220static void sl82c105_resetproc(ide_drive_t *drive)
221{
222	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
223	u32 val;
224
225	pci_read_config_dword(dev, 0x40, &val);
226	val |= (CTRL_P1F16 | CTRL_P0F16);
227	pci_write_config_dword(dev, 0x40, val);
228}
229
230/*
231 * Return the revision of the Winbond bridge
232 * which this function is part of.
233 */
234static u8 sl82c105_bridge_revision(struct pci_dev *dev)
235{
236	struct pci_dev *bridge;
237
238	/*
239	 * The bridge should be part of the same device, but function 0.
240	 */
241	bridge = pci_get_bus_and_slot(dev->bus->number,
242			       PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
243	if (!bridge)
244		return -1;
245
246	/*
247	 * Make sure it is a Winbond 553 and is an ISA bridge.
248	 */
249	if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
250	    bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
251	    bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
252	    	pci_dev_put(bridge);
253		return -1;
254	}
255	/*
256	 * We need to find function 0's revision, not function 1
257	 */
258	pci_dev_put(bridge);
259
260	return bridge->revision;
261}
262
263/*
264 * Enable the PCI device
265 *
266 * --BenH: It's arch fixup code that should enable channels that
267 * have not been enabled by firmware. I decided we can still enable
268 * channel 0 here at least, but channel 1 has to be enabled by
269 * firmware or arch code. We still set both to 16 bits mode.
270 */
271static int init_chipset_sl82c105(struct pci_dev *dev)
272{
273	u32 val;
274
275	pci_read_config_dword(dev, 0x40, &val);
276	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
277	pci_write_config_dword(dev, 0x40, val);
278
279	return 0;
280}
281
282static const struct ide_port_ops sl82c105_port_ops = {
283	.set_pio_mode		= sl82c105_set_pio_mode,
284	.set_dma_mode		= sl82c105_set_dma_mode,
285	.resetproc		= sl82c105_resetproc,
286	.test_irq		= sl82c105_test_irq,
287};
288
289static const struct ide_dma_ops sl82c105_dma_ops = {
290	.dma_host_set		= ide_dma_host_set,
291	.dma_setup		= ide_dma_setup,
292	.dma_start		= sl82c105_dma_start,
293	.dma_end		= sl82c105_dma_end,
294	.dma_test_irq		= ide_dma_test_irq,
295	.dma_lost_irq		= sl82c105_dma_lost_irq,
296	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
297	.dma_clear		= sl82c105_dma_clear,
298	.dma_sff_read_status	= ide_dma_sff_read_status,
299};
300
301static const struct ide_port_info sl82c105_chipset __devinitdata = {
302	.name		= DRV_NAME,
303	.init_chipset	= init_chipset_sl82c105,
304	.enablebits	= {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
305	.port_ops	= &sl82c105_port_ops,
306	.dma_ops	= &sl82c105_dma_ops,
307	.host_flags	= IDE_HFLAG_IO_32BIT |
308			  IDE_HFLAG_UNMASK_IRQS |
309			  IDE_HFLAG_SERIALIZE_DMA |
310			  IDE_HFLAG_NO_AUTODMA,
311	.pio_mask	= ATA_PIO5,
312	.mwdma_mask	= ATA_MWDMA2,
313};
314
315static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
316{
317	struct ide_port_info d = sl82c105_chipset;
318	u8 rev = sl82c105_bridge_revision(dev);
319
320	if (rev <= 5) {
321		/*
322		 * Never ever EVER under any circumstances enable
323		 * DMA when the bridge is this old.
324		 */
325		printk(KERN_INFO DRV_NAME ": Winbond W83C553 bridge "
326				 "revision %d, BM-DMA disabled\n", rev);
327		d.dma_ops = NULL;
328		d.mwdma_mask = 0;
329		d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA;
330	}
331
332	return ide_pci_init_one(dev, &d, NULL);
333}
334
335static const struct pci_device_id sl82c105_pci_tbl[] = {
336	{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 },
337	{ 0, },
338};
339MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
340
341static struct pci_driver sl82c105_pci_driver = {
342	.name		= "W82C105_IDE",
343	.id_table	= sl82c105_pci_tbl,
344	.probe		= sl82c105_init_one,
345	.remove		= ide_pci_remove,
346	.suspend	= ide_pci_suspend,
347	.resume		= ide_pci_resume,
348};
349
350static int __init sl82c105_ide_init(void)
351{
352	return ide_pci_register_driver(&sl82c105_pci_driver);
353}
354
355static void __exit sl82c105_ide_exit(void)
356{
357	pci_unregister_driver(&sl82c105_pci_driver);
358}
359
360module_init(sl82c105_ide_init);
361module_exit(sl82c105_ide_exit);
362
363MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
364MODULE_LICENSE("GPL");
365