sl82c105.c revision f9288e1525e1cca59fdca56463ad9f5a6625dffe 
1/*
2 * SL82C105/Winbond 553 IDE driver
3 *
4 * Maintainer unknown.
5 *
6 * Drive tuning added from Rebel.com's kernel sources
7 *  -- Russell King (15/11/98) linux@arm.linux.org.uk
8 *
9 * Merge in Russell's HW workarounds, fix various problems
10 * with the timing registers setup.
11 *  -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
12 *
13 * Copyright (C) 2006-2007,2009 MontaVista Software, Inc. <source@mvista.com>
14 * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
15 */
16
17#include <linux/types.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/ide.h>
22
23#include <asm/io.h>
24
25#define DRV_NAME "sl82c105"
26
27/*
28 * SL82C105 PCI config register 0x40 bits.
29 */
30#define CTRL_IDE_IRQB   (1 << 30)
31#define CTRL_IDE_IRQA   (1 << 28)
32#define CTRL_LEGIRQ     (1 << 11)
33#define CTRL_P1F16      (1 << 5)
34#define CTRL_P1EN       (1 << 4)
35#define CTRL_P0F16      (1 << 1)
36#define CTRL_P0EN       (1 << 0)
37
38/*
39 * Convert a PIO mode and cycle time to the required on/off times
40 * for the interface.  This has protection against runaway timings.
41 */
42static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
43{
44	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
45	unsigned int cmd_on, cmd_off;
46	u8 iordy = 0;
47
48	cmd_on  = (t->active + 29) / 30;
49	cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
50
51	if (cmd_on == 0)
52		cmd_on = 1;
53
54	if (cmd_off == 0)
55		cmd_off = 1;
56
57	if (ide_pio_need_iordy(drive, pio))
58		iordy = 0x40;
59
60	return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
61}
62
63/*
64 * Configure the chipset for PIO mode.
65 */
66static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
67{
68	struct pci_dev *dev	= to_pci_dev(drive->hwif->dev);
69	unsigned long timings	= (unsigned long)ide_get_drivedata(drive);
70	int reg			= 0x44 + drive->dn * 4;
71	u16 drv_ctrl;
72
73	drv_ctrl = get_pio_timings(drive, pio);
74
75	/*
76	 * Store the PIO timings so that we can restore them
77	 * in case DMA will be turned off...
78	 */
79	timings &= 0xffff0000;
80	timings |= drv_ctrl;
81	ide_set_drivedata(drive, (void *)timings);
82
83	pci_write_config_word(dev, reg,  drv_ctrl);
84	pci_read_config_word (dev, reg, &drv_ctrl);
85
86	printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
87			  ide_xfer_verbose(pio + XFER_PIO_0),
88			  ide_pio_cycle_time(drive, pio), drv_ctrl);
89}
90
91/*
92 * Configure the chipset for DMA mode.
93 */
94static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
95{
96	static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
97	unsigned long timings = (unsigned long)ide_get_drivedata(drive);
98	u16 drv_ctrl;
99
100	drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
101
102	/*
103	 * Store the DMA timings so that we can actually program
104	 * them when DMA will be turned on...
105	 */
106	timings &= 0x0000ffff;
107	timings |= (unsigned long)drv_ctrl << 16;
108	ide_set_drivedata(drive, (void *)timings);
109}
110
111static int sl82c105_test_irq(ide_hwif_t *hwif)
112{
113	struct pci_dev *dev	= to_pci_dev(hwif->dev);
114	u32 val, mask		= hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
115
116	pci_read_config_dword(dev, 0x40, &val);
117
118	return (val & mask) ? 1 : 0;
119}
120
121/*
122 * The SL82C105 holds off all IDE interrupts while in DMA mode until
123 * all DMA activity is completed.  Sometimes this causes problems (eg,
124 * when the drive wants to report an error condition).
125 *
126 * 0x7e is a "chip testing" register.  Bit 2 resets the DMA controller
127 * state machine.  We need to kick this to work around various bugs.
128 */
129static inline void sl82c105_reset_host(struct pci_dev *dev)
130{
131	u16 val;
132
133	pci_read_config_word(dev, 0x7e, &val);
134	pci_write_config_word(dev, 0x7e, val | (1 << 2));
135	pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
136}
137
138/*
139 * If we get an IRQ timeout, it might be that the DMA state machine
140 * got confused.  Fix from Todd Inglett.  Details from Winbond.
141 *
142 * This function is called when the IDE timer expires, the drive
143 * indicates that it is READY, and we were waiting for DMA to complete.
144 */
145static void sl82c105_dma_lost_irq(ide_drive_t *drive)
146{
147	ide_hwif_t *hwif	= drive->hwif;
148	struct pci_dev *dev	= to_pci_dev(hwif->dev);
149	u32 val, mask		= hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
150	u8 dma_cmd;
151
152	printk(KERN_WARNING "sl82c105: lost IRQ, resetting host\n");
153
154	/*
155	 * Check the raw interrupt from the drive.
156	 */
157	pci_read_config_dword(dev, 0x40, &val);
158	if (val & mask)
159		printk(KERN_INFO "sl82c105: drive was requesting IRQ, "
160		       "but host lost it\n");
161
162	/*
163	 * Was DMA enabled?  If so, disable it - we're resetting the
164	 * host.  The IDE layer will be handling the drive for us.
165	 */
166	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
167	if (dma_cmd & 1) {
168		outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
169		printk(KERN_INFO "sl82c105: DMA was enabled\n");
170	}
171
172	sl82c105_reset_host(dev);
173}
174
175/*
176 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
177 * Winbond recommend that the DMA state machine is reset prior to
178 * setting the bus master DMA enable bit.
179 *
180 * The generic IDE core will have disabled the BMEN bit before this
181 * function is called.
182 */
183static void sl82c105_dma_start(ide_drive_t *drive)
184{
185	ide_hwif_t *hwif	= drive->hwif;
186	struct pci_dev *dev	= to_pci_dev(hwif->dev);
187	int reg 		= 0x44 + drive->dn * 4;
188
189	pci_write_config_word(dev, reg,
190			      (unsigned long)ide_get_drivedata(drive) >> 16);
191
192	sl82c105_reset_host(dev);
193	ide_dma_start(drive);
194}
195
196static void sl82c105_dma_clear(ide_drive_t *drive)
197{
198	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
199
200	sl82c105_reset_host(dev);
201}
202
203static int sl82c105_dma_end(ide_drive_t *drive)
204{
205	struct pci_dev *dev	= to_pci_dev(drive->hwif->dev);
206	int reg 		= 0x44 + drive->dn * 4;
207	int ret			= ide_dma_end(drive);
208
209	pci_write_config_word(dev, reg,
210			      (unsigned long)ide_get_drivedata(drive));
211
212	return ret;
213}
214
215/*
216 * ATA reset will clear the 16 bits mode in the control
217 * register, we need to reprogram it
218 */
219static void sl82c105_resetproc(ide_drive_t *drive)
220{
221	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
222	u32 val;
223
224	pci_read_config_dword(dev, 0x40, &val);
225	val |= (CTRL_P1F16 | CTRL_P0F16);
226	pci_write_config_dword(dev, 0x40, val);
227}
228
229/*
230 * Return the revision of the Winbond bridge
231 * which this function is part of.
232 */
233static u8 sl82c105_bridge_revision(struct pci_dev *dev)
234{
235	struct pci_dev *bridge;
236
237	/*
238	 * The bridge should be part of the same device, but function 0.
239	 */
240	bridge = pci_get_bus_and_slot(dev->bus->number,
241			       PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
242	if (!bridge)
243		return -1;
244
245	/*
246	 * Make sure it is a Winbond 553 and is an ISA bridge.
247	 */
248	if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
249	    bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
250	    bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
251	    	pci_dev_put(bridge);
252		return -1;
253	}
254	/*
255	 * We need to find function 0's revision, not function 1
256	 */
257	pci_dev_put(bridge);
258
259	return bridge->revision;
260}
261
262/*
263 * Enable the PCI device
264 *
265 * --BenH: It's arch fixup code that should enable channels that
266 * have not been enabled by firmware. I decided we can still enable
267 * channel 0 here at least, but channel 1 has to be enabled by
268 * firmware or arch code. We still set both to 16 bits mode.
269 */
270static int init_chipset_sl82c105(struct pci_dev *dev)
271{
272	u32 val;
273
274	pci_read_config_dword(dev, 0x40, &val);
275	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
276	pci_write_config_dword(dev, 0x40, val);
277
278	return 0;
279}
280
281static const struct ide_port_ops sl82c105_port_ops = {
282	.set_pio_mode		= sl82c105_set_pio_mode,
283	.set_dma_mode		= sl82c105_set_dma_mode,
284	.resetproc		= sl82c105_resetproc,
285	.test_irq		= sl82c105_test_irq,
286};
287
288static const struct ide_dma_ops sl82c105_dma_ops = {
289	.dma_host_set		= ide_dma_host_set,
290	.dma_setup		= ide_dma_setup,
291	.dma_start		= sl82c105_dma_start,
292	.dma_end		= sl82c105_dma_end,
293	.dma_test_irq		= ide_dma_test_irq,
294	.dma_lost_irq		= sl82c105_dma_lost_irq,
295	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
296	.dma_clear		= sl82c105_dma_clear,
297	.dma_sff_read_status	= ide_dma_sff_read_status,
298};
299
300static const struct ide_port_info sl82c105_chipset __devinitdata = {
301	.name		= DRV_NAME,
302	.init_chipset	= init_chipset_sl82c105,
303	.enablebits	= {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
304	.port_ops	= &sl82c105_port_ops,
305	.dma_ops	= &sl82c105_dma_ops,
306	.host_flags	= IDE_HFLAG_IO_32BIT |
307			  IDE_HFLAG_UNMASK_IRQS |
308			  IDE_HFLAG_SERIALIZE_DMA |
309			  IDE_HFLAG_NO_AUTODMA,
310	.pio_mask	= ATA_PIO5,
311	.mwdma_mask	= ATA_MWDMA2,
312};
313
314static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
315{
316	struct ide_port_info d = sl82c105_chipset;
317	u8 rev = sl82c105_bridge_revision(dev);
318
319	if (rev <= 5) {
320		/*
321		 * Never ever EVER under any circumstances enable
322		 * DMA when the bridge is this old.
323		 */
324		printk(KERN_INFO DRV_NAME ": Winbond W83C553 bridge "
325				 "revision %d, BM-DMA disabled\n", rev);
326		d.dma_ops = NULL;
327		d.mwdma_mask = 0;
328		d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA;
329	}
330
331	return ide_pci_init_one(dev, &d, NULL);
332}
333
334static const struct pci_device_id sl82c105_pci_tbl[] = {
335	{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 },
336	{ 0, },
337};
338MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
339
340static struct pci_driver sl82c105_pci_driver = {
341	.name		= "W82C105_IDE",
342	.id_table	= sl82c105_pci_tbl,
343	.probe		= sl82c105_init_one,
344	.remove		= ide_pci_remove,
345	.suspend	= ide_pci_suspend,
346	.resume		= ide_pci_resume,
347};
348
349static int __init sl82c105_ide_init(void)
350{
351	return ide_pci_register_driver(&sl82c105_pci_driver);
352}
353
354static void __exit sl82c105_ide_exit(void)
355{
356	pci_unregister_driver(&sl82c105_pci_driver);
357}
358
359module_init(sl82c105_ide_init);
360module_exit(sl82c105_ide_exit);
361
362MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
363MODULE_LICENSE("GPL");
364