tx4939ide.c revision 4453011f959a5f5c6c7a33aea54fe17f5e43a867
1/* 2 * TX4939 internal IDE driver 3 * Based on RBTX49xx patch from CELF patch archive. 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file "COPYING" in the main directory of this archive 7 * for more details. 8 * 9 * (C) Copyright TOSHIBA CORPORATION 2005-2007 10 */ 11 12#include <linux/module.h> 13#include <linux/types.h> 14#include <linux/ide.h> 15#include <linux/init.h> 16#include <linux/delay.h> 17#include <linux/platform_device.h> 18#include <linux/io.h> 19#include <linux/scatterlist.h> 20 21#include <asm/ide.h> 22 23#define MODNAME "tx4939ide" 24 25/* ATA Shadow Registers (8-bit except for Data which is 16-bit) */ 26#define TX4939IDE_Data 0x000 27#define TX4939IDE_Error_Feature 0x001 28#define TX4939IDE_Sec 0x002 29#define TX4939IDE_LBA0 0x003 30#define TX4939IDE_LBA1 0x004 31#define TX4939IDE_LBA2 0x005 32#define TX4939IDE_DevHead 0x006 33#define TX4939IDE_Stat_Cmd 0x007 34#define TX4939IDE_AltStat_DevCtl 0x402 35/* H/W DMA Registers */ 36#define TX4939IDE_DMA_Cmd 0x800 /* 8-bit */ 37#define TX4939IDE_DMA_Stat 0x802 /* 8-bit */ 38#define TX4939IDE_PRD_Ptr 0x804 /* 32-bit */ 39/* ATA100 CORE Registers (16-bit) */ 40#define TX4939IDE_Sys_Ctl 0xc00 41#define TX4939IDE_Xfer_Cnt_1 0xc08 42#define TX4939IDE_Xfer_Cnt_2 0xc0a 43#define TX4939IDE_Sec_Cnt 0xc10 44#define TX4939IDE_Start_Lo_Addr 0xc18 45#define TX4939IDE_Start_Up_Addr 0xc20 46#define TX4939IDE_Add_Ctl 0xc28 47#define TX4939IDE_Lo_Burst_Cnt 0xc30 48#define TX4939IDE_Up_Burst_Cnt 0xc38 49#define TX4939IDE_PIO_Addr 0xc88 50#define TX4939IDE_H_Rst_Tim 0xc90 51#define TX4939IDE_Int_Ctl 0xc98 52#define TX4939IDE_Pkt_Cmd 0xcb8 53#define TX4939IDE_Bxfer_Cnt_Hi 0xcc0 54#define TX4939IDE_Bxfer_Cnt_Lo 0xcc8 55#define TX4939IDE_Dev_TErr 0xcd0 56#define TX4939IDE_Pkt_Xfer_Ctl 0xcd8 57#define TX4939IDE_Start_TAddr 0xce0 58 59/* bits for Int_Ctl */ 60#define TX4939IDE_INT_ADDRERR 0x80 61#define TX4939IDE_INT_REACHMUL 0x40 62#define TX4939IDE_INT_DEVTIMING 0x20 63#define TX4939IDE_INT_UDMATERM 0x10 64#define TX4939IDE_INT_TIMER 0x08 65#define TX4939IDE_INT_BUSERR 0x04 66#define TX4939IDE_INT_XFEREND 0x02 67#define TX4939IDE_INT_HOST 0x01 68 69#define TX4939IDE_IGNORE_INTS \ 70 (TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \ 71 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \ 72 TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND) 73 74#ifdef __BIG_ENDIAN 75#define tx4939ide_swizzlel(a) ((a) ^ 4) 76#define tx4939ide_swizzlew(a) ((a) ^ 6) 77#define tx4939ide_swizzleb(a) ((a) ^ 7) 78#else 79#define tx4939ide_swizzlel(a) (a) 80#define tx4939ide_swizzlew(a) (a) 81#define tx4939ide_swizzleb(a) (a) 82#endif 83 84static u16 tx4939ide_readw(void __iomem *base, u32 reg) 85{ 86 return __raw_readw(base + tx4939ide_swizzlew(reg)); 87} 88static u8 tx4939ide_readb(void __iomem *base, u32 reg) 89{ 90 return __raw_readb(base + tx4939ide_swizzleb(reg)); 91} 92static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg) 93{ 94 __raw_writel(val, base + tx4939ide_swizzlel(reg)); 95} 96static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg) 97{ 98 __raw_writew(val, base + tx4939ide_swizzlew(reg)); 99} 100static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) 101{ 102 __raw_writeb(val, base + tx4939ide_swizzleb(reg)); 103} 104 105#define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base) 106 107static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio) 108{ 109 ide_hwif_t *hwif = drive->hwif; 110 int is_slave = drive->dn; 111 u32 mask, val; 112 u8 safe = pio; 113 ide_drive_t *pair; 114 115 pair = ide_get_pair_dev(drive); 116 if (pair) 117 safe = min(safe, ide_get_best_pio_mode(pair, 255, 4)); 118 /* 119 * Update Command Transfer Mode for master/slave and Data 120 * Transfer Mode for this drive. 121 */ 122 mask = is_slave ? 0x07f00000 : 0x000007f0; 123 val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0); 124 hwif->select_data = (hwif->select_data & ~mask) | val; 125 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */ 126} 127 128static void tx4939ide_set_dma_mode(ide_drive_t *drive, const u8 mode) 129{ 130 ide_hwif_t *hwif = drive->hwif; 131 u32 mask, val; 132 133 /* Update Data Transfer Mode for this drive. */ 134 if (mode >= XFER_UDMA_0) 135 val = mode - XFER_UDMA_0 + 8; 136 else 137 val = mode - XFER_MW_DMA_0 + 5; 138 if (drive->dn) { 139 mask = 0x00f00000; 140 val <<= 20; 141 } else { 142 mask = 0x000000f0; 143 val <<= 4; 144 } 145 hwif->select_data = (hwif->select_data & ~mask) | val; 146 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */ 147} 148 149static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif) 150{ 151 void __iomem *base = TX4939IDE_BASE(hwif); 152 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); 153 154 if (ctl & TX4939IDE_INT_BUSERR) { 155 /* reset FIFO */ 156 u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl); 157 158 tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl); 159 mmiowb(); 160 /* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */ 161 ndelay(270); 162 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl); 163 } 164 if (ctl & (TX4939IDE_INT_ADDRERR | 165 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR)) 166 pr_err("%s: Error interrupt %#x (%s%s%s )\n", 167 hwif->name, ctl, 168 ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "", 169 ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "", 170 ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : ""); 171 return ctl; 172} 173 174static void tx4939ide_clear_irq(ide_drive_t *drive) 175{ 176 ide_hwif_t *hwif; 177 void __iomem *base; 178 u16 ctl; 179 180 /* 181 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job 182 * for DMA case. 183 */ 184 if (drive->waiting_for_dma) 185 return; 186 hwif = drive->hwif; 187 base = TX4939IDE_BASE(hwif); 188 ctl = tx4939ide_check_error_ints(hwif); 189 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl); 190} 191 192static u8 tx4939ide_cable_detect(ide_hwif_t *hwif) 193{ 194 void __iomem *base = TX4939IDE_BASE(hwif); 195 196 return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ? 197 ATA_CBL_PATA40 : ATA_CBL_PATA80; 198} 199 200#ifdef __BIG_ENDIAN 201static void tx4939ide_dma_host_set(ide_drive_t *drive, int on) 202{ 203 ide_hwif_t *hwif = drive->hwif; 204 u8 unit = drive->dn; 205 void __iomem *base = TX4939IDE_BASE(hwif); 206 u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); 207 208 if (on) 209 dma_stat |= (1 << (5 + unit)); 210 else 211 dma_stat &= ~(1 << (5 + unit)); 212 213 tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat); 214} 215#else 216#define tx4939ide_dma_host_set ide_dma_host_set 217#endif 218 219static u8 tx4939ide_clear_dma_status(void __iomem *base) 220{ 221 u8 dma_stat; 222 223 /* read DMA status for INTR & ERROR flags */ 224 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); 225 /* clear INTR & ERROR flags */ 226 tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base, 227 TX4939IDE_DMA_Stat); 228 /* recover intmask cleared by writing to bit2 of DMA_Stat */ 229 tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl); 230 return dma_stat; 231} 232 233#ifdef __BIG_ENDIAN 234/* custom ide_build_dmatable to handle swapped layout */ 235static int tx4939ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd) 236{ 237 ide_hwif_t *hwif = drive->hwif; 238 u32 *table = (u32 *)hwif->dmatable_cpu; 239 unsigned int count = 0; 240 int i; 241 struct scatterlist *sg; 242 243 for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) { 244 u32 cur_addr, cur_len, bcount; 245 246 cur_addr = sg_dma_address(sg); 247 cur_len = sg_dma_len(sg); 248 249 /* 250 * Fill in the DMA table, without crossing any 64kB boundaries. 251 */ 252 253 while (cur_len) { 254 if (count++ >= PRD_ENTRIES) 255 goto use_pio_instead; 256 257 bcount = 0x10000 - (cur_addr & 0xffff); 258 if (bcount > cur_len) 259 bcount = cur_len; 260 /* 261 * This workaround for zero count seems required. 262 * (standard ide_build_dmatable does it too) 263 */ 264 if (bcount == 0x10000) 265 bcount = 0x8000; 266 *table++ = bcount & 0xffff; 267 *table++ = cur_addr; 268 cur_addr += bcount; 269 cur_len -= bcount; 270 } 271 } 272 273 if (count) { 274 *(table - 2) |= 0x80000000; 275 return count; 276 } 277 278use_pio_instead: 279 printk(KERN_ERR "%s: %s\n", drive->name, 280 count ? "DMA table too small" : "empty DMA table?"); 281 282 ide_destroy_dmatable(drive); 283 284 return 0; /* revert to PIO for this request */ 285} 286#else 287#define tx4939ide_build_dmatable ide_build_dmatable 288#endif 289 290static int tx4939ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) 291{ 292 ide_hwif_t *hwif = drive->hwif; 293 void __iomem *base = TX4939IDE_BASE(hwif); 294 u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR; 295 296 /* fall back to PIO! */ 297 if (tx4939ide_build_dmatable(drive, cmd) == 0) { 298 ide_map_sg(drive, cmd); 299 return 1; 300 } 301 302 /* PRD table */ 303 tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr); 304 305 /* specify r/w */ 306 tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd); 307 308 /* clear INTR & ERROR flags */ 309 tx4939ide_clear_dma_status(base); 310 311 drive->waiting_for_dma = 1; 312 313 tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ? 314 TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1); 315 316 tx4939ide_writew(cmd->rq->nr_sectors, base, TX4939IDE_Sec_Cnt); 317 318 return 0; 319} 320 321static int tx4939ide_dma_end(ide_drive_t *drive) 322{ 323 ide_hwif_t *hwif = drive->hwif; 324 u8 dma_stat, dma_cmd; 325 void __iomem *base = TX4939IDE_BASE(hwif); 326 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); 327 328 drive->waiting_for_dma = 0; 329 330 /* get DMA command mode */ 331 dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd); 332 /* stop DMA */ 333 tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd); 334 335 /* read and clear the INTR & ERROR bits */ 336 dma_stat = tx4939ide_clear_dma_status(base); 337 338 wmb(); 339 340 /* verify good DMA status */ 341 if ((dma_stat & (ATA_DMA_INTR | ATA_DMA_ERR | ATA_DMA_ACTIVE)) == 0 && 342 (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) == 343 (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) 344 /* INT_IDE lost... bug? */ 345 return 0; 346 return ((dma_stat & (ATA_DMA_INTR | ATA_DMA_ERR | ATA_DMA_ACTIVE)) != 347 ATA_DMA_INTR) ? 0x10 | dma_stat : 0; 348} 349 350/* returns 1 if DMA IRQ issued, 0 otherwise */ 351static int tx4939ide_dma_test_irq(ide_drive_t *drive) 352{ 353 ide_hwif_t *hwif = drive->hwif; 354 void __iomem *base = TX4939IDE_BASE(hwif); 355 u16 ctl, ide_int; 356 u8 dma_stat, stat; 357 int found = 0; 358 359 ctl = tx4939ide_check_error_ints(hwif); 360 ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST); 361 switch (ide_int) { 362 case TX4939IDE_INT_HOST: 363 /* On error, XFEREND might not be asserted. */ 364 stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl); 365 if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR) 366 found = 1; 367 else 368 /* Wait for XFEREND (Mask HOST and unmask XFEREND) */ 369 ctl &= ~TX4939IDE_INT_XFEREND << 8; 370 ctl |= ide_int << 8; 371 break; 372 case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND: 373 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); 374 if (!(dma_stat & ATA_DMA_INTR)) 375 pr_warning("%s: weird interrupt status. " 376 "DMA_Stat %#02x int_ctl %#04x\n", 377 hwif->name, dma_stat, ctl); 378 found = 1; 379 break; 380 } 381 /* 382 * Do not clear XFEREND, HOST now. They will be cleared by 383 * clearing bit2 of DMA_Stat. 384 */ 385 ctl &= ~ide_int; 386 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl); 387 return found; 388} 389 390#ifdef __BIG_ENDIAN 391static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif) 392{ 393 void __iomem *base = TX4939IDE_BASE(hwif); 394 395 return tx4939ide_readb(base, TX4939IDE_DMA_Stat); 396} 397#else 398#define tx4939ide_dma_sff_read_status ide_dma_sff_read_status 399#endif 400 401static void tx4939ide_init_hwif(ide_hwif_t *hwif) 402{ 403 void __iomem *base = TX4939IDE_BASE(hwif); 404 405 /* Soft Reset */ 406 tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl); 407 mmiowb(); 408 /* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */ 409 ndelay(450); 410 tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl); 411 /* mask some interrupts and clear all interrupts */ 412 tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base, 413 TX4939IDE_Int_Ctl); 414 415 tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt); 416 tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt); 417} 418 419static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d) 420{ 421 hwif->dma_base = 422 hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd); 423 /* 424 * Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS 425 * for big endian. 426 */ 427 return ide_allocate_dma_engine(hwif); 428} 429 430static void tx4939ide_tf_load_fixup(ide_drive_t *drive) 431{ 432 ide_hwif_t *hwif = drive->hwif; 433 void __iomem *base = TX4939IDE_BASE(hwif); 434 u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0); 435 436 /* 437 * Fix ATA100 CORE System Control Register. (The write to the 438 * Device/Head register may write wrong data to the System 439 * Control Register) 440 * While Sys_Ctl is written here, selectproc is not needed. 441 */ 442 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl); 443} 444 445#ifdef __BIG_ENDIAN 446 447/* custom iops (independent from SWAP_IO_SPACE) */ 448static u8 tx4939ide_inb(unsigned long port) 449{ 450 return __raw_readb((void __iomem *)port); 451} 452 453static void tx4939ide_outb(u8 value, unsigned long port) 454{ 455 __raw_writeb(value, (void __iomem *)port); 456} 457 458static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_cmd *cmd) 459{ 460 ide_hwif_t *hwif = drive->hwif; 461 struct ide_io_ports *io_ports = &hwif->io_ports; 462 struct ide_taskfile *tf = &cmd->tf; 463 u8 HIHI = cmd->tf_flags & IDE_TFLAG_LBA48 ? 0xE0 : 0xEF; 464 465 if (cmd->ftf_flags & IDE_FTFLAG_FLAGGED) 466 HIHI = 0xFF; 467 468 if (cmd->ftf_flags & IDE_FTFLAG_OUT_DATA) { 469 u16 data = (tf->hob_data << 8) | tf->data; 470 471 /* no endian swap */ 472 __raw_writew(data, (void __iomem *)io_ports->data_addr); 473 } 474 475 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE) 476 tx4939ide_outb(tf->hob_feature, io_ports->feature_addr); 477 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_NSECT) 478 tx4939ide_outb(tf->hob_nsect, io_ports->nsect_addr); 479 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAL) 480 tx4939ide_outb(tf->hob_lbal, io_ports->lbal_addr); 481 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAM) 482 tx4939ide_outb(tf->hob_lbam, io_ports->lbam_addr); 483 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAH) 484 tx4939ide_outb(tf->hob_lbah, io_ports->lbah_addr); 485 486 if (cmd->tf_flags & IDE_TFLAG_OUT_FEATURE) 487 tx4939ide_outb(tf->feature, io_ports->feature_addr); 488 if (cmd->tf_flags & IDE_TFLAG_OUT_NSECT) 489 tx4939ide_outb(tf->nsect, io_ports->nsect_addr); 490 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAL) 491 tx4939ide_outb(tf->lbal, io_ports->lbal_addr); 492 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAM) 493 tx4939ide_outb(tf->lbam, io_ports->lbam_addr); 494 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAH) 495 tx4939ide_outb(tf->lbah, io_ports->lbah_addr); 496 497 if (cmd->tf_flags & IDE_TFLAG_OUT_DEVICE) { 498 tx4939ide_outb((tf->device & HIHI) | drive->select, 499 io_ports->device_addr); 500 tx4939ide_tf_load_fixup(drive); 501 } 502} 503 504static void tx4939ide_tf_read(ide_drive_t *drive, struct ide_cmd *cmd) 505{ 506 ide_hwif_t *hwif = drive->hwif; 507 struct ide_io_ports *io_ports = &hwif->io_ports; 508 struct ide_taskfile *tf = &cmd->tf; 509 510 if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) { 511 u16 data; 512 513 /* no endian swap */ 514 data = __raw_readw((void __iomem *)io_ports->data_addr); 515 tf->data = data & 0xff; 516 tf->hob_data = (data >> 8) & 0xff; 517 } 518 519 /* be sure we're looking at the low order bits */ 520 tx4939ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); 521 522 if (cmd->tf_flags & IDE_TFLAG_IN_FEATURE) 523 tf->feature = tx4939ide_inb(io_ports->feature_addr); 524 if (cmd->tf_flags & IDE_TFLAG_IN_NSECT) 525 tf->nsect = tx4939ide_inb(io_ports->nsect_addr); 526 if (cmd->tf_flags & IDE_TFLAG_IN_LBAL) 527 tf->lbal = tx4939ide_inb(io_ports->lbal_addr); 528 if (cmd->tf_flags & IDE_TFLAG_IN_LBAM) 529 tf->lbam = tx4939ide_inb(io_ports->lbam_addr); 530 if (cmd->tf_flags & IDE_TFLAG_IN_LBAH) 531 tf->lbah = tx4939ide_inb(io_ports->lbah_addr); 532 if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE) 533 tf->device = tx4939ide_inb(io_ports->device_addr); 534 535 if (cmd->tf_flags & IDE_TFLAG_LBA48) { 536 tx4939ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr); 537 538 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_FEATURE) 539 tf->hob_feature = 540 tx4939ide_inb(io_ports->feature_addr); 541 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT) 542 tf->hob_nsect = tx4939ide_inb(io_ports->nsect_addr); 543 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL) 544 tf->hob_lbal = tx4939ide_inb(io_ports->lbal_addr); 545 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM) 546 tf->hob_lbam = tx4939ide_inb(io_ports->lbam_addr); 547 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH) 548 tf->hob_lbah = tx4939ide_inb(io_ports->lbah_addr); 549 } 550} 551 552static void tx4939ide_input_data_swap(ide_drive_t *drive, struct request *rq, 553 void *buf, unsigned int len) 554{ 555 unsigned long port = drive->hwif->io_ports.data_addr; 556 unsigned short *ptr = buf; 557 unsigned int count = (len + 1) / 2; 558 559 while (count--) 560 *ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port)); 561 __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2)); 562} 563 564static void tx4939ide_output_data_swap(ide_drive_t *drive, struct request *rq, 565 void *buf, unsigned int len) 566{ 567 unsigned long port = drive->hwif->io_ports.data_addr; 568 unsigned short *ptr = buf; 569 unsigned int count = (len + 1) / 2; 570 571 while (count--) { 572 __raw_writew(le16_to_cpu(*ptr), (void __iomem *)port); 573 ptr++; 574 } 575 __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2)); 576} 577 578static const struct ide_tp_ops tx4939ide_tp_ops = { 579 .exec_command = ide_exec_command, 580 .read_status = ide_read_status, 581 .read_altstatus = ide_read_altstatus, 582 583 .set_irq = ide_set_irq, 584 585 .tf_load = tx4939ide_tf_load, 586 .tf_read = tx4939ide_tf_read, 587 588 .input_data = tx4939ide_input_data_swap, 589 .output_data = tx4939ide_output_data_swap, 590}; 591 592#else /* __LITTLE_ENDIAN */ 593 594static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_cmd *cmd) 595{ 596 ide_tf_load(drive, cmd); 597 598 if (cmd->tf_flags & IDE_TFLAG_OUT_DEVICE) 599 tx4939ide_tf_load_fixup(drive); 600} 601 602static const struct ide_tp_ops tx4939ide_tp_ops = { 603 .exec_command = ide_exec_command, 604 .read_status = ide_read_status, 605 .read_altstatus = ide_read_altstatus, 606 607 .set_irq = ide_set_irq, 608 609 .tf_load = tx4939ide_tf_load, 610 .tf_read = ide_tf_read, 611 612 .input_data = ide_input_data, 613 .output_data = ide_output_data, 614}; 615 616#endif /* __LITTLE_ENDIAN */ 617 618static const struct ide_port_ops tx4939ide_port_ops = { 619 .set_pio_mode = tx4939ide_set_pio_mode, 620 .set_dma_mode = tx4939ide_set_dma_mode, 621 .clear_irq = tx4939ide_clear_irq, 622 .cable_detect = tx4939ide_cable_detect, 623}; 624 625static const struct ide_dma_ops tx4939ide_dma_ops = { 626 .dma_host_set = tx4939ide_dma_host_set, 627 .dma_setup = tx4939ide_dma_setup, 628 .dma_start = ide_dma_start, 629 .dma_end = tx4939ide_dma_end, 630 .dma_test_irq = tx4939ide_dma_test_irq, 631 .dma_lost_irq = ide_dma_lost_irq, 632 .dma_timer_expiry = ide_dma_sff_timer_expiry, 633 .dma_sff_read_status = tx4939ide_dma_sff_read_status, 634}; 635 636static const struct ide_port_info tx4939ide_port_info __initdata = { 637 .init_hwif = tx4939ide_init_hwif, 638 .init_dma = tx4939ide_init_dma, 639 .port_ops = &tx4939ide_port_ops, 640 .dma_ops = &tx4939ide_dma_ops, 641 .tp_ops = &tx4939ide_tp_ops, 642 .host_flags = IDE_HFLAG_MMIO, 643 .pio_mask = ATA_PIO4, 644 .mwdma_mask = ATA_MWDMA2, 645 .udma_mask = ATA_UDMA5, 646 .chipset = ide_generic, 647}; 648 649static int __init tx4939ide_probe(struct platform_device *pdev) 650{ 651 hw_regs_t hw; 652 hw_regs_t *hws[] = { &hw, NULL, NULL, NULL }; 653 struct ide_host *host; 654 struct resource *res; 655 int irq, ret; 656 unsigned long mapbase; 657 658 irq = platform_get_irq(pdev, 0); 659 if (irq < 0) 660 return -ENODEV; 661 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 662 if (!res) 663 return -ENODEV; 664 665 if (!devm_request_mem_region(&pdev->dev, res->start, 666 res->end - res->start + 1, "tx4938ide")) 667 return -EBUSY; 668 mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start, 669 res->end - res->start + 1); 670 if (!mapbase) 671 return -EBUSY; 672 memset(&hw, 0, sizeof(hw)); 673 hw.io_ports.data_addr = 674 mapbase + tx4939ide_swizzlew(TX4939IDE_Data); 675 hw.io_ports.error_addr = 676 mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature); 677 hw.io_ports.nsect_addr = 678 mapbase + tx4939ide_swizzleb(TX4939IDE_Sec); 679 hw.io_ports.lbal_addr = 680 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0); 681 hw.io_ports.lbam_addr = 682 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1); 683 hw.io_ports.lbah_addr = 684 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2); 685 hw.io_ports.device_addr = 686 mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead); 687 hw.io_ports.command_addr = 688 mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd); 689 hw.io_ports.ctl_addr = 690 mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl); 691 hw.irq = irq; 692 hw.dev = &pdev->dev; 693 694 pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq); 695 host = ide_host_alloc(&tx4939ide_port_info, hws); 696 if (!host) 697 return -ENOMEM; 698 /* use extra_base for base address of the all registers */ 699 host->ports[0]->extra_base = mapbase; 700 ret = ide_host_register(host, &tx4939ide_port_info, hws); 701 if (ret) { 702 ide_host_free(host); 703 return ret; 704 } 705 platform_set_drvdata(pdev, host); 706 return 0; 707} 708 709static int __exit tx4939ide_remove(struct platform_device *pdev) 710{ 711 struct ide_host *host = platform_get_drvdata(pdev); 712 713 ide_host_remove(host); 714 return 0; 715} 716 717#ifdef CONFIG_PM 718static int tx4939ide_resume(struct platform_device *dev) 719{ 720 struct ide_host *host = platform_get_drvdata(dev); 721 ide_hwif_t *hwif = host->ports[0]; 722 723 tx4939ide_init_hwif(hwif); 724 return 0; 725} 726#else 727#define tx4939ide_resume NULL 728#endif 729 730static struct platform_driver tx4939ide_driver = { 731 .driver = { 732 .name = MODNAME, 733 .owner = THIS_MODULE, 734 }, 735 .remove = __exit_p(tx4939ide_remove), 736 .resume = tx4939ide_resume, 737}; 738 739static int __init tx4939ide_init(void) 740{ 741 return platform_driver_probe(&tx4939ide_driver, tx4939ide_probe); 742} 743 744static void __exit tx4939ide_exit(void) 745{ 746 platform_driver_unregister(&tx4939ide_driver); 747} 748 749module_init(tx4939ide_init); 750module_exit(tx4939ide_exit); 751 752MODULE_DESCRIPTION("TX4939 internal IDE driver"); 753MODULE_LICENSE("GPL"); 754MODULE_ALIAS("platform:tx4939ide"); 755