via82cxxx.c revision e085b3cae85af47eb0a3eda3186bd898310fb322
1/* 2 * VIA IDE driver for Linux. Supported southbridges: 3 * 4 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, 5 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, 6 * vt8235, vt8237, vt8237a 7 * 8 * Copyright (c) 2000-2002 Vojtech Pavlik 9 * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz 10 * 11 * Based on the work of: 12 * Michel Aubry 13 * Jeff Garzik 14 * Andre Hedrick 15 * 16 * Documentation: 17 * Obsolete device documentation publically available from via.com.tw 18 * Current device documentation available under NDA only 19 */ 20 21/* 22 * This program is free software; you can redistribute it and/or modify it 23 * under the terms of the GNU General Public License version 2 as published by 24 * the Free Software Foundation. 25 */ 26 27#include <linux/module.h> 28#include <linux/kernel.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/ide.h> 32#include <linux/dmi.h> 33 34#ifdef CONFIG_PPC_CHRP 35#include <asm/processor.h> 36#endif 37 38#define DRV_NAME "via82cxxx" 39 40#define VIA_IDE_ENABLE 0x40 41#define VIA_IDE_CONFIG 0x41 42#define VIA_FIFO_CONFIG 0x43 43#define VIA_MISC_1 0x44 44#define VIA_MISC_2 0x45 45#define VIA_MISC_3 0x46 46#define VIA_DRIVE_TIMING 0x48 47#define VIA_8BIT_TIMING 0x4e 48#define VIA_ADDRESS_SETUP 0x4c 49#define VIA_UDMA_TIMING 0x50 50 51#define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */ 52#define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */ 53#define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */ 54#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */ 55#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */ 56#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */ 57#define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */ 58 59enum { 60 VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */ 61}; 62 63/* 64 * VIA SouthBridge chips. 65 */ 66 67static struct via_isa_bridge { 68 char *name; 69 u16 id; 70 u8 rev_min; 71 u8 rev_max; 72 u8 udma_mask; 73 u8 flags; 74} via_isa_bridges[] = { 75 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, 76 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, 77 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, 78 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 79 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 80 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 81 { "vt6415", PCI_DEVICE_ID_VIA_6410, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST }, 82 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 83 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 84 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 85 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 86 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 87 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, }, 88 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, }, 89 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, }, 90 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, }, 91 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, }, 92 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, 93 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, }, 94 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, 95 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO }, 96 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ }, 97 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO }, 98 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO }, 99 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, 100 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, 101 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, 102 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 103 { NULL } 104}; 105 106static unsigned int via_clock; 107static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; 108 109struct via82cxxx_dev 110{ 111 struct via_isa_bridge *via_config; 112 unsigned int via_80w; 113 u8 cached_device[2]; 114}; 115 116/** 117 * via_set_speed - write timing registers 118 * @dev: PCI device 119 * @dn: device 120 * @timing: IDE timing data to use 121 * 122 * via_set_speed writes timing values to the chipset registers 123 */ 124 125static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) 126{ 127 struct pci_dev *dev = to_pci_dev(hwif->dev); 128 struct ide_host *host = pci_get_drvdata(dev); 129 struct via82cxxx_dev *vdev = host->host_priv; 130 u8 t; 131 132 if (~vdev->via_config->flags & VIA_BAD_AST) { 133 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t); 134 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); 135 pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t); 136 } 137 138 pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)), 139 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); 140 141 pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn), 142 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); 143 144 switch (vdev->via_config->udma_mask) { 145 case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; 146 case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; 147 case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; 148 case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; 149 } 150 151 /* Set UDMA unless device is not UDMA capable */ 152 if (vdev->via_config->udma_mask) { 153 u8 udma_etc; 154 155 pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc); 156 157 /* clear transfer mode bit */ 158 udma_etc &= ~0x20; 159 160 if (timing->udma) { 161 /* preserve 80-wire cable detection bit */ 162 udma_etc &= 0x10; 163 udma_etc |= t; 164 } 165 166 pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc); 167 } 168} 169 170/** 171 * via_set_drive - configure transfer mode 172 * @drive: Drive to set up 173 * @speed: desired speed 174 * 175 * via_set_drive() computes timing values configures the chipset to 176 * a desired transfer mode. It also can be called by upper layers. 177 */ 178 179static void via_set_drive(ide_drive_t *drive, const u8 speed) 180{ 181 ide_hwif_t *hwif = drive->hwif; 182 ide_drive_t *peer = ide_get_pair_dev(drive); 183 struct pci_dev *dev = to_pci_dev(hwif->dev); 184 struct ide_host *host = pci_get_drvdata(dev); 185 struct via82cxxx_dev *vdev = host->host_priv; 186 struct ide_timing t, p; 187 unsigned int T, UT; 188 189 T = 1000000000 / via_clock; 190 191 switch (vdev->via_config->udma_mask) { 192 case ATA_UDMA2: UT = T; break; 193 case ATA_UDMA4: UT = T/2; break; 194 case ATA_UDMA5: UT = T/3; break; 195 case ATA_UDMA6: UT = T/4; break; 196 default: UT = T; 197 } 198 199 ide_timing_compute(drive, speed, &t, T, UT); 200 201 if (peer) { 202 ide_timing_compute(peer, peer->current_speed, &p, T, UT); 203 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); 204 } 205 206 via_set_speed(hwif, drive->dn, &t); 207} 208 209/** 210 * via_set_pio_mode - set host controller for PIO mode 211 * @hwif: port 212 * @drive: drive 213 * 214 * A callback from the upper layers for PIO-only tuning. 215 */ 216 217static void via_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 218{ 219 via_set_drive(drive, drive->pio_mode); 220} 221 222static struct via_isa_bridge *via_config_find(struct pci_dev **isa) 223{ 224 struct via_isa_bridge *via_config; 225 226 for (via_config = via_isa_bridges; 227 via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++) 228 if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA + 229 !!(via_config->flags & VIA_BAD_ID), 230 via_config->id, NULL))) { 231 232 if ((*isa)->revision >= via_config->rev_min && 233 (*isa)->revision <= via_config->rev_max) 234 break; 235 pci_dev_put(*isa); 236 } 237 238 return via_config; 239} 240 241/* 242 * Check and handle 80-wire cable presence 243 */ 244static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u) 245{ 246 int i; 247 248 switch (vdev->via_config->udma_mask) { 249 case ATA_UDMA4: 250 for (i = 24; i >= 0; i -= 8) 251 if (((u >> (i & 16)) & 8) && 252 ((u >> i) & 0x20) && 253 (((u >> i) & 7) < 2)) { 254 /* 255 * 2x PCI clock and 256 * UDMA w/ < 3T/cycle 257 */ 258 vdev->via_80w |= (1 << (1 - (i >> 4))); 259 } 260 break; 261 262 case ATA_UDMA5: 263 for (i = 24; i >= 0; i -= 8) 264 if (((u >> i) & 0x10) || 265 (((u >> i) & 0x20) && 266 (((u >> i) & 7) < 4))) { 267 /* BIOS 80-wire bit or 268 * UDMA w/ < 60ns/cycle 269 */ 270 vdev->via_80w |= (1 << (1 - (i >> 4))); 271 } 272 break; 273 274 case ATA_UDMA6: 275 for (i = 24; i >= 0; i -= 8) 276 if (((u >> i) & 0x10) || 277 (((u >> i) & 0x20) && 278 (((u >> i) & 7) < 6))) { 279 /* BIOS 80-wire bit or 280 * UDMA w/ < 60ns/cycle 281 */ 282 vdev->via_80w |= (1 << (1 - (i >> 4))); 283 } 284 break; 285 } 286} 287 288/** 289 * init_chipset_via82cxxx - initialization handler 290 * @dev: PCI device 291 * 292 * The initialization callback. Here we determine the IDE chip type 293 * and initialize its drive independent registers. 294 */ 295 296static int init_chipset_via82cxxx(struct pci_dev *dev) 297{ 298 struct ide_host *host = pci_get_drvdata(dev); 299 struct via82cxxx_dev *vdev = host->host_priv; 300 struct via_isa_bridge *via_config = vdev->via_config; 301 u8 t, v; 302 u32 u; 303 304 /* 305 * Detect cable and configure Clk66 306 */ 307 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); 308 309 via_cable_detect(vdev, u); 310 311 if (via_config->udma_mask == ATA_UDMA4) { 312 /* Enable Clk66 */ 313 pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008); 314 } else if (via_config->flags & VIA_BAD_CLK66) { 315 /* Would cause trouble on 596a and 686 */ 316 pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008); 317 } 318 319 /* 320 * Check whether interfaces are enabled. 321 */ 322 323 pci_read_config_byte(dev, VIA_IDE_ENABLE, &v); 324 325 /* 326 * Set up FIFO sizes and thresholds. 327 */ 328 329 pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t); 330 331 /* Disable PREQ# till DDACK# */ 332 if (via_config->flags & VIA_BAD_PREQ) { 333 /* Would crash on 586b rev 41 */ 334 t &= 0x7f; 335 } 336 337 /* Fix FIFO split between channels */ 338 if (via_config->flags & VIA_SET_FIFO) { 339 t &= (t & 0x9f); 340 switch (v & 3) { 341 case 2: t |= 0x00; break; /* 16 on primary */ 342 case 1: t |= 0x60; break; /* 16 on secondary */ 343 case 3: t |= 0x20; break; /* 8 pri 8 sec */ 344 } 345 } 346 347 pci_write_config_byte(dev, VIA_FIFO_CONFIG, t); 348 349 return 0; 350} 351 352/* 353 * Cable special cases 354 */ 355 356static const struct dmi_system_id cable_dmi_table[] = { 357 { 358 .ident = "Acer Ferrari 3400", 359 .matches = { 360 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), 361 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), 362 }, 363 }, 364 { } 365}; 366 367static int via_cable_override(struct pci_dev *pdev) 368{ 369 /* Systems by DMI */ 370 if (dmi_check_system(cable_dmi_table)) 371 return 1; 372 373 /* Arima W730-K8/Targa Visionary 811/... */ 374 if (pdev->subsystem_vendor == 0x161F && 375 pdev->subsystem_device == 0x2032) 376 return 1; 377 378 return 0; 379} 380 381static u8 via82cxxx_cable_detect(ide_hwif_t *hwif) 382{ 383 struct pci_dev *pdev = to_pci_dev(hwif->dev); 384 struct ide_host *host = pci_get_drvdata(pdev); 385 struct via82cxxx_dev *vdev = host->host_priv; 386 387 if (via_cable_override(pdev)) 388 return ATA_CBL_PATA40_SHORT; 389 390 if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0) 391 return ATA_CBL_SATA; 392 393 if ((vdev->via_80w >> hwif->channel) & 1) 394 return ATA_CBL_PATA80; 395 else 396 return ATA_CBL_PATA40; 397} 398 399static const struct ide_port_ops via_port_ops = { 400 .set_pio_mode = via_set_pio_mode, 401 .set_dma_mode = via_set_drive, 402 .cable_detect = via82cxxx_cable_detect, 403}; 404 405static void via_write_devctl(ide_hwif_t *hwif, u8 ctl) 406{ 407 struct via82cxxx_dev *vdev = hwif->host->host_priv; 408 409 outb(ctl, hwif->io_ports.ctl_addr); 410 outb(vdev->cached_device[hwif->channel], hwif->io_ports.device_addr); 411} 412 413static void __via_dev_select(ide_drive_t *drive, u8 select) 414{ 415 ide_hwif_t *hwif = drive->hwif; 416 struct via82cxxx_dev *vdev = hwif->host->host_priv; 417 418 outb(select, hwif->io_ports.device_addr); 419 vdev->cached_device[hwif->channel] = select; 420} 421 422static void via_dev_select(ide_drive_t *drive) 423{ 424 __via_dev_select(drive, drive->select | ATA_DEVICE_OBS); 425} 426 427static void via_tf_load(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid) 428{ 429 ide_hwif_t *hwif = drive->hwif; 430 struct ide_io_ports *io_ports = &hwif->io_ports; 431 432 if (valid & IDE_VALID_FEATURE) 433 outb(tf->feature, io_ports->feature_addr); 434 if (valid & IDE_VALID_NSECT) 435 outb(tf->nsect, io_ports->nsect_addr); 436 if (valid & IDE_VALID_LBAL) 437 outb(tf->lbal, io_ports->lbal_addr); 438 if (valid & IDE_VALID_LBAM) 439 outb(tf->lbam, io_ports->lbam_addr); 440 if (valid & IDE_VALID_LBAH) 441 outb(tf->lbah, io_ports->lbah_addr); 442 if (valid & IDE_VALID_DEVICE) 443 __via_dev_select(drive, tf->device); 444} 445 446const struct ide_tp_ops via_tp_ops = { 447 .exec_command = ide_exec_command, 448 .read_status = ide_read_status, 449 .read_altstatus = ide_read_altstatus, 450 .write_devctl = via_write_devctl, 451 452 .dev_select = via_dev_select, 453 .tf_load = via_tf_load, 454 .tf_read = ide_tf_read, 455 456 .input_data = ide_input_data, 457 .output_data = ide_output_data, 458}; 459 460static const struct ide_port_info via82cxxx_chipset __devinitdata = { 461 .name = DRV_NAME, 462 .init_chipset = init_chipset_via82cxxx, 463 .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, 464 .tp_ops = &via_tp_ops, 465 .port_ops = &via_port_ops, 466 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | 467 IDE_HFLAG_POST_SET_MODE | 468 IDE_HFLAG_IO_32BIT, 469 .pio_mask = ATA_PIO5, 470 .swdma_mask = ATA_SWDMA2, 471 .mwdma_mask = ATA_MWDMA2, 472}; 473 474static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id) 475{ 476 struct pci_dev *isa = NULL; 477 struct via_isa_bridge *via_config; 478 struct via82cxxx_dev *vdev; 479 int rc; 480 u8 idx = id->driver_data; 481 struct ide_port_info d; 482 483 d = via82cxxx_chipset; 484 485 /* 486 * Find the ISA bridge and check we know what it is. 487 */ 488 via_config = via_config_find(&isa); 489 490 /* 491 * Print the boot message. 492 */ 493 printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n", 494 pci_name(dev), via_config->name, isa->revision, 495 via_config->udma_mask ? "U" : "MW", 496 via_dma[via_config->udma_mask ? 497 (fls(via_config->udma_mask) - 1) : 0]); 498 499 pci_dev_put(isa); 500 501 /* 502 * Determine system bus clock. 503 */ 504 via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000; 505 506 switch (via_clock) { 507 case 33000: via_clock = 33333; break; 508 case 37000: via_clock = 37500; break; 509 case 41000: via_clock = 41666; break; 510 } 511 512 if (via_clock < 20000 || via_clock > 50000) { 513 printk(KERN_WARNING DRV_NAME ": User given PCI clock speed " 514 "impossible (%d), using 33 MHz instead.\n", via_clock); 515 via_clock = 33333; 516 } 517 518 if (idx == 1) 519 d.enablebits[1].reg = d.enablebits[0].reg = 0; 520 else 521 d.host_flags |= IDE_HFLAG_NO_AUTODMA; 522 523 if (idx == VIA_IDFLAG_SINGLE) 524 d.host_flags |= IDE_HFLAG_SINGLE; 525 526 if ((via_config->flags & VIA_NO_UNMASK) == 0) 527 d.host_flags |= IDE_HFLAG_UNMASK_IRQS; 528 529 d.udma_mask = via_config->udma_mask; 530 531 vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); 532 if (!vdev) { 533 printk(KERN_ERR DRV_NAME " %s: out of memory :(\n", 534 pci_name(dev)); 535 return -ENOMEM; 536 } 537 538 vdev->via_config = via_config; 539 540 rc = ide_pci_init_one(dev, &d, vdev); 541 if (rc) 542 kfree(vdev); 543 544 return rc; 545} 546 547static void __devexit via_remove(struct pci_dev *dev) 548{ 549 struct ide_host *host = pci_get_drvdata(dev); 550 struct via82cxxx_dev *vdev = host->host_priv; 551 552 ide_pci_remove(dev); 553 kfree(vdev); 554} 555 556static const struct pci_device_id via_pci_tbl[] = { 557 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 }, 558 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 }, 559 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 }, 560 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE }, 561 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 }, 562 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415), 1 }, 563 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 }, 564 { 0, }, 565}; 566MODULE_DEVICE_TABLE(pci, via_pci_tbl); 567 568static struct pci_driver via_pci_driver = { 569 .name = "VIA_IDE", 570 .id_table = via_pci_tbl, 571 .probe = via_init_one, 572 .remove = __devexit_p(via_remove), 573 .suspend = ide_pci_suspend, 574 .resume = ide_pci_resume, 575}; 576 577static int __init via_ide_init(void) 578{ 579 return ide_pci_register_driver(&via_pci_driver); 580} 581 582static void __exit via_ide_exit(void) 583{ 584 pci_unregister_driver(&via_pci_driver); 585} 586 587module_init(via_ide_init); 588module_exit(via_ide_exit); 589 590MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick"); 591MODULE_DESCRIPTION("PCI driver module for VIA IDE"); 592MODULE_LICENSE("GPL"); 593