1/* 2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips: 3 * - BMC150 4 * - BMI055 5 * - BMA255 6 * - BMA250E 7 * - BMA222E 8 * - BMA280 9 * 10 * Copyright (c) 2014, Intel Corporation. 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms and conditions of the GNU General Public License, 14 * version 2, as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 */ 21 22#include <linux/module.h> 23#include <linux/i2c.h> 24#include <linux/interrupt.h> 25#include <linux/delay.h> 26#include <linux/slab.h> 27#include <linux/acpi.h> 28#include <linux/gpio/consumer.h> 29#include <linux/pm.h> 30#include <linux/pm_runtime.h> 31#include <linux/iio/iio.h> 32#include <linux/iio/sysfs.h> 33#include <linux/iio/buffer.h> 34#include <linux/iio/events.h> 35#include <linux/iio/trigger.h> 36#include <linux/iio/trigger_consumer.h> 37#include <linux/iio/triggered_buffer.h> 38 39#define BMC150_ACCEL_DRV_NAME "bmc150_accel" 40#define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event" 41#define BMC150_ACCEL_GPIO_NAME "bmc150_accel_int" 42 43#define BMC150_ACCEL_REG_CHIP_ID 0x00 44 45#define BMC150_ACCEL_REG_INT_STATUS_2 0x0B 46#define BMC150_ACCEL_ANY_MOTION_MASK 0x07 47#define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0) 48#define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1) 49#define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2) 50#define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3) 51 52#define BMC150_ACCEL_REG_PMU_LPW 0x11 53#define BMC150_ACCEL_PMU_MODE_MASK 0xE0 54#define BMC150_ACCEL_PMU_MODE_SHIFT 5 55#define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17 56#define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1 57 58#define BMC150_ACCEL_REG_PMU_RANGE 0x0F 59 60#define BMC150_ACCEL_DEF_RANGE_2G 0x03 61#define BMC150_ACCEL_DEF_RANGE_4G 0x05 62#define BMC150_ACCEL_DEF_RANGE_8G 0x08 63#define BMC150_ACCEL_DEF_RANGE_16G 0x0C 64 65/* Default BW: 125Hz */ 66#define BMC150_ACCEL_REG_PMU_BW 0x10 67#define BMC150_ACCEL_DEF_BW 125 68 69#define BMC150_ACCEL_REG_INT_MAP_0 0x19 70#define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) 71 72#define BMC150_ACCEL_REG_INT_MAP_1 0x1A 73#define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) 74 75#define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 76#define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 77#define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F 78#define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00 79 80#define BMC150_ACCEL_REG_INT_EN_0 0x16 81#define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0) 82#define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1) 83#define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) 84 85#define BMC150_ACCEL_REG_INT_EN_1 0x17 86#define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) 87 88#define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 89#define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) 90 91#define BMC150_ACCEL_REG_INT_5 0x27 92#define BMC150_ACCEL_SLOPE_DUR_MASK 0x03 93 94#define BMC150_ACCEL_REG_INT_6 0x28 95#define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF 96 97/* Slope duration in terms of number of samples */ 98#define BMC150_ACCEL_DEF_SLOPE_DURATION 1 99/* in terms of multiples of g's/LSB, based on range */ 100#define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1 101 102#define BMC150_ACCEL_REG_XOUT_L 0x02 103 104#define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100 105 106/* Sleep Duration values */ 107#define BMC150_ACCEL_SLEEP_500_MICRO 0x05 108#define BMC150_ACCEL_SLEEP_1_MS 0x06 109#define BMC150_ACCEL_SLEEP_2_MS 0x07 110#define BMC150_ACCEL_SLEEP_4_MS 0x08 111#define BMC150_ACCEL_SLEEP_6_MS 0x09 112#define BMC150_ACCEL_SLEEP_10_MS 0x0A 113#define BMC150_ACCEL_SLEEP_25_MS 0x0B 114#define BMC150_ACCEL_SLEEP_50_MS 0x0C 115#define BMC150_ACCEL_SLEEP_100_MS 0x0D 116#define BMC150_ACCEL_SLEEP_500_MS 0x0E 117#define BMC150_ACCEL_SLEEP_1_SEC 0x0F 118 119#define BMC150_ACCEL_REG_TEMP 0x08 120#define BMC150_ACCEL_TEMP_CENTER_VAL 24 121 122#define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) 123#define BMC150_AUTO_SUSPEND_DELAY_MS 2000 124 125enum bmc150_accel_axis { 126 AXIS_X, 127 AXIS_Y, 128 AXIS_Z, 129}; 130 131enum bmc150_power_modes { 132 BMC150_ACCEL_SLEEP_MODE_NORMAL, 133 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 134 BMC150_ACCEL_SLEEP_MODE_LPM, 135 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04, 136}; 137 138struct bmc150_scale_info { 139 int scale; 140 u8 reg_range; 141}; 142 143struct bmc150_accel_chip_info { 144 u8 chip_id; 145 const struct iio_chan_spec *channels; 146 int num_channels; 147 const struct bmc150_scale_info scale_table[4]; 148}; 149 150struct bmc150_accel_data { 151 struct i2c_client *client; 152 struct iio_trigger *dready_trig; 153 struct iio_trigger *motion_trig; 154 struct mutex mutex; 155 s16 buffer[8]; 156 u8 bw_bits; 157 u32 slope_dur; 158 u32 slope_thres; 159 u32 range; 160 int ev_enable_state; 161 bool dready_trigger_on; 162 bool motion_trigger_on; 163 int64_t timestamp; 164 const struct bmc150_accel_chip_info *chip_info; 165}; 166 167static const struct { 168 int val; 169 int val2; 170 u8 bw_bits; 171} bmc150_accel_samp_freq_table[] = { {7, 810000, 0x08}, 172 {15, 630000, 0x09}, 173 {31, 250000, 0x0A}, 174 {62, 500000, 0x0B}, 175 {125, 0, 0x0C}, 176 {250, 0, 0x0D}, 177 {500, 0, 0x0E}, 178 {1000, 0, 0x0F} }; 179 180static const struct { 181 int bw_bits; 182 int msec; 183} bmc150_accel_sample_upd_time[] = { {0x08, 64}, 184 {0x09, 32}, 185 {0x0A, 16}, 186 {0x0B, 8}, 187 {0x0C, 4}, 188 {0x0D, 2}, 189 {0x0E, 1}, 190 {0x0F, 1} }; 191 192static const struct { 193 int sleep_dur; 194 u8 reg_value; 195} bmc150_accel_sleep_value_table[] = { {0, 0}, 196 {500, BMC150_ACCEL_SLEEP_500_MICRO}, 197 {1000, BMC150_ACCEL_SLEEP_1_MS}, 198 {2000, BMC150_ACCEL_SLEEP_2_MS}, 199 {4000, BMC150_ACCEL_SLEEP_4_MS}, 200 {6000, BMC150_ACCEL_SLEEP_6_MS}, 201 {10000, BMC150_ACCEL_SLEEP_10_MS}, 202 {25000, BMC150_ACCEL_SLEEP_25_MS}, 203 {50000, BMC150_ACCEL_SLEEP_50_MS}, 204 {100000, BMC150_ACCEL_SLEEP_100_MS}, 205 {500000, BMC150_ACCEL_SLEEP_500_MS}, 206 {1000000, BMC150_ACCEL_SLEEP_1_SEC} }; 207 208 209static int bmc150_accel_set_mode(struct bmc150_accel_data *data, 210 enum bmc150_power_modes mode, 211 int dur_us) 212{ 213 int i; 214 int ret; 215 u8 lpw_bits; 216 int dur_val = -1; 217 218 if (dur_us > 0) { 219 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table); 220 ++i) { 221 if (bmc150_accel_sleep_value_table[i].sleep_dur == 222 dur_us) 223 dur_val = 224 bmc150_accel_sleep_value_table[i].reg_value; 225 } 226 } else 227 dur_val = 0; 228 229 if (dur_val < 0) 230 return -EINVAL; 231 232 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT; 233 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT); 234 235 dev_dbg(&data->client->dev, "Set Mode bits %x\n", lpw_bits); 236 237 ret = i2c_smbus_write_byte_data(data->client, 238 BMC150_ACCEL_REG_PMU_LPW, lpw_bits); 239 if (ret < 0) { 240 dev_err(&data->client->dev, "Error writing reg_pmu_lpw\n"); 241 return ret; 242 } 243 244 return 0; 245} 246 247static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, 248 int val2) 249{ 250 int i; 251 int ret; 252 253 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 254 if (bmc150_accel_samp_freq_table[i].val == val && 255 bmc150_accel_samp_freq_table[i].val2 == val2) { 256 ret = i2c_smbus_write_byte_data( 257 data->client, 258 BMC150_ACCEL_REG_PMU_BW, 259 bmc150_accel_samp_freq_table[i].bw_bits); 260 if (ret < 0) 261 return ret; 262 263 data->bw_bits = 264 bmc150_accel_samp_freq_table[i].bw_bits; 265 return 0; 266 } 267 } 268 269 return -EINVAL; 270} 271 272static int bmc150_accel_chip_init(struct bmc150_accel_data *data) 273{ 274 int ret; 275 276 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_CHIP_ID); 277 if (ret < 0) { 278 dev_err(&data->client->dev, 279 "Error: Reading chip id\n"); 280 return ret; 281 } 282 283 dev_dbg(&data->client->dev, "Chip Id %x\n", ret); 284 if (ret != data->chip_info->chip_id) { 285 dev_err(&data->client->dev, "Invalid chip %x\n", ret); 286 return -ENODEV; 287 } 288 289 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 290 if (ret < 0) 291 return ret; 292 293 /* Set Bandwidth */ 294 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0); 295 if (ret < 0) 296 return ret; 297 298 /* Set Default Range */ 299 ret = i2c_smbus_write_byte_data(data->client, 300 BMC150_ACCEL_REG_PMU_RANGE, 301 BMC150_ACCEL_DEF_RANGE_4G); 302 if (ret < 0) { 303 dev_err(&data->client->dev, 304 "Error writing reg_pmu_range\n"); 305 return ret; 306 } 307 308 data->range = BMC150_ACCEL_DEF_RANGE_4G; 309 310 /* Set default slope duration */ 311 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_INT_5); 312 if (ret < 0) { 313 dev_err(&data->client->dev, "Error reading reg_int_5\n"); 314 return ret; 315 } 316 data->slope_dur |= BMC150_ACCEL_DEF_SLOPE_DURATION; 317 ret = i2c_smbus_write_byte_data(data->client, 318 BMC150_ACCEL_REG_INT_5, 319 data->slope_dur); 320 if (ret < 0) { 321 dev_err(&data->client->dev, "Error writing reg_int_5\n"); 322 return ret; 323 } 324 dev_dbg(&data->client->dev, "slope_dur %x\n", data->slope_dur); 325 326 /* Set default slope thresholds */ 327 ret = i2c_smbus_write_byte_data(data->client, 328 BMC150_ACCEL_REG_INT_6, 329 BMC150_ACCEL_DEF_SLOPE_THRESHOLD); 330 if (ret < 0) { 331 dev_err(&data->client->dev, "Error writing reg_int_6\n"); 332 return ret; 333 } 334 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD; 335 dev_dbg(&data->client->dev, "slope_thres %x\n", data->slope_thres); 336 337 /* Set default as latched interrupts */ 338 ret = i2c_smbus_write_byte_data(data->client, 339 BMC150_ACCEL_REG_INT_RST_LATCH, 340 BMC150_ACCEL_INT_MODE_LATCH_INT | 341 BMC150_ACCEL_INT_MODE_LATCH_RESET); 342 if (ret < 0) { 343 dev_err(&data->client->dev, 344 "Error writing reg_int_rst_latch\n"); 345 return ret; 346 } 347 348 return 0; 349} 350 351static int bmc150_accel_setup_any_motion_interrupt( 352 struct bmc150_accel_data *data, 353 bool status) 354{ 355 int ret; 356 357 /* Enable/Disable INT1 mapping */ 358 ret = i2c_smbus_read_byte_data(data->client, 359 BMC150_ACCEL_REG_INT_MAP_0); 360 if (ret < 0) { 361 dev_err(&data->client->dev, "Error reading reg_int_map_0\n"); 362 return ret; 363 } 364 if (status) 365 ret |= BMC150_ACCEL_INT_MAP_0_BIT_SLOPE; 366 else 367 ret &= ~BMC150_ACCEL_INT_MAP_0_BIT_SLOPE; 368 369 ret = i2c_smbus_write_byte_data(data->client, 370 BMC150_ACCEL_REG_INT_MAP_0, 371 ret); 372 if (ret < 0) { 373 dev_err(&data->client->dev, "Error writing reg_int_map_0\n"); 374 return ret; 375 } 376 377 if (status) { 378 /* Set slope duration (no of samples) */ 379 ret = i2c_smbus_write_byte_data(data->client, 380 BMC150_ACCEL_REG_INT_5, 381 data->slope_dur); 382 if (ret < 0) { 383 dev_err(&data->client->dev, "Error write reg_int_5\n"); 384 return ret; 385 } 386 387 /* Set slope thresholds */ 388 ret = i2c_smbus_write_byte_data(data->client, 389 BMC150_ACCEL_REG_INT_6, 390 data->slope_thres); 391 if (ret < 0) { 392 dev_err(&data->client->dev, "Error write reg_int_6\n"); 393 return ret; 394 } 395 396 /* 397 * New data interrupt is always non-latched, 398 * which will have higher priority, so no need 399 * to set latched mode, we will be flooded anyway with INTR 400 */ 401 if (!data->dready_trigger_on) { 402 ret = i2c_smbus_write_byte_data(data->client, 403 BMC150_ACCEL_REG_INT_RST_LATCH, 404 BMC150_ACCEL_INT_MODE_LATCH_INT | 405 BMC150_ACCEL_INT_MODE_LATCH_RESET); 406 if (ret < 0) { 407 dev_err(&data->client->dev, 408 "Error writing reg_int_rst_latch\n"); 409 return ret; 410 } 411 } 412 413 ret = i2c_smbus_write_byte_data(data->client, 414 BMC150_ACCEL_REG_INT_EN_0, 415 BMC150_ACCEL_INT_EN_BIT_SLP_X | 416 BMC150_ACCEL_INT_EN_BIT_SLP_Y | 417 BMC150_ACCEL_INT_EN_BIT_SLP_Z); 418 } else 419 ret = i2c_smbus_write_byte_data(data->client, 420 BMC150_ACCEL_REG_INT_EN_0, 421 0); 422 423 if (ret < 0) { 424 dev_err(&data->client->dev, "Error writing reg_int_en_0\n"); 425 return ret; 426 } 427 428 return 0; 429} 430 431static int bmc150_accel_setup_new_data_interrupt(struct bmc150_accel_data *data, 432 bool status) 433{ 434 int ret; 435 436 /* Enable/Disable INT1 mapping */ 437 ret = i2c_smbus_read_byte_data(data->client, 438 BMC150_ACCEL_REG_INT_MAP_1); 439 if (ret < 0) { 440 dev_err(&data->client->dev, "Error reading reg_int_map_1\n"); 441 return ret; 442 } 443 if (status) 444 ret |= BMC150_ACCEL_INT_MAP_1_BIT_DATA; 445 else 446 ret &= ~BMC150_ACCEL_INT_MAP_1_BIT_DATA; 447 448 ret = i2c_smbus_write_byte_data(data->client, 449 BMC150_ACCEL_REG_INT_MAP_1, 450 ret); 451 if (ret < 0) { 452 dev_err(&data->client->dev, "Error writing reg_int_map_1\n"); 453 return ret; 454 } 455 456 if (status) { 457 /* 458 * Set non latched mode interrupt and clear any latched 459 * interrupt 460 */ 461 ret = i2c_smbus_write_byte_data(data->client, 462 BMC150_ACCEL_REG_INT_RST_LATCH, 463 BMC150_ACCEL_INT_MODE_NON_LATCH_INT | 464 BMC150_ACCEL_INT_MODE_LATCH_RESET); 465 if (ret < 0) { 466 dev_err(&data->client->dev, 467 "Error writing reg_int_rst_latch\n"); 468 return ret; 469 } 470 471 ret = i2c_smbus_write_byte_data(data->client, 472 BMC150_ACCEL_REG_INT_EN_1, 473 BMC150_ACCEL_INT_EN_BIT_DATA_EN); 474 475 } else { 476 /* Restore default interrupt mode */ 477 ret = i2c_smbus_write_byte_data(data->client, 478 BMC150_ACCEL_REG_INT_RST_LATCH, 479 BMC150_ACCEL_INT_MODE_LATCH_INT | 480 BMC150_ACCEL_INT_MODE_LATCH_RESET); 481 if (ret < 0) { 482 dev_err(&data->client->dev, 483 "Error writing reg_int_rst_latch\n"); 484 return ret; 485 } 486 487 ret = i2c_smbus_write_byte_data(data->client, 488 BMC150_ACCEL_REG_INT_EN_1, 489 0); 490 } 491 492 if (ret < 0) { 493 dev_err(&data->client->dev, "Error writing reg_int_en_1\n"); 494 return ret; 495 } 496 497 return 0; 498} 499 500static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val, 501 int *val2) 502{ 503 int i; 504 505 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 506 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) { 507 *val = bmc150_accel_samp_freq_table[i].val; 508 *val2 = bmc150_accel_samp_freq_table[i].val2; 509 return IIO_VAL_INT_PLUS_MICRO; 510 } 511 } 512 513 return -EINVAL; 514} 515 516#ifdef CONFIG_PM_RUNTIME 517static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data) 518{ 519 int i; 520 521 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) { 522 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits) 523 return bmc150_accel_sample_upd_time[i].msec; 524 } 525 526 return BMC150_ACCEL_MAX_STARTUP_TIME_MS; 527} 528 529static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 530{ 531 int ret; 532 533 if (on) 534 ret = pm_runtime_get_sync(&data->client->dev); 535 else { 536 pm_runtime_mark_last_busy(&data->client->dev); 537 ret = pm_runtime_put_autosuspend(&data->client->dev); 538 } 539 if (ret < 0) { 540 dev_err(&data->client->dev, 541 "Failed: bmc150_accel_set_power_state for %d\n", on); 542 if (on) 543 pm_runtime_put_noidle(&data->client->dev); 544 545 return ret; 546 } 547 548 return 0; 549} 550#else 551static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 552{ 553 return 0; 554} 555#endif 556 557static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) 558{ 559 int ret, i; 560 561 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) { 562 if (data->chip_info->scale_table[i].scale == val) { 563 ret = i2c_smbus_write_byte_data( 564 data->client, 565 BMC150_ACCEL_REG_PMU_RANGE, 566 data->chip_info->scale_table[i].reg_range); 567 if (ret < 0) { 568 dev_err(&data->client->dev, 569 "Error writing pmu_range\n"); 570 return ret; 571 } 572 573 data->range = data->chip_info->scale_table[i].reg_range; 574 return 0; 575 } 576 } 577 578 return -EINVAL; 579} 580 581static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val) 582{ 583 int ret; 584 585 mutex_lock(&data->mutex); 586 587 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_TEMP); 588 if (ret < 0) { 589 dev_err(&data->client->dev, "Error reading reg_temp\n"); 590 mutex_unlock(&data->mutex); 591 return ret; 592 } 593 *val = sign_extend32(ret, 7); 594 595 mutex_unlock(&data->mutex); 596 597 return IIO_VAL_INT; 598} 599 600static int bmc150_accel_get_axis(struct bmc150_accel_data *data, 601 struct iio_chan_spec const *chan, 602 int *val) 603{ 604 int ret; 605 int axis = chan->scan_index; 606 607 mutex_lock(&data->mutex); 608 ret = bmc150_accel_set_power_state(data, true); 609 if (ret < 0) { 610 mutex_unlock(&data->mutex); 611 return ret; 612 } 613 614 ret = i2c_smbus_read_word_data(data->client, 615 BMC150_ACCEL_AXIS_TO_REG(axis)); 616 if (ret < 0) { 617 dev_err(&data->client->dev, "Error reading axis %d\n", axis); 618 bmc150_accel_set_power_state(data, false); 619 mutex_unlock(&data->mutex); 620 return ret; 621 } 622 *val = sign_extend32(ret >> chan->scan_type.shift, 623 chan->scan_type.realbits - 1); 624 ret = bmc150_accel_set_power_state(data, false); 625 mutex_unlock(&data->mutex); 626 if (ret < 0) 627 return ret; 628 629 return IIO_VAL_INT; 630} 631 632static int bmc150_accel_read_raw(struct iio_dev *indio_dev, 633 struct iio_chan_spec const *chan, 634 int *val, int *val2, long mask) 635{ 636 struct bmc150_accel_data *data = iio_priv(indio_dev); 637 int ret; 638 639 switch (mask) { 640 case IIO_CHAN_INFO_RAW: 641 switch (chan->type) { 642 case IIO_TEMP: 643 return bmc150_accel_get_temp(data, val); 644 case IIO_ACCEL: 645 if (iio_buffer_enabled(indio_dev)) 646 return -EBUSY; 647 else 648 return bmc150_accel_get_axis(data, chan, val); 649 default: 650 return -EINVAL; 651 } 652 case IIO_CHAN_INFO_OFFSET: 653 if (chan->type == IIO_TEMP) { 654 *val = BMC150_ACCEL_TEMP_CENTER_VAL; 655 return IIO_VAL_INT; 656 } else 657 return -EINVAL; 658 case IIO_CHAN_INFO_SCALE: 659 *val = 0; 660 switch (chan->type) { 661 case IIO_TEMP: 662 *val2 = 500000; 663 return IIO_VAL_INT_PLUS_MICRO; 664 case IIO_ACCEL: 665 { 666 int i; 667 const struct bmc150_scale_info *si; 668 int st_size = ARRAY_SIZE(data->chip_info->scale_table); 669 670 for (i = 0; i < st_size; ++i) { 671 si = &data->chip_info->scale_table[i]; 672 if (si->reg_range == data->range) { 673 *val2 = si->scale; 674 return IIO_VAL_INT_PLUS_MICRO; 675 } 676 } 677 return -EINVAL; 678 } 679 default: 680 return -EINVAL; 681 } 682 case IIO_CHAN_INFO_SAMP_FREQ: 683 mutex_lock(&data->mutex); 684 ret = bmc150_accel_get_bw(data, val, val2); 685 mutex_unlock(&data->mutex); 686 return ret; 687 default: 688 return -EINVAL; 689 } 690} 691 692static int bmc150_accel_write_raw(struct iio_dev *indio_dev, 693 struct iio_chan_spec const *chan, 694 int val, int val2, long mask) 695{ 696 struct bmc150_accel_data *data = iio_priv(indio_dev); 697 int ret; 698 699 switch (mask) { 700 case IIO_CHAN_INFO_SAMP_FREQ: 701 mutex_lock(&data->mutex); 702 ret = bmc150_accel_set_bw(data, val, val2); 703 mutex_unlock(&data->mutex); 704 break; 705 case IIO_CHAN_INFO_SCALE: 706 if (val) 707 return -EINVAL; 708 709 mutex_lock(&data->mutex); 710 ret = bmc150_accel_set_scale(data, val2); 711 mutex_unlock(&data->mutex); 712 return ret; 713 default: 714 ret = -EINVAL; 715 } 716 717 return ret; 718} 719 720static int bmc150_accel_read_event(struct iio_dev *indio_dev, 721 const struct iio_chan_spec *chan, 722 enum iio_event_type type, 723 enum iio_event_direction dir, 724 enum iio_event_info info, 725 int *val, int *val2) 726{ 727 struct bmc150_accel_data *data = iio_priv(indio_dev); 728 729 *val2 = 0; 730 switch (info) { 731 case IIO_EV_INFO_VALUE: 732 *val = data->slope_thres; 733 break; 734 case IIO_EV_INFO_PERIOD: 735 *val = data->slope_dur & BMC150_ACCEL_SLOPE_DUR_MASK; 736 break; 737 default: 738 return -EINVAL; 739 } 740 741 return IIO_VAL_INT; 742} 743 744static int bmc150_accel_write_event(struct iio_dev *indio_dev, 745 const struct iio_chan_spec *chan, 746 enum iio_event_type type, 747 enum iio_event_direction dir, 748 enum iio_event_info info, 749 int val, int val2) 750{ 751 struct bmc150_accel_data *data = iio_priv(indio_dev); 752 753 if (data->ev_enable_state) 754 return -EBUSY; 755 756 switch (info) { 757 case IIO_EV_INFO_VALUE: 758 data->slope_thres = val; 759 break; 760 case IIO_EV_INFO_PERIOD: 761 data->slope_dur &= ~BMC150_ACCEL_SLOPE_DUR_MASK; 762 data->slope_dur |= val & BMC150_ACCEL_SLOPE_DUR_MASK; 763 break; 764 default: 765 return -EINVAL; 766 } 767 768 return 0; 769} 770 771static int bmc150_accel_read_event_config(struct iio_dev *indio_dev, 772 const struct iio_chan_spec *chan, 773 enum iio_event_type type, 774 enum iio_event_direction dir) 775{ 776 777 struct bmc150_accel_data *data = iio_priv(indio_dev); 778 779 return data->ev_enable_state; 780} 781 782static int bmc150_accel_write_event_config(struct iio_dev *indio_dev, 783 const struct iio_chan_spec *chan, 784 enum iio_event_type type, 785 enum iio_event_direction dir, 786 int state) 787{ 788 struct bmc150_accel_data *data = iio_priv(indio_dev); 789 int ret; 790 791 if (state && data->ev_enable_state) 792 return 0; 793 794 mutex_lock(&data->mutex); 795 796 if (!state && data->motion_trigger_on) { 797 data->ev_enable_state = 0; 798 mutex_unlock(&data->mutex); 799 return 0; 800 } 801 802 /* 803 * We will expect the enable and disable to do operation in 804 * in reverse order. This will happen here anyway as our 805 * resume operation uses sync mode runtime pm calls, the 806 * suspend operation will be delayed by autosuspend delay 807 * So the disable operation will still happen in reverse of 808 * enable operation. When runtime pm is disabled the mode 809 * is always on so sequence doesn't matter 810 */ 811 812 ret = bmc150_accel_set_power_state(data, state); 813 if (ret < 0) { 814 mutex_unlock(&data->mutex); 815 return ret; 816 } 817 818 ret = bmc150_accel_setup_any_motion_interrupt(data, state); 819 if (ret < 0) { 820 bmc150_accel_set_power_state(data, false); 821 mutex_unlock(&data->mutex); 822 return ret; 823 } 824 825 data->ev_enable_state = state; 826 mutex_unlock(&data->mutex); 827 828 return 0; 829} 830 831static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, 832 struct iio_trigger *trig) 833{ 834 struct bmc150_accel_data *data = iio_priv(indio_dev); 835 836 if (data->dready_trig != trig && data->motion_trig != trig) 837 return -EINVAL; 838 839 return 0; 840} 841 842static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 843 "7.810000 15.630000 31.250000 62.500000 125 250 500 1000"); 844 845static struct attribute *bmc150_accel_attributes[] = { 846 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 847 NULL, 848}; 849 850static const struct attribute_group bmc150_accel_attrs_group = { 851 .attrs = bmc150_accel_attributes, 852}; 853 854static const struct iio_event_spec bmc150_accel_event = { 855 .type = IIO_EV_TYPE_ROC, 856 .dir = IIO_EV_DIR_EITHER, 857 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 858 BIT(IIO_EV_INFO_ENABLE) | 859 BIT(IIO_EV_INFO_PERIOD) 860}; 861 862#define BMC150_ACCEL_CHANNEL(_axis, bits) { \ 863 .type = IIO_ACCEL, \ 864 .modified = 1, \ 865 .channel2 = IIO_MOD_##_axis, \ 866 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 867 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 868 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 869 .scan_index = AXIS_##_axis, \ 870 .scan_type = { \ 871 .sign = 's', \ 872 .realbits = (bits), \ 873 .storagebits = 16, \ 874 .shift = 16 - (bits), \ 875 }, \ 876 .event_spec = &bmc150_accel_event, \ 877 .num_event_specs = 1 \ 878} 879 880#define BMC150_ACCEL_CHANNELS(bits) { \ 881 { \ 882 .type = IIO_TEMP, \ 883 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 884 BIT(IIO_CHAN_INFO_SCALE) | \ 885 BIT(IIO_CHAN_INFO_OFFSET), \ 886 .scan_index = -1, \ 887 }, \ 888 BMC150_ACCEL_CHANNEL(X, bits), \ 889 BMC150_ACCEL_CHANNEL(Y, bits), \ 890 BMC150_ACCEL_CHANNEL(Z, bits), \ 891 IIO_CHAN_SOFT_TIMESTAMP(3), \ 892} 893 894static const struct iio_chan_spec bma222e_accel_channels[] = 895 BMC150_ACCEL_CHANNELS(8); 896static const struct iio_chan_spec bma250e_accel_channels[] = 897 BMC150_ACCEL_CHANNELS(10); 898static const struct iio_chan_spec bmc150_accel_channels[] = 899 BMC150_ACCEL_CHANNELS(12); 900static const struct iio_chan_spec bma280_accel_channels[] = 901 BMC150_ACCEL_CHANNELS(14); 902 903enum { 904 bmc150, 905 bmi055, 906 bma255, 907 bma250e, 908 bma222e, 909 bma280, 910}; 911 912static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = { 913 [bmc150] = { 914 .chip_id = 0xFA, 915 .channels = bmc150_accel_channels, 916 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 917 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 918 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 919 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 920 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 921 }, 922 [bmi055] = { 923 .chip_id = 0xFA, 924 .channels = bmc150_accel_channels, 925 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 926 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 927 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 928 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 929 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 930 }, 931 [bma255] = { 932 .chip_id = 0xFA, 933 .channels = bmc150_accel_channels, 934 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 935 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 936 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 937 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 938 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 939 }, 940 [bma250e] = { 941 .chip_id = 0xF9, 942 .channels = bma250e_accel_channels, 943 .num_channels = ARRAY_SIZE(bma250e_accel_channels), 944 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G}, 945 {76590, BMC150_ACCEL_DEF_RANGE_4G}, 946 {153277, BMC150_ACCEL_DEF_RANGE_8G}, 947 {306457, BMC150_ACCEL_DEF_RANGE_16G} }, 948 }, 949 [bma222e] = { 950 .chip_id = 0xF8, 951 .channels = bma222e_accel_channels, 952 .num_channels = ARRAY_SIZE(bma222e_accel_channels), 953 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G}, 954 {306457, BMC150_ACCEL_DEF_RANGE_4G}, 955 {612915, BMC150_ACCEL_DEF_RANGE_8G}, 956 {1225831, BMC150_ACCEL_DEF_RANGE_16G} }, 957 }, 958 [bma280] = { 959 .chip_id = 0xFB, 960 .channels = bma280_accel_channels, 961 .num_channels = ARRAY_SIZE(bma280_accel_channels), 962 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G}, 963 {4785, BMC150_ACCEL_DEF_RANGE_4G}, 964 {9581, BMC150_ACCEL_DEF_RANGE_8G}, 965 {19152, BMC150_ACCEL_DEF_RANGE_16G} }, 966 }, 967}; 968 969static const struct iio_info bmc150_accel_info = { 970 .attrs = &bmc150_accel_attrs_group, 971 .read_raw = bmc150_accel_read_raw, 972 .write_raw = bmc150_accel_write_raw, 973 .read_event_value = bmc150_accel_read_event, 974 .write_event_value = bmc150_accel_write_event, 975 .write_event_config = bmc150_accel_write_event_config, 976 .read_event_config = bmc150_accel_read_event_config, 977 .validate_trigger = bmc150_accel_validate_trigger, 978 .driver_module = THIS_MODULE, 979}; 980 981static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) 982{ 983 struct iio_poll_func *pf = p; 984 struct iio_dev *indio_dev = pf->indio_dev; 985 struct bmc150_accel_data *data = iio_priv(indio_dev); 986 int bit, ret, i = 0; 987 988 mutex_lock(&data->mutex); 989 for_each_set_bit(bit, indio_dev->buffer->scan_mask, 990 indio_dev->masklength) { 991 ret = i2c_smbus_read_word_data(data->client, 992 BMC150_ACCEL_AXIS_TO_REG(bit)); 993 if (ret < 0) { 994 mutex_unlock(&data->mutex); 995 goto err_read; 996 } 997 data->buffer[i++] = ret; 998 } 999 mutex_unlock(&data->mutex); 1000 1001 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 1002 data->timestamp); 1003err_read: 1004 iio_trigger_notify_done(indio_dev->trig); 1005 1006 return IRQ_HANDLED; 1007} 1008 1009static int bmc150_accel_trig_try_reen(struct iio_trigger *trig) 1010{ 1011 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1012 struct bmc150_accel_data *data = iio_priv(indio_dev); 1013 int ret; 1014 1015 /* new data interrupts don't need ack */ 1016 if (data->dready_trigger_on) 1017 return 0; 1018 1019 mutex_lock(&data->mutex); 1020 /* clear any latched interrupt */ 1021 ret = i2c_smbus_write_byte_data(data->client, 1022 BMC150_ACCEL_REG_INT_RST_LATCH, 1023 BMC150_ACCEL_INT_MODE_LATCH_INT | 1024 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1025 mutex_unlock(&data->mutex); 1026 if (ret < 0) { 1027 dev_err(&data->client->dev, 1028 "Error writing reg_int_rst_latch\n"); 1029 return ret; 1030 } 1031 1032 return 0; 1033} 1034 1035static int bmc150_accel_data_rdy_trigger_set_state(struct iio_trigger *trig, 1036 bool state) 1037{ 1038 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1039 struct bmc150_accel_data *data = iio_priv(indio_dev); 1040 int ret; 1041 1042 mutex_lock(&data->mutex); 1043 1044 if (!state && data->ev_enable_state && data->motion_trigger_on) { 1045 data->motion_trigger_on = false; 1046 mutex_unlock(&data->mutex); 1047 return 0; 1048 } 1049 1050 /* 1051 * Refer to comment in bmc150_accel_write_event_config for 1052 * enable/disable operation order 1053 */ 1054 ret = bmc150_accel_set_power_state(data, state); 1055 if (ret < 0) { 1056 mutex_unlock(&data->mutex); 1057 return ret; 1058 } 1059 if (data->motion_trig == trig) 1060 ret = bmc150_accel_setup_any_motion_interrupt(data, state); 1061 else 1062 ret = bmc150_accel_setup_new_data_interrupt(data, state); 1063 if (ret < 0) { 1064 bmc150_accel_set_power_state(data, false); 1065 mutex_unlock(&data->mutex); 1066 return ret; 1067 } 1068 if (data->motion_trig == trig) 1069 data->motion_trigger_on = state; 1070 else 1071 data->dready_trigger_on = state; 1072 1073 mutex_unlock(&data->mutex); 1074 1075 return ret; 1076} 1077 1078static const struct iio_trigger_ops bmc150_accel_trigger_ops = { 1079 .set_trigger_state = bmc150_accel_data_rdy_trigger_set_state, 1080 .try_reenable = bmc150_accel_trig_try_reen, 1081 .owner = THIS_MODULE, 1082}; 1083 1084static irqreturn_t bmc150_accel_event_handler(int irq, void *private) 1085{ 1086 struct iio_dev *indio_dev = private; 1087 struct bmc150_accel_data *data = iio_priv(indio_dev); 1088 int ret; 1089 int dir; 1090 1091 ret = i2c_smbus_read_byte_data(data->client, 1092 BMC150_ACCEL_REG_INT_STATUS_2); 1093 if (ret < 0) { 1094 dev_err(&data->client->dev, "Error reading reg_int_status_2\n"); 1095 goto ack_intr_status; 1096 } 1097 1098 if (ret & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) 1099 dir = IIO_EV_DIR_FALLING; 1100 else 1101 dir = IIO_EV_DIR_RISING; 1102 1103 if (ret & BMC150_ACCEL_ANY_MOTION_BIT_X) 1104 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 1105 0, 1106 IIO_MOD_X, 1107 IIO_EV_TYPE_ROC, 1108 dir), 1109 data->timestamp); 1110 if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Y) 1111 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 1112 0, 1113 IIO_MOD_Y, 1114 IIO_EV_TYPE_ROC, 1115 dir), 1116 data->timestamp); 1117 if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Z) 1118 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 1119 0, 1120 IIO_MOD_Z, 1121 IIO_EV_TYPE_ROC, 1122 dir), 1123 data->timestamp); 1124ack_intr_status: 1125 if (!data->dready_trigger_on) 1126 ret = i2c_smbus_write_byte_data(data->client, 1127 BMC150_ACCEL_REG_INT_RST_LATCH, 1128 BMC150_ACCEL_INT_MODE_LATCH_INT | 1129 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1130 1131 return IRQ_HANDLED; 1132} 1133 1134static irqreturn_t bmc150_accel_data_rdy_trig_poll(int irq, void *private) 1135{ 1136 struct iio_dev *indio_dev = private; 1137 struct bmc150_accel_data *data = iio_priv(indio_dev); 1138 1139 data->timestamp = iio_get_time_ns(); 1140 1141 if (data->dready_trigger_on) 1142 iio_trigger_poll(data->dready_trig); 1143 else if (data->motion_trigger_on) 1144 iio_trigger_poll(data->motion_trig); 1145 1146 if (data->ev_enable_state) 1147 return IRQ_WAKE_THREAD; 1148 else 1149 return IRQ_HANDLED; 1150} 1151 1152static const char *bmc150_accel_match_acpi_device(struct device *dev, int *data) 1153{ 1154 const struct acpi_device_id *id; 1155 1156 id = acpi_match_device(dev->driver->acpi_match_table, dev); 1157 1158 if (!id) 1159 return NULL; 1160 1161 *data = (int) id->driver_data; 1162 1163 return dev_name(dev); 1164} 1165 1166static int bmc150_accel_gpio_probe(struct i2c_client *client, 1167 struct bmc150_accel_data *data) 1168{ 1169 struct device *dev; 1170 struct gpio_desc *gpio; 1171 int ret; 1172 1173 if (!client) 1174 return -EINVAL; 1175 1176 dev = &client->dev; 1177 1178 /* data ready gpio interrupt pin */ 1179 gpio = devm_gpiod_get_index(dev, BMC150_ACCEL_GPIO_NAME, 0); 1180 if (IS_ERR(gpio)) { 1181 dev_err(dev, "Failed: gpio get index\n"); 1182 return PTR_ERR(gpio); 1183 } 1184 1185 ret = gpiod_direction_input(gpio); 1186 if (ret) 1187 return ret; 1188 1189 ret = gpiod_to_irq(gpio); 1190 1191 dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret); 1192 1193 return ret; 1194} 1195 1196static int bmc150_accel_probe(struct i2c_client *client, 1197 const struct i2c_device_id *id) 1198{ 1199 struct bmc150_accel_data *data; 1200 struct iio_dev *indio_dev; 1201 int ret; 1202 const char *name = NULL; 1203 int chip_id = 0; 1204 1205 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1206 if (!indio_dev) 1207 return -ENOMEM; 1208 1209 data = iio_priv(indio_dev); 1210 i2c_set_clientdata(client, indio_dev); 1211 data->client = client; 1212 1213 if (id) { 1214 name = id->name; 1215 chip_id = id->driver_data; 1216 } 1217 1218 if (ACPI_HANDLE(&client->dev)) 1219 name = bmc150_accel_match_acpi_device(&client->dev, &chip_id); 1220 1221 data->chip_info = &bmc150_accel_chip_info_tbl[chip_id]; 1222 1223 ret = bmc150_accel_chip_init(data); 1224 if (ret < 0) 1225 return ret; 1226 1227 mutex_init(&data->mutex); 1228 1229 indio_dev->dev.parent = &client->dev; 1230 indio_dev->channels = data->chip_info->channels; 1231 indio_dev->num_channels = data->chip_info->num_channels; 1232 indio_dev->name = name; 1233 indio_dev->modes = INDIO_DIRECT_MODE; 1234 indio_dev->info = &bmc150_accel_info; 1235 1236 if (client->irq < 0) 1237 client->irq = bmc150_accel_gpio_probe(client, data); 1238 1239 if (client->irq >= 0) { 1240 ret = devm_request_threaded_irq( 1241 &client->dev, client->irq, 1242 bmc150_accel_data_rdy_trig_poll, 1243 bmc150_accel_event_handler, 1244 IRQF_TRIGGER_RISING, 1245 BMC150_ACCEL_IRQ_NAME, 1246 indio_dev); 1247 if (ret) 1248 return ret; 1249 1250 data->dready_trig = devm_iio_trigger_alloc(&client->dev, 1251 "%s-dev%d", 1252 indio_dev->name, 1253 indio_dev->id); 1254 if (!data->dready_trig) 1255 return -ENOMEM; 1256 1257 data->motion_trig = devm_iio_trigger_alloc(&client->dev, 1258 "%s-any-motion-dev%d", 1259 indio_dev->name, 1260 indio_dev->id); 1261 if (!data->motion_trig) 1262 return -ENOMEM; 1263 1264 data->dready_trig->dev.parent = &client->dev; 1265 data->dready_trig->ops = &bmc150_accel_trigger_ops; 1266 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 1267 ret = iio_trigger_register(data->dready_trig); 1268 if (ret) 1269 return ret; 1270 1271 data->motion_trig->dev.parent = &client->dev; 1272 data->motion_trig->ops = &bmc150_accel_trigger_ops; 1273 iio_trigger_set_drvdata(data->motion_trig, indio_dev); 1274 ret = iio_trigger_register(data->motion_trig); 1275 if (ret) { 1276 data->motion_trig = NULL; 1277 goto err_trigger_unregister; 1278 } 1279 1280 ret = iio_triggered_buffer_setup(indio_dev, 1281 &iio_pollfunc_store_time, 1282 bmc150_accel_trigger_handler, 1283 NULL); 1284 if (ret < 0) { 1285 dev_err(&client->dev, 1286 "Failed: iio triggered buffer setup\n"); 1287 goto err_trigger_unregister; 1288 } 1289 } 1290 1291 ret = iio_device_register(indio_dev); 1292 if (ret < 0) { 1293 dev_err(&client->dev, "Unable to register iio device\n"); 1294 goto err_buffer_cleanup; 1295 } 1296 1297 ret = pm_runtime_set_active(&client->dev); 1298 if (ret) 1299 goto err_iio_unregister; 1300 1301 pm_runtime_enable(&client->dev); 1302 pm_runtime_set_autosuspend_delay(&client->dev, 1303 BMC150_AUTO_SUSPEND_DELAY_MS); 1304 pm_runtime_use_autosuspend(&client->dev); 1305 1306 return 0; 1307 1308err_iio_unregister: 1309 iio_device_unregister(indio_dev); 1310err_buffer_cleanup: 1311 if (data->dready_trig) 1312 iio_triggered_buffer_cleanup(indio_dev); 1313err_trigger_unregister: 1314 if (data->dready_trig) 1315 iio_trigger_unregister(data->dready_trig); 1316 if (data->motion_trig) 1317 iio_trigger_unregister(data->motion_trig); 1318 1319 return ret; 1320} 1321 1322static int bmc150_accel_remove(struct i2c_client *client) 1323{ 1324 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1325 struct bmc150_accel_data *data = iio_priv(indio_dev); 1326 1327 pm_runtime_disable(&client->dev); 1328 pm_runtime_set_suspended(&client->dev); 1329 pm_runtime_put_noidle(&client->dev); 1330 1331 iio_device_unregister(indio_dev); 1332 1333 if (data->dready_trig) { 1334 iio_triggered_buffer_cleanup(indio_dev); 1335 iio_trigger_unregister(data->dready_trig); 1336 iio_trigger_unregister(data->motion_trig); 1337 } 1338 1339 mutex_lock(&data->mutex); 1340 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0); 1341 mutex_unlock(&data->mutex); 1342 1343 return 0; 1344} 1345 1346#ifdef CONFIG_PM_SLEEP 1347static int bmc150_accel_suspend(struct device *dev) 1348{ 1349 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1350 struct bmc150_accel_data *data = iio_priv(indio_dev); 1351 1352 mutex_lock(&data->mutex); 1353 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1354 mutex_unlock(&data->mutex); 1355 1356 return 0; 1357} 1358 1359static int bmc150_accel_resume(struct device *dev) 1360{ 1361 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1362 struct bmc150_accel_data *data = iio_priv(indio_dev); 1363 1364 mutex_lock(&data->mutex); 1365 if (data->dready_trigger_on || data->motion_trigger_on || 1366 data->ev_enable_state) 1367 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1368 mutex_unlock(&data->mutex); 1369 1370 return 0; 1371} 1372#endif 1373 1374#ifdef CONFIG_PM_RUNTIME 1375static int bmc150_accel_runtime_suspend(struct device *dev) 1376{ 1377 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1378 struct bmc150_accel_data *data = iio_priv(indio_dev); 1379 int ret; 1380 1381 dev_dbg(&data->client->dev, __func__); 1382 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1383 if (ret < 0) 1384 return -EAGAIN; 1385 1386 return 0; 1387} 1388 1389static int bmc150_accel_runtime_resume(struct device *dev) 1390{ 1391 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1392 struct bmc150_accel_data *data = iio_priv(indio_dev); 1393 int ret; 1394 int sleep_val; 1395 1396 dev_dbg(&data->client->dev, __func__); 1397 1398 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1399 if (ret < 0) 1400 return ret; 1401 1402 sleep_val = bmc150_accel_get_startup_times(data); 1403 if (sleep_val < 20) 1404 usleep_range(sleep_val * 1000, 20000); 1405 else 1406 msleep_interruptible(sleep_val); 1407 1408 return 0; 1409} 1410#endif 1411 1412static const struct dev_pm_ops bmc150_accel_pm_ops = { 1413 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume) 1414 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend, 1415 bmc150_accel_runtime_resume, NULL) 1416}; 1417 1418static const struct acpi_device_id bmc150_accel_acpi_match[] = { 1419 {"BSBA0150", bmc150}, 1420 {"BMC150A", bmc150}, 1421 {"BMI055A", bmi055}, 1422 {"BMA0255", bma255}, 1423 {"BMA250E", bma250e}, 1424 {"BMA222E", bma222e}, 1425 {"BMA0280", bma280}, 1426 { }, 1427}; 1428MODULE_DEVICE_TABLE(acpi, bmc150_accel_acpi_match); 1429 1430static const struct i2c_device_id bmc150_accel_id[] = { 1431 {"bmc150_accel", bmc150}, 1432 {"bmi055_accel", bmi055}, 1433 {"bma255", bma255}, 1434 {"bma250e", bma250e}, 1435 {"bma222e", bma222e}, 1436 {"bma280", bma280}, 1437 {} 1438}; 1439 1440MODULE_DEVICE_TABLE(i2c, bmc150_accel_id); 1441 1442static struct i2c_driver bmc150_accel_driver = { 1443 .driver = { 1444 .name = BMC150_ACCEL_DRV_NAME, 1445 .acpi_match_table = ACPI_PTR(bmc150_accel_acpi_match), 1446 .pm = &bmc150_accel_pm_ops, 1447 }, 1448 .probe = bmc150_accel_probe, 1449 .remove = bmc150_accel_remove, 1450 .id_table = bmc150_accel_id, 1451}; 1452module_i2c_driver(bmc150_accel_driver); 1453 1454MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1455MODULE_LICENSE("GPL v2"); 1456MODULE_DESCRIPTION("BMC150 accelerometer driver"); 1457