ipath_intr.c revision 555b203e48faeacc0373eda7bc87db874db37136
1/* 2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved. 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34#include <linux/pci.h> 35#include <linux/delay.h> 36 37#include "ipath_kernel.h" 38#include "ipath_verbs.h" 39#include "ipath_common.h" 40 41/* 42 * clear (write) a pio buffer, to clear a parity error. This routine 43 * should only be called when in freeze mode, and the buffer should be 44 * canceled afterwards. 45 */ 46static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum) 47{ 48 u32 __iomem *pbuf; 49 u32 dwcnt; /* dword count to write */ 50 if (pnum < dd->ipath_piobcnt2k) { 51 pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum * 52 dd->ipath_palign); 53 dwcnt = dd->ipath_piosize2k >> 2; 54 } 55 else { 56 pbuf = (u32 __iomem *) (dd->ipath_pio4kbase + 57 (pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign); 58 dwcnt = dd->ipath_piosize4k >> 2; 59 } 60 dev_info(&dd->pcidev->dev, 61 "Rewrite PIO buffer %u, to recover from parity error\n", 62 pnum); 63 64 /* no flush required, since already in freeze */ 65 writel(dwcnt + 1, pbuf); 66 while (--dwcnt) 67 writel(0, pbuf++); 68} 69 70/* 71 * Called when we might have an error that is specific to a particular 72 * PIO buffer, and may need to cancel that buffer, so it can be re-used. 73 * If rewrite is true, and bits are set in the sendbufferror registers, 74 * we'll write to the buffer, for error recovery on parity errors. 75 */ 76static void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite) 77{ 78 u32 piobcnt; 79 unsigned long sbuf[4]; 80 /* 81 * it's possible that sendbuffererror could have bits set; might 82 * have already done this as a result of hardware error handling 83 */ 84 piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; 85 /* read these before writing errorclear */ 86 sbuf[0] = ipath_read_kreg64( 87 dd, dd->ipath_kregs->kr_sendbuffererror); 88 sbuf[1] = ipath_read_kreg64( 89 dd, dd->ipath_kregs->kr_sendbuffererror + 1); 90 if (piobcnt > 128) { 91 sbuf[2] = ipath_read_kreg64( 92 dd, dd->ipath_kregs->kr_sendbuffererror + 2); 93 sbuf[3] = ipath_read_kreg64( 94 dd, dd->ipath_kregs->kr_sendbuffererror + 3); 95 } 96 97 if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) { 98 int i; 99 if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) && 100 dd->ipath_lastcancel > jiffies) { 101 __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG, 102 "SendbufErrs %lx %lx", sbuf[0], 103 sbuf[1]); 104 if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128) 105 printk(" %lx %lx ", sbuf[2], sbuf[3]); 106 printk("\n"); 107 } 108 109 for (i = 0; i < piobcnt; i++) 110 if (test_bit(i, sbuf)) { 111 if (rewrite) 112 ipath_clrpiobuf(dd, i); 113 ipath_disarm_piobufs(dd, i, 1); 114 } 115 /* ignore armlaunch errs for a bit */ 116 dd->ipath_lastcancel = jiffies+3; 117 } 118} 119 120 121/* These are all rcv-related errors which we want to count for stats */ 122#define E_SUM_PKTERRS \ 123 (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \ 124 INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \ 125 INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \ 126 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \ 127 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \ 128 INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP) 129 130/* These are all send-related errors which we want to count for stats */ 131#define E_SUM_ERRS \ 132 (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \ 133 INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 134 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \ 135 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ 136 INFINIPATH_E_INVALIDADDR) 137 138/* 139 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore 140 * errors not related to freeze and cancelling buffers. Can't ignore 141 * armlaunch because could get more while still cleaning up, and need 142 * to cancel those as they happen. 143 */ 144#define E_SPKT_ERRS_IGNORE \ 145 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 146 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SMINPKTLEN | \ 147 INFINIPATH_E_SPKTLEN) 148 149/* 150 * these are errors that can occur when the link changes state while 151 * a packet is being sent or received. This doesn't cover things 152 * like EBP or VCRC that can be the result of a sending having the 153 * link change state, so we receive a "known bad" packet. 154 */ 155#define E_SUM_LINK_PKTERRS \ 156 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 157 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ 158 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \ 159 INFINIPATH_E_RUNEXPCHAR) 160 161static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs) 162{ 163 u64 ignore_this_time = 0; 164 165 ipath_disarm_senderrbufs(dd, 0); 166 if ((errs & E_SUM_LINK_PKTERRS) && 167 !(dd->ipath_flags & IPATH_LINKACTIVE)) { 168 /* 169 * This can happen when SMA is trying to bring the link 170 * up, but the IB link changes state at the "wrong" time. 171 * The IB logic then complains that the packet isn't 172 * valid. We don't want to confuse people, so we just 173 * don't print them, except at debug 174 */ 175 ipath_dbg("Ignoring packet errors %llx, because link not " 176 "ACTIVE\n", (unsigned long long) errs); 177 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 178 } 179 180 return ignore_this_time; 181} 182 183/* generic hw error messages... */ 184#define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \ 185 { \ 186 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \ 187 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \ 188 .msg = "TXE " #a " Memory Parity" \ 189 } 190#define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \ 191 { \ 192 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \ 193 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \ 194 .msg = "RXE " #a " Memory Parity" \ 195 } 196 197static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = { 198 INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"), 199 INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"), 200 201 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF), 202 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC), 203 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO), 204 205 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF), 206 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ), 207 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID), 208 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID), 209 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF), 210 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO), 211 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO), 212}; 213 214/** 215 * ipath_format_hwmsg - format a single hwerror message 216 * @msg message buffer 217 * @msgl length of message buffer 218 * @hwmsg message to add to message buffer 219 */ 220static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg) 221{ 222 strlcat(msg, "[", msgl); 223 strlcat(msg, hwmsg, msgl); 224 strlcat(msg, "]", msgl); 225} 226 227/** 228 * ipath_format_hwerrors - format hardware error messages for display 229 * @hwerrs hardware errors bit vector 230 * @hwerrmsgs hardware error descriptions 231 * @nhwerrmsgs number of hwerrmsgs 232 * @msg message buffer 233 * @msgl message buffer length 234 */ 235void ipath_format_hwerrors(u64 hwerrs, 236 const struct ipath_hwerror_msgs *hwerrmsgs, 237 size_t nhwerrmsgs, 238 char *msg, size_t msgl) 239{ 240 int i; 241 const int glen = 242 sizeof(ipath_generic_hwerror_msgs) / 243 sizeof(ipath_generic_hwerror_msgs[0]); 244 245 for (i=0; i<glen; i++) { 246 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) { 247 ipath_format_hwmsg(msg, msgl, 248 ipath_generic_hwerror_msgs[i].msg); 249 } 250 } 251 252 for (i=0; i<nhwerrmsgs; i++) { 253 if (hwerrs & hwerrmsgs[i].mask) { 254 ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg); 255 } 256 } 257} 258 259/* return the strings for the most common link states */ 260static char *ib_linkstate(struct ipath_devdata *dd, u64 ibcs) 261{ 262 char *ret; 263 u32 state; 264 265 state = ipath_ib_state(dd, ibcs); 266 if (state == dd->ib_init) 267 ret = "Init"; 268 else if (state == dd->ib_arm) 269 ret = "Arm"; 270 else if (state == dd->ib_active) 271 ret = "Active"; 272 else 273 ret = "Down"; 274 return ret; 275} 276 277void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev) 278{ 279 struct ib_event event; 280 281 event.device = &dd->verbs_dev->ibdev; 282 event.element.port_num = 1; 283 event.event = ev; 284 ib_dispatch_event(&event); 285} 286 287static void handle_e_ibstatuschanged(struct ipath_devdata *dd, 288 ipath_err_t errs) 289{ 290 u32 ltstate, lstate, ibstate, lastlstate; 291 u32 init = dd->ib_init; 292 u32 arm = dd->ib_arm; 293 u32 active = dd->ib_active; 294 const u64 ibcs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus); 295 296 lstate = ipath_ib_linkstate(dd, ibcs); /* linkstate */ 297 ibstate = ipath_ib_state(dd, ibcs); 298 /* linkstate at last interrupt */ 299 lastlstate = ipath_ib_linkstate(dd, dd->ipath_lastibcstat); 300 ltstate = ipath_ib_linktrstate(dd, ibcs); /* linktrainingtate */ 301 302 /* 303 * Since going into a recovery state causes the link state to go 304 * down and since recovery is transitory, it is better if we "miss" 305 * ever seeing the link training state go into recovery (i.e., 306 * ignore this transition for link state special handling purposes) 307 * without even updating ipath_lastibcstat. 308 */ 309 if ((ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN) || 310 (ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT) || 311 (ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERIDLE)) 312 goto done; 313 314 /* 315 * if linkstate transitions into INIT from any of the various down 316 * states, or if it transitions from any of the up (INIT or better) 317 * states into any of the down states (except link recovery), then 318 * call the chip-specific code to take appropriate actions. 319 */ 320 if (lstate >= INFINIPATH_IBCS_L_STATE_INIT && 321 lastlstate == INFINIPATH_IBCS_L_STATE_DOWN) { 322 /* transitioned to UP */ 323 if (dd->ipath_f_ib_updown(dd, 1, ibcs)) { 324 /* link came up, so we must no longer be disabled */ 325 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED; 326 ipath_cdbg(LINKVERB, "LinkUp handled, skipped\n"); 327 goto skip_ibchange; /* chip-code handled */ 328 } 329 } else if ((lastlstate >= INFINIPATH_IBCS_L_STATE_INIT || 330 (dd->ipath_flags & IPATH_IB_FORCE_NOTIFY)) && 331 ltstate <= INFINIPATH_IBCS_LT_STATE_CFGWAITRMT && 332 ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) { 333 int handled; 334 handled = dd->ipath_f_ib_updown(dd, 0, ibcs); 335 dd->ipath_flags &= ~IPATH_IB_FORCE_NOTIFY; 336 if (handled) { 337 ipath_cdbg(LINKVERB, "LinkDown handled, skipped\n"); 338 goto skip_ibchange; /* chip-code handled */ 339 } 340 } 341 342 /* 343 * Significant enough to always print and get into logs, if it was 344 * unexpected. If it was a requested state change, we'll have 345 * already cleared the flags, so we won't print this warning 346 */ 347 if ((ibstate != arm && ibstate != active) && 348 (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) { 349 dev_info(&dd->pcidev->dev, "Link state changed from %s " 350 "to %s\n", (dd->ipath_flags & IPATH_LINKARMED) ? 351 "ARM" : "ACTIVE", ib_linkstate(dd, ibcs)); 352 } 353 354 if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE || 355 ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) { 356 u32 lastlts; 357 lastlts = ipath_ib_linktrstate(dd, dd->ipath_lastibcstat); 358 /* 359 * Ignore cycling back and forth from Polling.Active to 360 * Polling.Quiet while waiting for the other end of the link 361 * to come up, except to try and decide if we are connected 362 * to a live IB device or not. We will cycle back and 363 * forth between them if no cable is plugged in, the other 364 * device is powered off or disabled, etc. 365 */ 366 if (lastlts == INFINIPATH_IBCS_LT_STATE_POLLACTIVE || 367 lastlts == INFINIPATH_IBCS_LT_STATE_POLLQUIET) { 368 if (++dd->ipath_ibpollcnt == 40) { 369 dd->ipath_flags |= IPATH_NOCABLE; 370 *dd->ipath_statusp |= 371 IPATH_STATUS_IB_NOCABLE; 372 ipath_cdbg(LINKVERB, "Set NOCABLE\n"); 373 } 374 ipath_cdbg(LINKVERB, "POLL change to %s (%x)\n", 375 ipath_ibcstatus_str[ltstate], ibstate); 376 goto skip_ibchange; 377 } 378 } 379 380 dd->ipath_ibpollcnt = 0; /* not poll*, now */ 381 ipath_stats.sps_iblink++; 382 383 if (ibstate != init && dd->ipath_lastlinkrecov && ipath_linkrecovery) { 384 u64 linkrecov; 385 linkrecov = ipath_snap_cntr(dd, 386 dd->ipath_cregs->cr_iblinkerrrecovcnt); 387 if (linkrecov != dd->ipath_lastlinkrecov) { 388 ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n", 389 ibcs, ib_linkstate(dd, ibcs), 390 ipath_ibcstatus_str[ltstate], 391 linkrecov); 392 /* and no more until active again */ 393 dd->ipath_lastlinkrecov = 0; 394 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN); 395 goto skip_ibchange; 396 } 397 } 398 399 if (ibstate == init || ibstate == arm || ibstate == active) { 400 *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE; 401 if (ibstate == init || ibstate == arm) { 402 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 403 if (dd->ipath_flags & IPATH_LINKACTIVE) 404 signal_ib_event(dd, IB_EVENT_PORT_ERR); 405 } 406 if (ibstate == arm) { 407 dd->ipath_flags |= IPATH_LINKARMED; 408 dd->ipath_flags &= ~(IPATH_LINKUNK | 409 IPATH_LINKINIT | IPATH_LINKDOWN | 410 IPATH_LINKACTIVE | IPATH_NOCABLE); 411 ipath_hol_down(dd); 412 } else if (ibstate == init) { 413 /* 414 * set INIT and DOWN. Down is checked by 415 * most of the other code, but INIT is 416 * useful to know in a few places. 417 */ 418 dd->ipath_flags |= IPATH_LINKINIT | 419 IPATH_LINKDOWN; 420 dd->ipath_flags &= ~(IPATH_LINKUNK | 421 IPATH_LINKARMED | IPATH_LINKACTIVE | 422 IPATH_NOCABLE); 423 ipath_hol_down(dd); 424 } else { /* active */ 425 dd->ipath_lastlinkrecov = ipath_snap_cntr(dd, 426 dd->ipath_cregs->cr_iblinkerrrecovcnt); 427 *dd->ipath_statusp |= 428 IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF; 429 dd->ipath_flags |= IPATH_LINKACTIVE; 430 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 431 | IPATH_LINKDOWN | IPATH_LINKARMED | 432 IPATH_NOCABLE); 433 signal_ib_event(dd, IB_EVENT_PORT_ACTIVE); 434 /* LED active not handled in chip _f_updown */ 435 dd->ipath_f_setextled(dd, lstate, ltstate); 436 ipath_hol_up(dd); 437 } 438 439 /* 440 * print after we've already done the work, so as not to 441 * delay the state changes and notifications, for debugging 442 */ 443 if (lstate == lastlstate) 444 ipath_cdbg(LINKVERB, "Unchanged from last: %s " 445 "(%x)\n", ib_linkstate(dd, ibcs), ibstate); 446 else 447 ipath_cdbg(VERBOSE, "Unit %u: link up to %s %s (%x)\n", 448 dd->ipath_unit, ib_linkstate(dd, ibcs), 449 ipath_ibcstatus_str[ltstate], ibstate); 450 } else { /* down */ 451 if (dd->ipath_flags & IPATH_LINKACTIVE) 452 signal_ib_event(dd, IB_EVENT_PORT_ERR); 453 dd->ipath_flags |= IPATH_LINKDOWN; 454 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 455 | IPATH_LINKACTIVE | 456 IPATH_LINKARMED); 457 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 458 dd->ipath_lli_counter = 0; 459 460 if (lastlstate != INFINIPATH_IBCS_L_STATE_DOWN) 461 ipath_cdbg(VERBOSE, "Unit %u link state down " 462 "(state 0x%x), from %s\n", 463 dd->ipath_unit, lstate, 464 ib_linkstate(dd, dd->ipath_lastibcstat)); 465 else 466 ipath_cdbg(LINKVERB, "Unit %u link state changed " 467 "to %s (0x%x) from down (%x)\n", 468 dd->ipath_unit, 469 ipath_ibcstatus_str[ltstate], 470 ibstate, lastlstate); 471 } 472 473skip_ibchange: 474 dd->ipath_lastibcstat = ibcs; 475done: 476 return; 477} 478 479static void handle_supp_msgs(struct ipath_devdata *dd, 480 unsigned supp_msgs, char *msg, int msgsz) 481{ 482 /* 483 * Print the message unless it's ibc status change only, which 484 * happens so often we never want to count it. 485 */ 486 if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) { 487 int iserr; 488 iserr = ipath_decode_err(msg, msgsz, 489 dd->ipath_lasterror & 490 ~INFINIPATH_E_IBSTATUSCHANGED); 491 if (dd->ipath_lasterror & 492 ~(INFINIPATH_E_RRCVEGRFULL | 493 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) 494 ipath_dev_err(dd, "Suppressed %u messages for " 495 "fast-repeating errors (%s) (%llx)\n", 496 supp_msgs, msg, 497 (unsigned long long) 498 dd->ipath_lasterror); 499 else { 500 /* 501 * rcvegrfull and rcvhdrqfull are "normal", for some 502 * types of processes (mostly benchmarks) that send 503 * huge numbers of messages, while not processing 504 * them. So only complain about these at debug 505 * level. 506 */ 507 if (iserr) 508 ipath_dbg("Suppressed %u messages for %s\n", 509 supp_msgs, msg); 510 else 511 ipath_cdbg(ERRPKT, 512 "Suppressed %u messages for %s\n", 513 supp_msgs, msg); 514 } 515 } 516} 517 518static unsigned handle_frequent_errors(struct ipath_devdata *dd, 519 ipath_err_t errs, char *msg, 520 int msgsz, int *noprint) 521{ 522 unsigned long nc; 523 static unsigned long nextmsg_time; 524 static unsigned nmsgs, supp_msgs; 525 526 /* 527 * Throttle back "fast" messages to no more than 10 per 5 seconds. 528 * This isn't perfect, but it's a reasonable heuristic. If we get 529 * more than 10, give a 6x longer delay. 530 */ 531 nc = jiffies; 532 if (nmsgs > 10) { 533 if (time_before(nc, nextmsg_time)) { 534 *noprint = 1; 535 if (!supp_msgs++) 536 nextmsg_time = nc + HZ * 3; 537 } 538 else if (supp_msgs) { 539 handle_supp_msgs(dd, supp_msgs, msg, msgsz); 540 supp_msgs = 0; 541 nmsgs = 0; 542 } 543 } 544 else if (!nmsgs++ || time_after(nc, nextmsg_time)) 545 nextmsg_time = nc + HZ / 2; 546 547 return supp_msgs; 548} 549 550static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs) 551{ 552 char msg[128]; 553 u64 ignore_this_time = 0; 554 int i, iserr = 0; 555 int chkerrpkts = 0, noprint = 0; 556 unsigned supp_msgs; 557 int log_idx; 558 559 supp_msgs = handle_frequent_errors(dd, errs, msg, sizeof msg, &noprint); 560 561 /* don't report errors that are masked */ 562 errs &= ~dd->ipath_maskederrs; 563 564 /* do these first, they are most important */ 565 if (errs & INFINIPATH_E_HARDWARE) { 566 /* reuse same msg buf */ 567 dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg); 568 } else { 569 u64 mask; 570 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) { 571 mask = dd->ipath_eep_st_masks[log_idx].errs_to_log; 572 if (errs & mask) 573 ipath_inc_eeprom_err(dd, log_idx, 1); 574 } 575 } 576 577 if (!noprint && (errs & ~dd->ipath_e_bitsextant)) 578 ipath_dev_err(dd, "error interrupt with unknown errors " 579 "%llx set\n", (unsigned long long) 580 (errs & ~dd->ipath_e_bitsextant)); 581 582 if (errs & E_SUM_ERRS) 583 ignore_this_time = handle_e_sum_errs(dd, errs); 584 else if ((errs & E_SUM_LINK_PKTERRS) && 585 !(dd->ipath_flags & IPATH_LINKACTIVE)) { 586 /* 587 * This can happen when SMA is trying to bring the link 588 * up, but the IB link changes state at the "wrong" time. 589 * The IB logic then complains that the packet isn't 590 * valid. We don't want to confuse people, so we just 591 * don't print them, except at debug 592 */ 593 ipath_dbg("Ignoring packet errors %llx, because link not " 594 "ACTIVE\n", (unsigned long long) errs); 595 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 596 } 597 598 if (supp_msgs == 250000) { 599 int s_iserr; 600 /* 601 * It's not entirely reasonable assuming that the errors set 602 * in the last clear period are all responsible for the 603 * problem, but the alternative is to assume it's the only 604 * ones on this particular interrupt, which also isn't great 605 */ 606 dd->ipath_maskederrs |= dd->ipath_lasterror | errs; 607 608 dd->ipath_errormask &= ~dd->ipath_maskederrs; 609 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 610 dd->ipath_errormask); 611 s_iserr = ipath_decode_err(msg, sizeof msg, 612 dd->ipath_maskederrs); 613 614 if (dd->ipath_maskederrs & 615 ~(INFINIPATH_E_RRCVEGRFULL | 616 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) 617 ipath_dev_err(dd, "Temporarily disabling " 618 "error(s) %llx reporting; too frequent (%s)\n", 619 (unsigned long long) dd->ipath_maskederrs, 620 msg); 621 else { 622 /* 623 * rcvegrfull and rcvhdrqfull are "normal", 624 * for some types of processes (mostly benchmarks) 625 * that send huge numbers of messages, while not 626 * processing them. So only complain about 627 * these at debug level. 628 */ 629 if (s_iserr) 630 ipath_dbg("Temporarily disabling reporting " 631 "too frequent queue full errors (%s)\n", 632 msg); 633 else 634 ipath_cdbg(ERRPKT, 635 "Temporarily disabling reporting too" 636 " frequent packet errors (%s)\n", 637 msg); 638 } 639 640 /* 641 * Re-enable the masked errors after around 3 minutes. in 642 * ipath_get_faststats(). If we have a series of fast 643 * repeating but different errors, the interval will keep 644 * stretching out, but that's OK, as that's pretty 645 * catastrophic. 646 */ 647 dd->ipath_unmasktime = jiffies + HZ * 180; 648 } 649 650 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs); 651 if (ignore_this_time) 652 errs &= ~ignore_this_time; 653 if (errs & ~dd->ipath_lasterror) { 654 errs &= ~dd->ipath_lasterror; 655 /* never suppress duplicate hwerrors or ibstatuschange */ 656 dd->ipath_lasterror |= errs & 657 ~(INFINIPATH_E_HARDWARE | 658 INFINIPATH_E_IBSTATUSCHANGED); 659 } 660 661 /* likely due to cancel, so suppress */ 662 if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) && 663 dd->ipath_lastcancel > jiffies) { 664 ipath_dbg("Suppressed armlaunch/spktlen after error send cancel\n"); 665 errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN); 666 } 667 668 if (!errs) 669 return 0; 670 671 if (!noprint) 672 /* 673 * the ones we mask off are handled specially below or above 674 */ 675 ipath_decode_err(msg, sizeof msg, 676 errs & ~(INFINIPATH_E_IBSTATUSCHANGED | 677 INFINIPATH_E_RRCVEGRFULL | 678 INFINIPATH_E_RRCVHDRFULL | 679 INFINIPATH_E_HARDWARE)); 680 else 681 /* so we don't need if (!noprint) at strlcat's below */ 682 *msg = 0; 683 684 if (errs & E_SUM_PKTERRS) { 685 ipath_stats.sps_pkterrs++; 686 chkerrpkts = 1; 687 } 688 if (errs & E_SUM_ERRS) 689 ipath_stats.sps_errs++; 690 691 if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) { 692 ipath_stats.sps_crcerrs++; 693 chkerrpkts = 1; 694 } 695 iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS); 696 697 698 /* 699 * We don't want to print these two as they happen, or we can make 700 * the situation even worse, because it takes so long to print 701 * messages to serial consoles. Kernel ports get printed from 702 * fast_stats, no more than every 5 seconds, user ports get printed 703 * on close 704 */ 705 if (errs & INFINIPATH_E_RRCVHDRFULL) { 706 u32 hd, tl; 707 ipath_stats.sps_hdrqfull++; 708 for (i = 0; i < dd->ipath_cfgports; i++) { 709 struct ipath_portdata *pd = dd->ipath_pd[i]; 710 if (i == 0) { 711 hd = pd->port_head; 712 tl = ipath_get_hdrqtail(pd); 713 } else if (pd && pd->port_cnt && 714 pd->port_rcvhdrtail_kvaddr) { 715 /* 716 * don't report same point multiple times, 717 * except kernel 718 */ 719 tl = *(u64 *) pd->port_rcvhdrtail_kvaddr; 720 if (tl == pd->port_lastrcvhdrqtail) 721 continue; 722 hd = ipath_read_ureg32(dd, ur_rcvhdrhead, 723 i); 724 } else 725 continue; 726 if (hd == (tl + 1) || 727 (!hd && tl == dd->ipath_hdrqlast)) { 728 if (i == 0) 729 chkerrpkts = 1; 730 pd->port_lastrcvhdrqtail = tl; 731 pd->port_hdrqfull++; 732 /* flush hdrqfull so that poll() sees it */ 733 wmb(); 734 wake_up_interruptible(&pd->port_wait); 735 } 736 } 737 } 738 if (errs & INFINIPATH_E_RRCVEGRFULL) { 739 struct ipath_portdata *pd = dd->ipath_pd[0]; 740 741 /* 742 * since this is of less importance and not likely to 743 * happen without also getting hdrfull, only count 744 * occurrences; don't check each port (or even the kernel 745 * vs user) 746 */ 747 ipath_stats.sps_etidfull++; 748 if (pd->port_head != ipath_get_hdrqtail(pd)) 749 chkerrpkts = 1; 750 } 751 752 /* 753 * do this before IBSTATUSCHANGED, in case both bits set in a single 754 * interrupt; we want the STATUSCHANGE to "win", so we do our 755 * internal copy of state machine correctly 756 */ 757 if (errs & INFINIPATH_E_RIBLOSTLINK) { 758 /* 759 * force through block below 760 */ 761 errs |= INFINIPATH_E_IBSTATUSCHANGED; 762 ipath_stats.sps_iblink++; 763 dd->ipath_flags |= IPATH_LINKDOWN; 764 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 765 | IPATH_LINKARMED | IPATH_LINKACTIVE); 766 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 767 768 ipath_dbg("Lost link, link now down (%s)\n", 769 ipath_ibcstatus_str[ipath_read_kreg64(dd, 770 dd->ipath_kregs->kr_ibcstatus) & 0xf]); 771 } 772 if (errs & INFINIPATH_E_IBSTATUSCHANGED) 773 handle_e_ibstatuschanged(dd, errs); 774 775 if (errs & INFINIPATH_E_RESET) { 776 if (!noprint) 777 ipath_dev_err(dd, "Got reset, requires re-init " 778 "(unload and reload driver)\n"); 779 dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */ 780 /* mark as having had error */ 781 *dd->ipath_statusp |= IPATH_STATUS_HWERROR; 782 *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF; 783 } 784 785 if (!noprint && *msg) { 786 if (iserr) 787 ipath_dev_err(dd, "%s error\n", msg); 788 else 789 dev_info(&dd->pcidev->dev, "%s packet problems\n", 790 msg); 791 } 792 if (dd->ipath_state_wanted & dd->ipath_flags) { 793 ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, " 794 "waking\n", dd->ipath_state_wanted, 795 dd->ipath_flags); 796 wake_up_interruptible(&ipath_state_wait); 797 } 798 799 return chkerrpkts; 800} 801 802/* 803 * try to cleanup as much as possible for anything that might have gone 804 * wrong while in freeze mode, such as pio buffers being written by user 805 * processes (causing armlaunch), send errors due to going into freeze mode, 806 * etc., and try to avoid causing extra interrupts while doing so. 807 * Forcibly update the in-memory pioavail register copies after cleanup 808 * because the chip won't do it for anything changing while in freeze mode 809 * (we don't want to wait for the next pio buffer state change). 810 * Make sure that we don't lose any important interrupts by using the chip 811 * feature that says that writing 0 to a bit in *clear that is set in 812 * *status will cause an interrupt to be generated again (if allowed by 813 * the *mask value). 814 */ 815void ipath_clear_freeze(struct ipath_devdata *dd) 816{ 817 int i, im; 818 u64 val; 819 820 /* disable error interrupts, to avoid confusion */ 821 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 0ULL); 822 823 /* also disable interrupts; errormask is sometimes overwriten */ 824 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); 825 826 /* 827 * clear all sends, because they have may been 828 * completed by usercode while in freeze mode, and 829 * therefore would not be sent, and eventually 830 * might cause the process to run out of bufs 831 */ 832 ipath_cancel_sends(dd, 0); 833 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 834 dd->ipath_control); 835 836 /* ensure pio avail updates continue */ 837 ipath_force_pio_avail_update(dd); 838 839 /* 840 * We just enabled pioavailupdate, so dma copy is almost certainly 841 * not yet right, so read the registers directly. Similar to init 842 */ 843 for (i = 0; i < dd->ipath_pioavregs; i++) { 844 /* deal with 6110 chip bug */ 845 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ? 846 i ^ 1 : i; 847 val = ipath_read_kreg64(dd, (0x1000 / sizeof(u64)) + im); 848 dd->ipath_pioavailregs_dma[i] = cpu_to_le64(val); 849 dd->ipath_pioavailshadow[i] = val | 850 (~dd->ipath_pioavailkernel[i] << 851 INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT); 852 } 853 854 /* 855 * force new interrupt if any hwerr, error or interrupt bits are 856 * still set, and clear "safe" send packet errors related to freeze 857 * and cancelling sends. Re-enable error interrupts before possible 858 * force of re-interrupt on pending interrupts. 859 */ 860 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 0ULL); 861 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, 862 E_SPKT_ERRS_IGNORE); 863 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 864 dd->ipath_errormask); 865 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, -1LL); 866 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL); 867} 868 869 870/* this is separate to allow for better optimization of ipath_intr() */ 871 872static noinline void ipath_bad_intr(struct ipath_devdata *dd, u32 *unexpectp) 873{ 874 /* 875 * sometimes happen during driver init and unload, don't want 876 * to process any interrupts at that point 877 */ 878 879 /* this is just a bandaid, not a fix, if something goes badly 880 * wrong */ 881 if (++*unexpectp > 100) { 882 if (++*unexpectp > 105) { 883 /* 884 * ok, we must be taking somebody else's interrupts, 885 * due to a messed up mptable and/or PIRQ table, so 886 * unregister the interrupt. We've seen this during 887 * linuxbios development work, and it may happen in 888 * the future again. 889 */ 890 if (dd->pcidev && dd->ipath_irq) { 891 ipath_dev_err(dd, "Now %u unexpected " 892 "interrupts, unregistering " 893 "interrupt handler\n", 894 *unexpectp); 895 ipath_dbg("free_irq of irq %d\n", 896 dd->ipath_irq); 897 dd->ipath_f_free_irq(dd); 898 } 899 } 900 if (ipath_read_ireg(dd, dd->ipath_kregs->kr_intmask)) { 901 ipath_dev_err(dd, "%u unexpected interrupts, " 902 "disabling interrupts completely\n", 903 *unexpectp); 904 /* 905 * disable all interrupts, something is very wrong 906 */ 907 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 908 0ULL); 909 } 910 } else if (*unexpectp > 1) 911 ipath_dbg("Interrupt when not ready, should not happen, " 912 "ignoring\n"); 913} 914 915static noinline void ipath_bad_regread(struct ipath_devdata *dd) 916{ 917 static int allbits; 918 919 /* separate routine, for better optimization of ipath_intr() */ 920 921 /* 922 * We print the message and disable interrupts, in hope of 923 * having a better chance of debugging the problem. 924 */ 925 ipath_dev_err(dd, 926 "Read of interrupt status failed (all bits set)\n"); 927 if (allbits++) { 928 /* disable all interrupts, something is very wrong */ 929 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); 930 if (allbits == 2) { 931 ipath_dev_err(dd, "Still bad interrupt status, " 932 "unregistering interrupt\n"); 933 dd->ipath_f_free_irq(dd); 934 } else if (allbits > 2) { 935 if ((allbits % 10000) == 0) 936 printk("."); 937 } else 938 ipath_dev_err(dd, "Disabling interrupts, " 939 "multiple errors\n"); 940 } 941} 942 943static void handle_layer_pioavail(struct ipath_devdata *dd) 944{ 945 unsigned long flags; 946 int ret; 947 948 ret = ipath_ib_piobufavail(dd->verbs_dev); 949 if (ret > 0) 950 goto set; 951 952 return; 953set: 954 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); 955 dd->ipath_sendctrl |= INFINIPATH_S_PIOINTBUFAVAIL; 956 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 957 dd->ipath_sendctrl); 958 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); 959 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); 960} 961 962/* 963 * Handle receive interrupts for user ports; this means a user 964 * process was waiting for a packet to arrive, and didn't want 965 * to poll 966 */ 967static void handle_urcv(struct ipath_devdata *dd, u64 istat) 968{ 969 u64 portr; 970 int i; 971 int rcvdint = 0; 972 973 /* 974 * test_and_clear_bit(IPATH_PORT_WAITING_RCV) and 975 * test_and_clear_bit(IPATH_PORT_WAITING_URG) below 976 * would both like timely updates of the bits so that 977 * we don't pass them by unnecessarily. the rmb() 978 * here ensures that we see them promptly -- the 979 * corresponding wmb()'s are in ipath_poll_urgent() 980 * and ipath_poll_next()... 981 */ 982 rmb(); 983 portr = ((istat >> dd->ipath_i_rcvavail_shift) & 984 dd->ipath_i_rcvavail_mask) | 985 ((istat >> dd->ipath_i_rcvurg_shift) & 986 dd->ipath_i_rcvurg_mask); 987 for (i = 1; i < dd->ipath_cfgports; i++) { 988 struct ipath_portdata *pd = dd->ipath_pd[i]; 989 990 if (portr & (1 << i) && pd && pd->port_cnt) { 991 if (test_and_clear_bit(IPATH_PORT_WAITING_RCV, 992 &pd->port_flag)) { 993 clear_bit(i + dd->ipath_r_intravail_shift, 994 &dd->ipath_rcvctrl); 995 wake_up_interruptible(&pd->port_wait); 996 rcvdint = 1; 997 } else if (test_and_clear_bit(IPATH_PORT_WAITING_URG, 998 &pd->port_flag)) { 999 pd->port_urgent++; 1000 wake_up_interruptible(&pd->port_wait); 1001 } 1002 } 1003 } 1004 if (rcvdint) { 1005 /* only want to take one interrupt, so turn off the rcv 1006 * interrupt for all the ports that we set the rcv_waiting 1007 * (but never for kernel port) 1008 */ 1009 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 1010 dd->ipath_rcvctrl); 1011 } 1012} 1013 1014irqreturn_t ipath_intr(int irq, void *data) 1015{ 1016 struct ipath_devdata *dd = data; 1017 u32 istat, chk0rcv = 0; 1018 ipath_err_t estat = 0; 1019 irqreturn_t ret; 1020 static unsigned unexpected = 0; 1021 u64 kportrbits; 1022 1023 ipath_stats.sps_ints++; 1024 1025 if (dd->ipath_int_counter != (u32) -1) 1026 dd->ipath_int_counter++; 1027 1028 if (!(dd->ipath_flags & IPATH_PRESENT)) { 1029 /* 1030 * This return value is not great, but we do not want the 1031 * interrupt core code to remove our interrupt handler 1032 * because we don't appear to be handling an interrupt 1033 * during a chip reset. 1034 */ 1035 return IRQ_HANDLED; 1036 } 1037 1038 /* 1039 * this needs to be flags&initted, not statusp, so we keep 1040 * taking interrupts even after link goes down, etc. 1041 * Also, we *must* clear the interrupt at some point, or we won't 1042 * take it again, which can be real bad for errors, etc... 1043 */ 1044 1045 if (!(dd->ipath_flags & IPATH_INITTED)) { 1046 ipath_bad_intr(dd, &unexpected); 1047 ret = IRQ_NONE; 1048 goto bail; 1049 } 1050 1051 istat = ipath_read_ireg(dd, dd->ipath_kregs->kr_intstatus); 1052 1053 if (unlikely(!istat)) { 1054 ipath_stats.sps_nullintr++; 1055 ret = IRQ_NONE; /* not our interrupt, or already handled */ 1056 goto bail; 1057 } 1058 if (unlikely(istat == -1)) { 1059 ipath_bad_regread(dd); 1060 /* don't know if it was our interrupt or not */ 1061 ret = IRQ_NONE; 1062 goto bail; 1063 } 1064 1065 if (unexpected) 1066 unexpected = 0; 1067 1068 if (unlikely(istat & ~dd->ipath_i_bitsextant)) 1069 ipath_dev_err(dd, 1070 "interrupt with unknown interrupts %x set\n", 1071 istat & (u32) ~ dd->ipath_i_bitsextant); 1072 else 1073 ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat); 1074 1075 if (unlikely(istat & INFINIPATH_I_ERROR)) { 1076 ipath_stats.sps_errints++; 1077 estat = ipath_read_kreg64(dd, 1078 dd->ipath_kregs->kr_errorstatus); 1079 if (!estat) 1080 dev_info(&dd->pcidev->dev, "error interrupt (%x), " 1081 "but no error bits set!\n", istat); 1082 else if (estat == -1LL) 1083 /* 1084 * should we try clearing all, or hope next read 1085 * works? 1086 */ 1087 ipath_dev_err(dd, "Read of error status failed " 1088 "(all bits set); ignoring\n"); 1089 else 1090 chk0rcv |= handle_errors(dd, estat); 1091 } 1092 1093 if (istat & INFINIPATH_I_GPIO) { 1094 /* 1095 * GPIO interrupts fall in two broad classes: 1096 * GPIO_2 indicates (on some HT4xx boards) that a packet 1097 * has arrived for Port 0. Checking for this 1098 * is controlled by flag IPATH_GPIO_INTR. 1099 * GPIO_3..5 on IBA6120 Rev2 and IBA6110 Rev4 chips indicate 1100 * errors that we need to count. Checking for this 1101 * is controlled by flag IPATH_GPIO_ERRINTRS. 1102 */ 1103 u32 gpiostatus; 1104 u32 to_clear = 0; 1105 1106 gpiostatus = ipath_read_kreg32( 1107 dd, dd->ipath_kregs->kr_gpio_status); 1108 /* First the error-counter case. */ 1109 if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) && 1110 (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) { 1111 /* want to clear the bits we see asserted. */ 1112 to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK); 1113 1114 /* 1115 * Count appropriately, clear bits out of our copy, 1116 * as they have been "handled". 1117 */ 1118 if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) { 1119 ipath_dbg("FlowCtl on UnsupVL\n"); 1120 dd->ipath_rxfc_unsupvl_errs++; 1121 } 1122 if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) { 1123 ipath_dbg("Overrun Threshold exceeded\n"); 1124 dd->ipath_overrun_thresh_errs++; 1125 } 1126 if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) { 1127 ipath_dbg("Local Link Integrity error\n"); 1128 dd->ipath_lli_errs++; 1129 } 1130 gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK; 1131 } 1132 /* Now the Port0 Receive case */ 1133 if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) && 1134 (dd->ipath_flags & IPATH_GPIO_INTR)) { 1135 /* 1136 * GPIO status bit 2 is set, and we expected it. 1137 * clear it and indicate in p0bits. 1138 * This probably only happens if a Port0 pkt 1139 * arrives at _just_ the wrong time, and we 1140 * handle that by seting chk0rcv; 1141 */ 1142 to_clear |= (1 << IPATH_GPIO_PORT0_BIT); 1143 gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT); 1144 chk0rcv = 1; 1145 } 1146 if (gpiostatus) { 1147 /* 1148 * Some unexpected bits remain. If they could have 1149 * caused the interrupt, complain and clear. 1150 * To avoid repetition of this condition, also clear 1151 * the mask. It is almost certainly due to error. 1152 */ 1153 const u32 mask = (u32) dd->ipath_gpio_mask; 1154 1155 if (mask & gpiostatus) { 1156 ipath_dbg("Unexpected GPIO IRQ bits %x\n", 1157 gpiostatus & mask); 1158 to_clear |= (gpiostatus & mask); 1159 dd->ipath_gpio_mask &= ~(gpiostatus & mask); 1160 ipath_write_kreg(dd, 1161 dd->ipath_kregs->kr_gpio_mask, 1162 dd->ipath_gpio_mask); 1163 } 1164 } 1165 if (to_clear) { 1166 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear, 1167 (u64) to_clear); 1168 } 1169 } 1170 1171 /* 1172 * Clear the interrupt bits we found set, unless they are receive 1173 * related, in which case we already cleared them above, and don't 1174 * want to clear them again, because we might lose an interrupt. 1175 * Clear it early, so we "know" know the chip will have seen this by 1176 * the time we process the queue, and will re-interrupt if necessary. 1177 * The processor itself won't take the interrupt again until we return. 1178 */ 1179 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat); 1180 1181 /* 1182 * Handle kernel receive queues before checking for pio buffers 1183 * available since receives can overflow; piobuf waiters can afford 1184 * a few extra cycles, since they were waiting anyway, and user's 1185 * waiting for receive are at the bottom. 1186 */ 1187 kportrbits = (1ULL << dd->ipath_i_rcvavail_shift) | 1188 (1ULL << dd->ipath_i_rcvurg_shift); 1189 if (chk0rcv || (istat & kportrbits)) { 1190 istat &= ~kportrbits; 1191 ipath_kreceive(dd->ipath_pd[0]); 1192 } 1193 1194 if (istat & ((dd->ipath_i_rcvavail_mask << dd->ipath_i_rcvavail_shift) | 1195 (dd->ipath_i_rcvurg_mask << dd->ipath_i_rcvurg_shift))) 1196 handle_urcv(dd, istat); 1197 1198 if (istat & INFINIPATH_I_SPIOBUFAVAIL) { 1199 unsigned long flags; 1200 1201 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); 1202 dd->ipath_sendctrl &= ~INFINIPATH_S_PIOINTBUFAVAIL; 1203 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 1204 dd->ipath_sendctrl); 1205 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); 1206 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); 1207 1208 handle_layer_pioavail(dd); 1209 } 1210 1211 ret = IRQ_HANDLED; 1212 1213bail: 1214 return ret; 1215} 1216