ipath_intr.c revision 78d1e02fac0595a8aa8a5064d1bd0c0ea55b22b0
1/* 2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved. 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34#include <linux/pci.h> 35 36#include "ipath_kernel.h" 37#include "ipath_verbs.h" 38#include "ipath_common.h" 39 40/* 41 * clear (write) a pio buffer, to clear a parity error. This routine 42 * should only be called when in freeze mode, and the buffer should be 43 * canceled afterwards. 44 */ 45static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum) 46{ 47 u32 __iomem *pbuf; 48 u32 dwcnt; /* dword count to write */ 49 if (pnum < dd->ipath_piobcnt2k) { 50 pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum * 51 dd->ipath_palign); 52 dwcnt = dd->ipath_piosize2k >> 2; 53 } 54 else { 55 pbuf = (u32 __iomem *) (dd->ipath_pio4kbase + 56 (pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign); 57 dwcnt = dd->ipath_piosize4k >> 2; 58 } 59 dev_info(&dd->pcidev->dev, 60 "Rewrite PIO buffer %u, to recover from parity error\n", 61 pnum); 62 *pbuf = dwcnt+1; /* no flush required, since already in freeze */ 63 while(--dwcnt) 64 *pbuf++ = 0; 65} 66 67/* 68 * Called when we might have an error that is specific to a particular 69 * PIO buffer, and may need to cancel that buffer, so it can be re-used. 70 * If rewrite is true, and bits are set in the sendbufferror registers, 71 * we'll write to the buffer, for error recovery on parity errors. 72 */ 73static void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite) 74{ 75 u32 piobcnt; 76 unsigned long sbuf[4]; 77 /* 78 * it's possible that sendbuffererror could have bits set; might 79 * have already done this as a result of hardware error handling 80 */ 81 piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; 82 /* read these before writing errorclear */ 83 sbuf[0] = ipath_read_kreg64( 84 dd, dd->ipath_kregs->kr_sendbuffererror); 85 sbuf[1] = ipath_read_kreg64( 86 dd, dd->ipath_kregs->kr_sendbuffererror + 1); 87 if (piobcnt > 128) { 88 sbuf[2] = ipath_read_kreg64( 89 dd, dd->ipath_kregs->kr_sendbuffererror + 2); 90 sbuf[3] = ipath_read_kreg64( 91 dd, dd->ipath_kregs->kr_sendbuffererror + 3); 92 } 93 94 if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) { 95 int i; 96 if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) && 97 dd->ipath_lastcancel > jiffies) { 98 __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG, 99 "SendbufErrs %lx %lx", sbuf[0], 100 sbuf[1]); 101 if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128) 102 printk(" %lx %lx ", sbuf[2], sbuf[3]); 103 printk("\n"); 104 } 105 106 for (i = 0; i < piobcnt; i++) 107 if (test_bit(i, sbuf)) { 108 if (rewrite) 109 ipath_clrpiobuf(dd, i); 110 ipath_disarm_piobufs(dd, i, 1); 111 } 112 /* ignore armlaunch errs for a bit */ 113 dd->ipath_lastcancel = jiffies+3; 114 } 115} 116 117 118/* These are all rcv-related errors which we want to count for stats */ 119#define E_SUM_PKTERRS \ 120 (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \ 121 INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \ 122 INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \ 123 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \ 124 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \ 125 INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP) 126 127/* These are all send-related errors which we want to count for stats */ 128#define E_SUM_ERRS \ 129 (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \ 130 INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 131 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \ 132 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ 133 INFINIPATH_E_INVALIDADDR) 134 135/* 136 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore 137 * errors not related to freeze and cancelling buffers. Can't ignore 138 * armlaunch because could get more while still cleaning up, and need 139 * to cancel those as they happen. 140 */ 141#define E_SPKT_ERRS_IGNORE \ 142 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 143 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SMINPKTLEN | \ 144 INFINIPATH_E_SPKTLEN) 145 146/* 147 * these are errors that can occur when the link changes state while 148 * a packet is being sent or received. This doesn't cover things 149 * like EBP or VCRC that can be the result of a sending having the 150 * link change state, so we receive a "known bad" packet. 151 */ 152#define E_SUM_LINK_PKTERRS \ 153 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 154 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ 155 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \ 156 INFINIPATH_E_RUNEXPCHAR) 157 158static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs) 159{ 160 u64 ignore_this_time = 0; 161 162 ipath_disarm_senderrbufs(dd, 0); 163 if ((errs & E_SUM_LINK_PKTERRS) && 164 !(dd->ipath_flags & IPATH_LINKACTIVE)) { 165 /* 166 * This can happen when SMA is trying to bring the link 167 * up, but the IB link changes state at the "wrong" time. 168 * The IB logic then complains that the packet isn't 169 * valid. We don't want to confuse people, so we just 170 * don't print them, except at debug 171 */ 172 ipath_dbg("Ignoring packet errors %llx, because link not " 173 "ACTIVE\n", (unsigned long long) errs); 174 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 175 } 176 177 return ignore_this_time; 178} 179 180/* generic hw error messages... */ 181#define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \ 182 { \ 183 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \ 184 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \ 185 .msg = "TXE " #a " Memory Parity" \ 186 } 187#define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \ 188 { \ 189 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \ 190 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \ 191 .msg = "RXE " #a " Memory Parity" \ 192 } 193 194static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = { 195 INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"), 196 INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"), 197 198 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF), 199 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC), 200 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO), 201 202 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF), 203 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ), 204 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID), 205 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID), 206 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF), 207 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO), 208 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO), 209}; 210 211/** 212 * ipath_format_hwmsg - format a single hwerror message 213 * @msg message buffer 214 * @msgl length of message buffer 215 * @hwmsg message to add to message buffer 216 */ 217static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg) 218{ 219 strlcat(msg, "[", msgl); 220 strlcat(msg, hwmsg, msgl); 221 strlcat(msg, "]", msgl); 222} 223 224/** 225 * ipath_format_hwerrors - format hardware error messages for display 226 * @hwerrs hardware errors bit vector 227 * @hwerrmsgs hardware error descriptions 228 * @nhwerrmsgs number of hwerrmsgs 229 * @msg message buffer 230 * @msgl message buffer length 231 */ 232void ipath_format_hwerrors(u64 hwerrs, 233 const struct ipath_hwerror_msgs *hwerrmsgs, 234 size_t nhwerrmsgs, 235 char *msg, size_t msgl) 236{ 237 int i; 238 const int glen = 239 sizeof(ipath_generic_hwerror_msgs) / 240 sizeof(ipath_generic_hwerror_msgs[0]); 241 242 for (i=0; i<glen; i++) { 243 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) { 244 ipath_format_hwmsg(msg, msgl, 245 ipath_generic_hwerror_msgs[i].msg); 246 } 247 } 248 249 for (i=0; i<nhwerrmsgs; i++) { 250 if (hwerrs & hwerrmsgs[i].mask) { 251 ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg); 252 } 253 } 254} 255 256/* return the strings for the most common link states */ 257static char *ib_linkstate(u32 linkstate) 258{ 259 char *ret; 260 261 switch (linkstate) { 262 case IPATH_IBSTATE_INIT: 263 ret = "Init"; 264 break; 265 case IPATH_IBSTATE_ARM: 266 ret = "Arm"; 267 break; 268 case IPATH_IBSTATE_ACTIVE: 269 ret = "Active"; 270 break; 271 default: 272 ret = "Down"; 273 } 274 275 return ret; 276} 277 278static void handle_e_ibstatuschanged(struct ipath_devdata *dd, 279 ipath_err_t errs, int noprint) 280{ 281 u64 val; 282 u32 ltstate, lstate; 283 284 /* 285 * even if diags are enabled, we want to notice LINKINIT, etc. 286 * We just don't want to change the LED state, or 287 * dd->ipath_kregs->kr_ibcctrl 288 */ 289 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus); 290 lstate = val & IPATH_IBSTATE_MASK; 291 292 /* 293 * this is confusing enough when it happens that I want to always put it 294 * on the console and in the logs. If it was a requested state change, 295 * we'll have already cleared the flags, so we won't print this warning 296 */ 297 if ((lstate != IPATH_IBSTATE_ARM && lstate != IPATH_IBSTATE_ACTIVE) 298 && (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) { 299 dev_info(&dd->pcidev->dev, "Link state changed from %s to %s\n", 300 (dd->ipath_flags & IPATH_LINKARMED) ? "ARM" : "ACTIVE", 301 ib_linkstate(lstate)); 302 /* 303 * Flush all queued sends when link went to DOWN or INIT, 304 * to be sure that they don't block SMA and other MAD packets 305 */ 306 ipath_cancel_sends(dd, 1); 307 } 308 else if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM || 309 lstate == IPATH_IBSTATE_ACTIVE) { 310 /* 311 * only print at SMA if there is a change, debug if not 312 * (sometimes we want to know that, usually not). 313 */ 314 if (lstate == ((unsigned) dd->ipath_lastibcstat 315 & IPATH_IBSTATE_MASK)) { 316 ipath_dbg("Status change intr but no change (%s)\n", 317 ib_linkstate(lstate)); 318 } 319 else 320 ipath_cdbg(VERBOSE, "Unit %u link state %s, last " 321 "was %s\n", dd->ipath_unit, 322 ib_linkstate(lstate), 323 ib_linkstate((unsigned) 324 dd->ipath_lastibcstat 325 & IPATH_IBSTATE_MASK)); 326 } 327 else { 328 lstate = dd->ipath_lastibcstat & IPATH_IBSTATE_MASK; 329 if (lstate == IPATH_IBSTATE_INIT || 330 lstate == IPATH_IBSTATE_ARM || 331 lstate == IPATH_IBSTATE_ACTIVE) 332 ipath_cdbg(VERBOSE, "Unit %u link state down" 333 " (state 0x%x), from %s\n", 334 dd->ipath_unit, 335 (u32)val & IPATH_IBSTATE_MASK, 336 ib_linkstate(lstate)); 337 else 338 ipath_cdbg(VERBOSE, "Unit %u link state changed " 339 "to 0x%x from down (%x)\n", 340 dd->ipath_unit, (u32) val, lstate); 341 } 342 ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) & 343 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK; 344 lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) & 345 INFINIPATH_IBCS_LINKSTATE_MASK; 346 347 if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE || 348 ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) { 349 u32 last_ltstate; 350 351 /* 352 * Ignore cycling back and forth from Polling.Active 353 * to Polling.Quiet while waiting for the other end of 354 * the link to come up. We will cycle back and forth 355 * between them if no cable is plugged in, 356 * the other device is powered off or disabled, etc. 357 */ 358 last_ltstate = (dd->ipath_lastibcstat >> 359 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) 360 & INFINIPATH_IBCS_LINKTRAININGSTATE_MASK; 361 if (last_ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE 362 || last_ltstate == 363 INFINIPATH_IBCS_LT_STATE_POLLQUIET) { 364 if (dd->ipath_ibpollcnt > 40) { 365 dd->ipath_flags |= IPATH_NOCABLE; 366 *dd->ipath_statusp |= 367 IPATH_STATUS_IB_NOCABLE; 368 } else 369 dd->ipath_ibpollcnt++; 370 goto skip_ibchange; 371 } 372 } 373 dd->ipath_ibpollcnt = 0; /* some state other than 2 or 3 */ 374 ipath_stats.sps_iblink++; 375 if (ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) { 376 dd->ipath_flags |= IPATH_LINKDOWN; 377 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 378 | IPATH_LINKACTIVE | 379 IPATH_LINKARMED); 380 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 381 dd->ipath_lli_counter = 0; 382 if (!noprint) { 383 if (((dd->ipath_lastibcstat >> 384 INFINIPATH_IBCS_LINKSTATE_SHIFT) & 385 INFINIPATH_IBCS_LINKSTATE_MASK) 386 == INFINIPATH_IBCS_L_STATE_ACTIVE) 387 /* if from up to down be more vocal */ 388 ipath_cdbg(VERBOSE, 389 "Unit %u link now down (%s)\n", 390 dd->ipath_unit, 391 ipath_ibcstatus_str[ltstate]); 392 else 393 ipath_cdbg(VERBOSE, "Unit %u link is " 394 "down (%s)\n", dd->ipath_unit, 395 ipath_ibcstatus_str[ltstate]); 396 } 397 398 dd->ipath_f_setextled(dd, lstate, ltstate); 399 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ACTIVE) { 400 dd->ipath_flags |= IPATH_LINKACTIVE; 401 dd->ipath_flags &= 402 ~(IPATH_LINKUNK | IPATH_LINKINIT | IPATH_LINKDOWN | 403 IPATH_LINKARMED | IPATH_NOCABLE); 404 *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE; 405 *dd->ipath_statusp |= 406 IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF; 407 dd->ipath_f_setextled(dd, lstate, ltstate); 408 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_INIT) { 409 /* 410 * set INIT and DOWN. Down is checked by most of the other 411 * code, but INIT is useful to know in a few places. 412 */ 413 dd->ipath_flags |= IPATH_LINKINIT | IPATH_LINKDOWN; 414 dd->ipath_flags &= 415 ~(IPATH_LINKUNK | IPATH_LINKACTIVE | IPATH_LINKARMED 416 | IPATH_NOCABLE); 417 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE 418 | IPATH_STATUS_IB_READY); 419 dd->ipath_f_setextled(dd, lstate, ltstate); 420 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ARM) { 421 dd->ipath_flags |= IPATH_LINKARMED; 422 dd->ipath_flags &= 423 ~(IPATH_LINKUNK | IPATH_LINKDOWN | IPATH_LINKINIT | 424 IPATH_LINKACTIVE | IPATH_NOCABLE); 425 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE 426 | IPATH_STATUS_IB_READY); 427 dd->ipath_f_setextled(dd, lstate, ltstate); 428 } else { 429 if (!noprint) 430 ipath_dbg("IBstatuschange unit %u: %s (%x)\n", 431 dd->ipath_unit, 432 ipath_ibcstatus_str[ltstate], ltstate); 433 } 434skip_ibchange: 435 dd->ipath_lastibcstat = val; 436} 437 438static void handle_supp_msgs(struct ipath_devdata *dd, 439 unsigned supp_msgs, char msg[512]) 440{ 441 /* 442 * Print the message unless it's ibc status change only, which 443 * happens so often we never want to count it. 444 */ 445 if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) { 446 int iserr; 447 iserr = ipath_decode_err(msg, sizeof msg, 448 dd->ipath_lasterror & 449 ~INFINIPATH_E_IBSTATUSCHANGED); 450 if (dd->ipath_lasterror & 451 ~(INFINIPATH_E_RRCVEGRFULL | 452 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) 453 ipath_dev_err(dd, "Suppressed %u messages for " 454 "fast-repeating errors (%s) (%llx)\n", 455 supp_msgs, msg, 456 (unsigned long long) 457 dd->ipath_lasterror); 458 else { 459 /* 460 * rcvegrfull and rcvhdrqfull are "normal", for some 461 * types of processes (mostly benchmarks) that send 462 * huge numbers of messages, while not processing 463 * them. So only complain about these at debug 464 * level. 465 */ 466 if (iserr) 467 ipath_dbg("Suppressed %u messages for %s\n", 468 supp_msgs, msg); 469 else 470 ipath_cdbg(ERRPKT, 471 "Suppressed %u messages for %s\n", 472 supp_msgs, msg); 473 } 474 } 475} 476 477static unsigned handle_frequent_errors(struct ipath_devdata *dd, 478 ipath_err_t errs, char msg[512], 479 int *noprint) 480{ 481 unsigned long nc; 482 static unsigned long nextmsg_time; 483 static unsigned nmsgs, supp_msgs; 484 485 /* 486 * Throttle back "fast" messages to no more than 10 per 5 seconds. 487 * This isn't perfect, but it's a reasonable heuristic. If we get 488 * more than 10, give a 6x longer delay. 489 */ 490 nc = jiffies; 491 if (nmsgs > 10) { 492 if (time_before(nc, nextmsg_time)) { 493 *noprint = 1; 494 if (!supp_msgs++) 495 nextmsg_time = nc + HZ * 3; 496 } 497 else if (supp_msgs) { 498 handle_supp_msgs(dd, supp_msgs, msg); 499 supp_msgs = 0; 500 nmsgs = 0; 501 } 502 } 503 else if (!nmsgs++ || time_after(nc, nextmsg_time)) 504 nextmsg_time = nc + HZ / 2; 505 506 return supp_msgs; 507} 508 509static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs) 510{ 511 char msg[512]; 512 u64 ignore_this_time = 0; 513 int i, iserr = 0; 514 int chkerrpkts = 0, noprint = 0; 515 unsigned supp_msgs; 516 int log_idx; 517 518 supp_msgs = handle_frequent_errors(dd, errs, msg, &noprint); 519 520 /* don't report errors that are masked */ 521 errs &= ~dd->ipath_maskederrs; 522 523 /* do these first, they are most important */ 524 if (errs & INFINIPATH_E_HARDWARE) { 525 /* reuse same msg buf */ 526 dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg); 527 } else { 528 u64 mask; 529 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) { 530 mask = dd->ipath_eep_st_masks[log_idx].errs_to_log; 531 if (errs & mask) 532 ipath_inc_eeprom_err(dd, log_idx, 1); 533 } 534 } 535 536 if (!noprint && (errs & ~dd->ipath_e_bitsextant)) 537 ipath_dev_err(dd, "error interrupt with unknown errors " 538 "%llx set\n", (unsigned long long) 539 (errs & ~dd->ipath_e_bitsextant)); 540 541 if (errs & E_SUM_ERRS) 542 ignore_this_time = handle_e_sum_errs(dd, errs); 543 else if ((errs & E_SUM_LINK_PKTERRS) && 544 !(dd->ipath_flags & IPATH_LINKACTIVE)) { 545 /* 546 * This can happen when SMA is trying to bring the link 547 * up, but the IB link changes state at the "wrong" time. 548 * The IB logic then complains that the packet isn't 549 * valid. We don't want to confuse people, so we just 550 * don't print them, except at debug 551 */ 552 ipath_dbg("Ignoring packet errors %llx, because link not " 553 "ACTIVE\n", (unsigned long long) errs); 554 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 555 } 556 557 if (supp_msgs == 250000) { 558 int s_iserr; 559 /* 560 * It's not entirely reasonable assuming that the errors set 561 * in the last clear period are all responsible for the 562 * problem, but the alternative is to assume it's the only 563 * ones on this particular interrupt, which also isn't great 564 */ 565 dd->ipath_maskederrs |= dd->ipath_lasterror | errs; 566 dd->ipath_errormask &= ~dd->ipath_maskederrs; 567 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 568 dd->ipath_errormask); 569 s_iserr = ipath_decode_err(msg, sizeof msg, 570 dd->ipath_maskederrs); 571 572 if (dd->ipath_maskederrs & 573 ~(INFINIPATH_E_RRCVEGRFULL | 574 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) 575 ipath_dev_err(dd, "Temporarily disabling " 576 "error(s) %llx reporting; too frequent (%s)\n", 577 (unsigned long long)dd->ipath_maskederrs, 578 msg); 579 else { 580 /* 581 * rcvegrfull and rcvhdrqfull are "normal", 582 * for some types of processes (mostly benchmarks) 583 * that send huge numbers of messages, while not 584 * processing them. So only complain about 585 * these at debug level. 586 */ 587 if (s_iserr) 588 ipath_dbg("Temporarily disabling reporting " 589 "too frequent queue full errors (%s)\n", 590 msg); 591 else 592 ipath_cdbg(ERRPKT, 593 "Temporarily disabling reporting too" 594 " frequent packet errors (%s)\n", 595 msg); 596 } 597 598 /* 599 * Re-enable the masked errors after around 3 minutes. in 600 * ipath_get_faststats(). If we have a series of fast 601 * repeating but different errors, the interval will keep 602 * stretching out, but that's OK, as that's pretty 603 * catastrophic. 604 */ 605 dd->ipath_unmasktime = jiffies + HZ * 180; 606 } 607 608 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs); 609 if (ignore_this_time) 610 errs &= ~ignore_this_time; 611 if (errs & ~dd->ipath_lasterror) { 612 errs &= ~dd->ipath_lasterror; 613 /* never suppress duplicate hwerrors or ibstatuschange */ 614 dd->ipath_lasterror |= errs & 615 ~(INFINIPATH_E_HARDWARE | 616 INFINIPATH_E_IBSTATUSCHANGED); 617 } 618 619 /* likely due to cancel, so suppress */ 620 if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) && 621 dd->ipath_lastcancel > jiffies) { 622 ipath_dbg("Suppressed armlaunch/spktlen after error send cancel\n"); 623 errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN); 624 } 625 626 if (!errs) 627 return 0; 628 629 if (!noprint) 630 /* 631 * the ones we mask off are handled specially below or above 632 */ 633 ipath_decode_err(msg, sizeof msg, 634 errs & ~(INFINIPATH_E_IBSTATUSCHANGED | 635 INFINIPATH_E_RRCVEGRFULL | 636 INFINIPATH_E_RRCVHDRFULL | 637 INFINIPATH_E_HARDWARE)); 638 else 639 /* so we don't need if (!noprint) at strlcat's below */ 640 *msg = 0; 641 642 if (errs & E_SUM_PKTERRS) { 643 ipath_stats.sps_pkterrs++; 644 chkerrpkts = 1; 645 } 646 if (errs & E_SUM_ERRS) 647 ipath_stats.sps_errs++; 648 649 if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) { 650 ipath_stats.sps_crcerrs++; 651 chkerrpkts = 1; 652 } 653 iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS); 654 655 656 /* 657 * We don't want to print these two as they happen, or we can make 658 * the situation even worse, because it takes so long to print 659 * messages to serial consoles. Kernel ports get printed from 660 * fast_stats, no more than every 5 seconds, user ports get printed 661 * on close 662 */ 663 if (errs & INFINIPATH_E_RRCVHDRFULL) { 664 u32 hd, tl; 665 ipath_stats.sps_hdrqfull++; 666 for (i = 0; i < dd->ipath_cfgports; i++) { 667 struct ipath_portdata *pd = dd->ipath_pd[i]; 668 if (i == 0) { 669 hd = dd->ipath_port0head; 670 tl = (u32) le64_to_cpu( 671 *dd->ipath_hdrqtailptr); 672 } else if (pd && pd->port_cnt && 673 pd->port_rcvhdrtail_kvaddr) { 674 /* 675 * don't report same point multiple times, 676 * except kernel 677 */ 678 tl = *(u64 *) pd->port_rcvhdrtail_kvaddr; 679 if (tl == dd->ipath_lastrcvhdrqtails[i]) 680 continue; 681 hd = ipath_read_ureg32(dd, ur_rcvhdrhead, 682 i); 683 } else 684 continue; 685 if (hd == (tl + 1) || 686 (!hd && tl == dd->ipath_hdrqlast)) { 687 if (i == 0) 688 chkerrpkts = 1; 689 dd->ipath_lastrcvhdrqtails[i] = tl; 690 pd->port_hdrqfull++; 691 if (test_bit(IPATH_PORT_WAITING_OVERFLOW, 692 &pd->port_flag)) { 693 clear_bit( 694 IPATH_PORT_WAITING_OVERFLOW, 695 &pd->port_flag); 696 set_bit( 697 IPATH_PORT_WAITING_OVERFLOW, 698 &pd->int_flag); 699 wake_up_interruptible( 700 &pd->port_wait); 701 } 702 } 703 } 704 } 705 if (errs & INFINIPATH_E_RRCVEGRFULL) { 706 /* 707 * since this is of less importance and not likely to 708 * happen without also getting hdrfull, only count 709 * occurrences; don't check each port (or even the kernel 710 * vs user) 711 */ 712 ipath_stats.sps_etidfull++; 713 if (dd->ipath_port0head != 714 (u32) le64_to_cpu(*dd->ipath_hdrqtailptr)) 715 chkerrpkts = 1; 716 } 717 718 /* 719 * do this before IBSTATUSCHANGED, in case both bits set in a single 720 * interrupt; we want the STATUSCHANGE to "win", so we do our 721 * internal copy of state machine correctly 722 */ 723 if (errs & INFINIPATH_E_RIBLOSTLINK) { 724 /* 725 * force through block below 726 */ 727 errs |= INFINIPATH_E_IBSTATUSCHANGED; 728 ipath_stats.sps_iblink++; 729 dd->ipath_flags |= IPATH_LINKDOWN; 730 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 731 | IPATH_LINKARMED | IPATH_LINKACTIVE); 732 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 733 if (!noprint) { 734 u64 st = ipath_read_kreg64( 735 dd, dd->ipath_kregs->kr_ibcstatus); 736 737 ipath_dbg("Lost link, link now down (%s)\n", 738 ipath_ibcstatus_str[st & 0xf]); 739 } 740 } 741 if (errs & INFINIPATH_E_IBSTATUSCHANGED) 742 handle_e_ibstatuschanged(dd, errs, noprint); 743 744 if (errs & INFINIPATH_E_RESET) { 745 if (!noprint) 746 ipath_dev_err(dd, "Got reset, requires re-init " 747 "(unload and reload driver)\n"); 748 dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */ 749 /* mark as having had error */ 750 *dd->ipath_statusp |= IPATH_STATUS_HWERROR; 751 *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF; 752 } 753 754 if (!noprint && *msg) { 755 if (iserr) 756 ipath_dev_err(dd, "%s error\n", msg); 757 else 758 dev_info(&dd->pcidev->dev, "%s packet problems\n", 759 msg); 760 } 761 if (dd->ipath_state_wanted & dd->ipath_flags) { 762 ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, " 763 "waking\n", dd->ipath_state_wanted, 764 dd->ipath_flags); 765 wake_up_interruptible(&ipath_state_wait); 766 } 767 768 return chkerrpkts; 769} 770 771 772/* 773 * try to cleanup as much as possible for anything that might have gone 774 * wrong while in freeze mode, such as pio buffers being written by user 775 * processes (causing armlaunch), send errors due to going into freeze mode, 776 * etc., and try to avoid causing extra interrupts while doing so. 777 * Forcibly update the in-memory pioavail register copies after cleanup 778 * because the chip won't do it for anything changing while in freeze mode 779 * (we don't want to wait for the next pio buffer state change). 780 * Make sure that we don't lose any important interrupts by using the chip 781 * feature that says that writing 0 to a bit in *clear that is set in 782 * *status will cause an interrupt to be generated again (if allowed by 783 * the *mask value). 784 */ 785void ipath_clear_freeze(struct ipath_devdata *dd) 786{ 787 int i, im; 788 __le64 val; 789 790 /* disable error interrupts, to avoid confusion */ 791 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 0ULL); 792 793 /* also disable interrupts; errormask is sometimes overwriten */ 794 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); 795 796 /* 797 * clear all sends, because they have may been 798 * completed by usercode while in freeze mode, and 799 * therefore would not be sent, and eventually 800 * might cause the process to run out of bufs 801 */ 802 ipath_cancel_sends(dd, 0); 803 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 804 dd->ipath_control); 805 806 /* ensure pio avail updates continue */ 807 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 808 dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD); 809 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); 810 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 811 dd->ipath_sendctrl); 812 813 /* 814 * We just enabled pioavailupdate, so dma copy is almost certainly 815 * not yet right, so read the registers directly. Similar to init 816 */ 817 for (i = 0; i < dd->ipath_pioavregs; i++) { 818 /* deal with 6110 chip bug */ 819 im = i > 3 ? ((i&1) ? i-1 : i+1) : i; 820 val = ipath_read_kreg64(dd, (0x1000/sizeof(u64))+im); 821 dd->ipath_pioavailregs_dma[i] = dd->ipath_pioavailshadow[i] 822 = le64_to_cpu(val); 823 } 824 825 /* 826 * force new interrupt if any hwerr, error or interrupt bits are 827 * still set, and clear "safe" send packet errors related to freeze 828 * and cancelling sends. Re-enable error interrupts before possible 829 * force of re-interrupt on pending interrupts. 830 */ 831 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 0ULL); 832 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, 833 E_SPKT_ERRS_IGNORE); 834 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 835 dd->ipath_errormask); 836 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, -1LL); 837 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL); 838} 839 840 841/* this is separate to allow for better optimization of ipath_intr() */ 842 843static void ipath_bad_intr(struct ipath_devdata *dd, u32 * unexpectp) 844{ 845 /* 846 * sometimes happen during driver init and unload, don't want 847 * to process any interrupts at that point 848 */ 849 850 /* this is just a bandaid, not a fix, if something goes badly 851 * wrong */ 852 if (++*unexpectp > 100) { 853 if (++*unexpectp > 105) { 854 /* 855 * ok, we must be taking somebody else's interrupts, 856 * due to a messed up mptable and/or PIRQ table, so 857 * unregister the interrupt. We've seen this during 858 * linuxbios development work, and it may happen in 859 * the future again. 860 */ 861 if (dd->pcidev && dd->ipath_irq) { 862 ipath_dev_err(dd, "Now %u unexpected " 863 "interrupts, unregistering " 864 "interrupt handler\n", 865 *unexpectp); 866 ipath_dbg("free_irq of irq %d\n", 867 dd->ipath_irq); 868 dd->ipath_f_free_irq(dd); 869 } 870 } 871 if (ipath_read_kreg32(dd, dd->ipath_kregs->kr_intmask)) { 872 ipath_dev_err(dd, "%u unexpected interrupts, " 873 "disabling interrupts completely\n", 874 *unexpectp); 875 /* 876 * disable all interrupts, something is very wrong 877 */ 878 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 879 0ULL); 880 } 881 } else if (*unexpectp > 1) 882 ipath_dbg("Interrupt when not ready, should not happen, " 883 "ignoring\n"); 884} 885 886static void ipath_bad_regread(struct ipath_devdata *dd) 887{ 888 static int allbits; 889 890 /* separate routine, for better optimization of ipath_intr() */ 891 892 /* 893 * We print the message and disable interrupts, in hope of 894 * having a better chance of debugging the problem. 895 */ 896 ipath_dev_err(dd, 897 "Read of interrupt status failed (all bits set)\n"); 898 if (allbits++) { 899 /* disable all interrupts, something is very wrong */ 900 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); 901 if (allbits == 2) { 902 ipath_dev_err(dd, "Still bad interrupt status, " 903 "unregistering interrupt\n"); 904 dd->ipath_f_free_irq(dd); 905 } else if (allbits > 2) { 906 if ((allbits % 10000) == 0) 907 printk("."); 908 } else 909 ipath_dev_err(dd, "Disabling interrupts, " 910 "multiple errors\n"); 911 } 912} 913 914static void handle_port_pioavail(struct ipath_devdata *dd) 915{ 916 u32 i; 917 /* 918 * start from port 1, since for now port 0 is never using 919 * wait_event for PIO 920 */ 921 for (i = 1; dd->ipath_portpiowait && i < dd->ipath_cfgports; i++) { 922 struct ipath_portdata *pd = dd->ipath_pd[i]; 923 924 if (pd && pd->port_cnt && 925 dd->ipath_portpiowait & (1U << i)) { 926 clear_bit(i, &dd->ipath_portpiowait); 927 if (test_bit(IPATH_PORT_WAITING_PIO, 928 &pd->port_flag)) { 929 clear_bit(IPATH_PORT_WAITING_PIO, 930 &pd->port_flag); 931 wake_up_interruptible(&pd->port_wait); 932 } 933 } 934 } 935} 936 937static void handle_layer_pioavail(struct ipath_devdata *dd) 938{ 939 int ret; 940 941 ret = ipath_ib_piobufavail(dd->verbs_dev); 942 if (ret > 0) 943 goto set; 944 945 return; 946set: 947 set_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl); 948 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 949 dd->ipath_sendctrl); 950} 951 952/* 953 * Handle receive interrupts for user ports; this means a user 954 * process was waiting for a packet to arrive, and didn't want 955 * to poll 956 */ 957static void handle_urcv(struct ipath_devdata *dd, u32 istat) 958{ 959 u64 portr; 960 int i; 961 int rcvdint = 0; 962 963 portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) & 964 dd->ipath_i_rcvavail_mask) 965 | ((istat >> INFINIPATH_I_RCVURG_SHIFT) & 966 dd->ipath_i_rcvurg_mask); 967 for (i = 1; i < dd->ipath_cfgports; i++) { 968 struct ipath_portdata *pd = dd->ipath_pd[i]; 969 if (portr & (1 << i) && pd && pd->port_cnt) { 970 if (test_bit(IPATH_PORT_WAITING_RCV, 971 &pd->port_flag)) { 972 clear_bit(IPATH_PORT_WAITING_RCV, 973 &pd->port_flag); 974 set_bit(IPATH_PORT_WAITING_RCV, 975 &pd->int_flag); 976 clear_bit(i + INFINIPATH_R_INTRAVAIL_SHIFT, 977 &dd->ipath_rcvctrl); 978 wake_up_interruptible(&pd->port_wait); 979 rcvdint = 1; 980 } else if (test_bit(IPATH_PORT_WAITING_URG, 981 &pd->port_flag)) { 982 clear_bit(IPATH_PORT_WAITING_URG, 983 &pd->port_flag); 984 set_bit(IPATH_PORT_WAITING_URG, 985 &pd->int_flag); 986 wake_up_interruptible(&pd->port_wait); 987 } 988 } 989 } 990 if (rcvdint) { 991 /* only want to take one interrupt, so turn off the rcv 992 * interrupt for all the ports that we did the wakeup on 993 * (but never for kernel port) 994 */ 995 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 996 dd->ipath_rcvctrl); 997 } 998} 999 1000irqreturn_t ipath_intr(int irq, void *data) 1001{ 1002 struct ipath_devdata *dd = data; 1003 u32 istat, chk0rcv = 0; 1004 ipath_err_t estat = 0; 1005 irqreturn_t ret; 1006 static unsigned unexpected = 0; 1007 static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) | 1008 (1U<<INFINIPATH_I_RCVURG_SHIFT); 1009 1010 ipath_stats.sps_ints++; 1011 1012 if (dd->ipath_int_counter != (u32) -1) 1013 dd->ipath_int_counter++; 1014 1015 if (!(dd->ipath_flags & IPATH_PRESENT)) { 1016 /* 1017 * This return value is not great, but we do not want the 1018 * interrupt core code to remove our interrupt handler 1019 * because we don't appear to be handling an interrupt 1020 * during a chip reset. 1021 */ 1022 return IRQ_HANDLED; 1023 } 1024 1025 /* 1026 * this needs to be flags&initted, not statusp, so we keep 1027 * taking interrupts even after link goes down, etc. 1028 * Also, we *must* clear the interrupt at some point, or we won't 1029 * take it again, which can be real bad for errors, etc... 1030 */ 1031 1032 if (!(dd->ipath_flags & IPATH_INITTED)) { 1033 ipath_bad_intr(dd, &unexpected); 1034 ret = IRQ_NONE; 1035 goto bail; 1036 } 1037 1038 istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus); 1039 1040 if (unlikely(!istat)) { 1041 ipath_stats.sps_nullintr++; 1042 ret = IRQ_NONE; /* not our interrupt, or already handled */ 1043 goto bail; 1044 } 1045 if (unlikely(istat == -1)) { 1046 ipath_bad_regread(dd); 1047 /* don't know if it was our interrupt or not */ 1048 ret = IRQ_NONE; 1049 goto bail; 1050 } 1051 1052 if (unexpected) 1053 unexpected = 0; 1054 1055 if (unlikely(istat & ~dd->ipath_i_bitsextant)) 1056 ipath_dev_err(dd, 1057 "interrupt with unknown interrupts %x set\n", 1058 istat & (u32) ~ dd->ipath_i_bitsextant); 1059 else 1060 ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat); 1061 1062 if (unlikely(istat & INFINIPATH_I_ERROR)) { 1063 ipath_stats.sps_errints++; 1064 estat = ipath_read_kreg64(dd, 1065 dd->ipath_kregs->kr_errorstatus); 1066 if (!estat) 1067 dev_info(&dd->pcidev->dev, "error interrupt (%x), " 1068 "but no error bits set!\n", istat); 1069 else if (estat == -1LL) 1070 /* 1071 * should we try clearing all, or hope next read 1072 * works? 1073 */ 1074 ipath_dev_err(dd, "Read of error status failed " 1075 "(all bits set); ignoring\n"); 1076 else 1077 if (handle_errors(dd, estat)) 1078 /* force calling ipath_kreceive() */ 1079 chk0rcv = 1; 1080 } 1081 1082 if (istat & INFINIPATH_I_GPIO) { 1083 /* 1084 * GPIO interrupts fall in two broad classes: 1085 * GPIO_2 indicates (on some HT4xx boards) that a packet 1086 * has arrived for Port 0. Checking for this 1087 * is controlled by flag IPATH_GPIO_INTR. 1088 * GPIO_3..5 on IBA6120 Rev2 chips indicate errors 1089 * that we need to count. Checking for this 1090 * is controlled by flag IPATH_GPIO_ERRINTRS. 1091 */ 1092 u32 gpiostatus; 1093 u32 to_clear = 0; 1094 1095 gpiostatus = ipath_read_kreg32( 1096 dd, dd->ipath_kregs->kr_gpio_status); 1097 /* First the error-counter case. 1098 */ 1099 if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) && 1100 (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) { 1101 /* want to clear the bits we see asserted. */ 1102 to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK); 1103 1104 /* 1105 * Count appropriately, clear bits out of our copy, 1106 * as they have been "handled". 1107 */ 1108 if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) { 1109 ipath_dbg("FlowCtl on UnsupVL\n"); 1110 dd->ipath_rxfc_unsupvl_errs++; 1111 } 1112 if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) { 1113 ipath_dbg("Overrun Threshold exceeded\n"); 1114 dd->ipath_overrun_thresh_errs++; 1115 } 1116 if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) { 1117 ipath_dbg("Local Link Integrity error\n"); 1118 dd->ipath_lli_errs++; 1119 } 1120 gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK; 1121 } 1122 /* Now the Port0 Receive case */ 1123 if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) && 1124 (dd->ipath_flags & IPATH_GPIO_INTR)) { 1125 /* 1126 * GPIO status bit 2 is set, and we expected it. 1127 * clear it and indicate in p0bits. 1128 * This probably only happens if a Port0 pkt 1129 * arrives at _just_ the wrong time, and we 1130 * handle that by seting chk0rcv; 1131 */ 1132 to_clear |= (1 << IPATH_GPIO_PORT0_BIT); 1133 gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT); 1134 chk0rcv = 1; 1135 } 1136 if (gpiostatus) { 1137 /* 1138 * Some unexpected bits remain. If they could have 1139 * caused the interrupt, complain and clear. 1140 * MEA: this is almost certainly non-ideal. 1141 * we should look into auto-disable of unexpected 1142 * GPIO interrupts, possibly on a "three strikes" 1143 * basis. 1144 */ 1145 const u32 mask = (u32) dd->ipath_gpio_mask; 1146 1147 if (mask & gpiostatus) { 1148 ipath_dbg("Unexpected GPIO IRQ bits %x\n", 1149 gpiostatus & mask); 1150 to_clear |= (gpiostatus & mask); 1151 } 1152 } 1153 if (to_clear) { 1154 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear, 1155 (u64) to_clear); 1156 } 1157 } 1158 chk0rcv |= istat & port0rbits; 1159 1160 /* 1161 * Clear the interrupt bits we found set, unless they are receive 1162 * related, in which case we already cleared them above, and don't 1163 * want to clear them again, because we might lose an interrupt. 1164 * Clear it early, so we "know" know the chip will have seen this by 1165 * the time we process the queue, and will re-interrupt if necessary. 1166 * The processor itself won't take the interrupt again until we return. 1167 */ 1168 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat); 1169 1170 /* 1171 * handle port0 receive before checking for pio buffers available, 1172 * since receives can overflow; piobuf waiters can afford a few 1173 * extra cycles, since they were waiting anyway, and user's waiting 1174 * for receive are at the bottom. 1175 */ 1176 if (chk0rcv) { 1177 ipath_kreceive(dd); 1178 istat &= ~port0rbits; 1179 } 1180 1181 if (istat & ((dd->ipath_i_rcvavail_mask << 1182 INFINIPATH_I_RCVAVAIL_SHIFT) 1183 | (dd->ipath_i_rcvurg_mask << 1184 INFINIPATH_I_RCVURG_SHIFT))) 1185 handle_urcv(dd, istat); 1186 1187 if (istat & INFINIPATH_I_SPIOBUFAVAIL) { 1188 clear_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl); 1189 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 1190 dd->ipath_sendctrl); 1191 1192 if (dd->ipath_portpiowait) 1193 handle_port_pioavail(dd); 1194 1195 handle_layer_pioavail(dd); 1196 } 1197 1198 ret = IRQ_HANDLED; 1199 1200bail: 1201 return ret; 1202} 1203