ipath_intr.c revision 9355fb6a064723c71e80e9c78de3140b43bfb52d
1/* 2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved. 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34#include <linux/pci.h> 35#include <linux/delay.h> 36 37#include "ipath_kernel.h" 38#include "ipath_verbs.h" 39#include "ipath_common.h" 40 41/* 42 * clear (write) a pio buffer, to clear a parity error. This routine 43 * should only be called when in freeze mode, and the buffer should be 44 * canceled afterwards. 45 */ 46static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum) 47{ 48 u32 __iomem *pbuf; 49 u32 dwcnt; /* dword count to write */ 50 if (pnum < dd->ipath_piobcnt2k) { 51 pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum * 52 dd->ipath_palign); 53 dwcnt = dd->ipath_piosize2k >> 2; 54 } 55 else { 56 pbuf = (u32 __iomem *) (dd->ipath_pio4kbase + 57 (pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign); 58 dwcnt = dd->ipath_piosize4k >> 2; 59 } 60 dev_info(&dd->pcidev->dev, 61 "Rewrite PIO buffer %u, to recover from parity error\n", 62 pnum); 63 64 /* no flush required, since already in freeze */ 65 writel(dwcnt + 1, pbuf); 66 while (--dwcnt) 67 writel(0, pbuf++); 68} 69 70/* 71 * Called when we might have an error that is specific to a particular 72 * PIO buffer, and may need to cancel that buffer, so it can be re-used. 73 * If rewrite is true, and bits are set in the sendbufferror registers, 74 * we'll write to the buffer, for error recovery on parity errors. 75 */ 76static void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite) 77{ 78 u32 piobcnt; 79 unsigned long sbuf[4]; 80 /* 81 * it's possible that sendbuffererror could have bits set; might 82 * have already done this as a result of hardware error handling 83 */ 84 piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; 85 /* read these before writing errorclear */ 86 sbuf[0] = ipath_read_kreg64( 87 dd, dd->ipath_kregs->kr_sendbuffererror); 88 sbuf[1] = ipath_read_kreg64( 89 dd, dd->ipath_kregs->kr_sendbuffererror + 1); 90 if (piobcnt > 128) { 91 sbuf[2] = ipath_read_kreg64( 92 dd, dd->ipath_kregs->kr_sendbuffererror + 2); 93 sbuf[3] = ipath_read_kreg64( 94 dd, dd->ipath_kregs->kr_sendbuffererror + 3); 95 } 96 97 if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) { 98 int i; 99 if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) && 100 dd->ipath_lastcancel > jiffies) { 101 __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG, 102 "SendbufErrs %lx %lx", sbuf[0], 103 sbuf[1]); 104 if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128) 105 printk(" %lx %lx ", sbuf[2], sbuf[3]); 106 printk("\n"); 107 } 108 109 for (i = 0; i < piobcnt; i++) 110 if (test_bit(i, sbuf)) { 111 if (rewrite) 112 ipath_clrpiobuf(dd, i); 113 ipath_disarm_piobufs(dd, i, 1); 114 } 115 /* ignore armlaunch errs for a bit */ 116 dd->ipath_lastcancel = jiffies+3; 117 } 118} 119 120 121/* These are all rcv-related errors which we want to count for stats */ 122#define E_SUM_PKTERRS \ 123 (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \ 124 INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \ 125 INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \ 126 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \ 127 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \ 128 INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP) 129 130/* These are all send-related errors which we want to count for stats */ 131#define E_SUM_ERRS \ 132 (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \ 133 INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 134 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \ 135 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ 136 INFINIPATH_E_INVALIDADDR) 137 138/* 139 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore 140 * errors not related to freeze and cancelling buffers. Can't ignore 141 * armlaunch because could get more while still cleaning up, and need 142 * to cancel those as they happen. 143 */ 144#define E_SPKT_ERRS_IGNORE \ 145 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 146 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SMINPKTLEN | \ 147 INFINIPATH_E_SPKTLEN) 148 149/* 150 * these are errors that can occur when the link changes state while 151 * a packet is being sent or received. This doesn't cover things 152 * like EBP or VCRC that can be the result of a sending having the 153 * link change state, so we receive a "known bad" packet. 154 */ 155#define E_SUM_LINK_PKTERRS \ 156 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 157 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ 158 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \ 159 INFINIPATH_E_RUNEXPCHAR) 160 161static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs) 162{ 163 u64 ignore_this_time = 0; 164 165 ipath_disarm_senderrbufs(dd, 0); 166 if ((errs & E_SUM_LINK_PKTERRS) && 167 !(dd->ipath_flags & IPATH_LINKACTIVE)) { 168 /* 169 * This can happen when SMA is trying to bring the link 170 * up, but the IB link changes state at the "wrong" time. 171 * The IB logic then complains that the packet isn't 172 * valid. We don't want to confuse people, so we just 173 * don't print them, except at debug 174 */ 175 ipath_dbg("Ignoring packet errors %llx, because link not " 176 "ACTIVE\n", (unsigned long long) errs); 177 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 178 } 179 180 return ignore_this_time; 181} 182 183/* generic hw error messages... */ 184#define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \ 185 { \ 186 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \ 187 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \ 188 .msg = "TXE " #a " Memory Parity" \ 189 } 190#define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \ 191 { \ 192 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \ 193 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \ 194 .msg = "RXE " #a " Memory Parity" \ 195 } 196 197static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = { 198 INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"), 199 INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"), 200 201 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF), 202 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC), 203 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO), 204 205 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF), 206 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ), 207 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID), 208 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID), 209 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF), 210 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO), 211 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO), 212}; 213 214/** 215 * ipath_format_hwmsg - format a single hwerror message 216 * @msg message buffer 217 * @msgl length of message buffer 218 * @hwmsg message to add to message buffer 219 */ 220static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg) 221{ 222 strlcat(msg, "[", msgl); 223 strlcat(msg, hwmsg, msgl); 224 strlcat(msg, "]", msgl); 225} 226 227/** 228 * ipath_format_hwerrors - format hardware error messages for display 229 * @hwerrs hardware errors bit vector 230 * @hwerrmsgs hardware error descriptions 231 * @nhwerrmsgs number of hwerrmsgs 232 * @msg message buffer 233 * @msgl message buffer length 234 */ 235void ipath_format_hwerrors(u64 hwerrs, 236 const struct ipath_hwerror_msgs *hwerrmsgs, 237 size_t nhwerrmsgs, 238 char *msg, size_t msgl) 239{ 240 int i; 241 const int glen = 242 sizeof(ipath_generic_hwerror_msgs) / 243 sizeof(ipath_generic_hwerror_msgs[0]); 244 245 for (i=0; i<glen; i++) { 246 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) { 247 ipath_format_hwmsg(msg, msgl, 248 ipath_generic_hwerror_msgs[i].msg); 249 } 250 } 251 252 for (i=0; i<nhwerrmsgs; i++) { 253 if (hwerrs & hwerrmsgs[i].mask) { 254 ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg); 255 } 256 } 257} 258 259/* return the strings for the most common link states */ 260static char *ib_linkstate(struct ipath_devdata *dd, u64 ibcs) 261{ 262 char *ret; 263 u32 state; 264 265 state = ipath_ib_state(dd, ibcs); 266 if (state == dd->ib_init) 267 ret = "Init"; 268 else if (state == dd->ib_arm) 269 ret = "Arm"; 270 else if (state == dd->ib_active) 271 ret = "Active"; 272 else 273 ret = "Down"; 274 return ret; 275} 276 277void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev) 278{ 279 struct ib_event event; 280 281 event.device = &dd->verbs_dev->ibdev; 282 event.element.port_num = 1; 283 event.event = ev; 284 ib_dispatch_event(&event); 285} 286 287static void handle_e_ibstatuschanged(struct ipath_devdata *dd, 288 ipath_err_t errs) 289{ 290 u32 ltstate, lstate, ibstate, lastlstate; 291 u32 init = dd->ib_init; 292 u32 arm = dd->ib_arm; 293 u32 active = dd->ib_active; 294 const u64 ibcs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus); 295 296 lstate = ipath_ib_linkstate(dd, ibcs); /* linkstate */ 297 ibstate = ipath_ib_state(dd, ibcs); 298 /* linkstate at last interrupt */ 299 lastlstate = ipath_ib_linkstate(dd, dd->ipath_lastibcstat); 300 ltstate = ipath_ib_linktrstate(dd, ibcs); /* linktrainingtate */ 301 302 /* 303 * if linkstate transitions into INIT from any of the various down 304 * states, or if it transitions from any of the up (INIT or better) 305 * states into any of the down states (except link recovery), then 306 * call the chip-specific code to take appropriate actions. 307 */ 308 if (lstate >= INFINIPATH_IBCS_L_STATE_INIT && 309 lastlstate == INFINIPATH_IBCS_L_STATE_DOWN) { 310 /* transitioned to UP */ 311 if (dd->ipath_f_ib_updown(dd, 1, ibcs)) { 312 /* link came up, so we must no longer be disabled */ 313 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED; 314 ipath_cdbg(LINKVERB, "LinkUp handled, skipped\n"); 315 goto skip_ibchange; /* chip-code handled */ 316 } 317 } else if ((lastlstate >= INFINIPATH_IBCS_L_STATE_INIT || 318 (dd->ipath_flags & IPATH_IB_FORCE_NOTIFY)) && 319 ltstate <= INFINIPATH_IBCS_LT_STATE_CFGDEBOUNCE && 320 ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) { 321 int handled; 322 handled = dd->ipath_f_ib_updown(dd, 0, ibcs); 323 dd->ipath_flags &= ~IPATH_IB_FORCE_NOTIFY; 324 if (handled) { 325 ipath_cdbg(LINKVERB, "LinkDown handled, skipped\n"); 326 goto skip_ibchange; /* chip-code handled */ 327 } 328 } 329 330 /* 331 * Significant enough to always print and get into logs, if it was 332 * unexpected. If it was a requested state change, we'll have 333 * already cleared the flags, so we won't print this warning 334 */ 335 if ((ibstate != arm && ibstate != active) && 336 (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) { 337 dev_info(&dd->pcidev->dev, "Link state changed from %s " 338 "to %s\n", (dd->ipath_flags & IPATH_LINKARMED) ? 339 "ARM" : "ACTIVE", ib_linkstate(dd, ibcs)); 340 } 341 342 if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE || 343 ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) { 344 u32 lastlts; 345 lastlts = ipath_ib_linktrstate(dd, dd->ipath_lastibcstat); 346 /* 347 * Ignore cycling back and forth from Polling.Active to 348 * Polling.Quiet while waiting for the other end of the link 349 * to come up, except to try and decide if we are connected 350 * to a live IB device or not. We will cycle back and 351 * forth between them if no cable is plugged in, the other 352 * device is powered off or disabled, etc. 353 */ 354 if (lastlts == INFINIPATH_IBCS_LT_STATE_POLLACTIVE || 355 lastlts == INFINIPATH_IBCS_LT_STATE_POLLQUIET) { 356 if (++dd->ipath_ibpollcnt == 40) { 357 dd->ipath_flags |= IPATH_NOCABLE; 358 *dd->ipath_statusp |= 359 IPATH_STATUS_IB_NOCABLE; 360 ipath_cdbg(LINKVERB, "Set NOCABLE\n"); 361 } 362 ipath_cdbg(LINKVERB, "POLL change to %s (%x)\n", 363 ipath_ibcstatus_str[ltstate], ibstate); 364 goto skip_ibchange; 365 } 366 } 367 368 dd->ipath_ibpollcnt = 0; /* not poll*, now */ 369 ipath_stats.sps_iblink++; 370 371 if (ibstate != init && dd->ipath_lastlinkrecov && ipath_linkrecovery) { 372 u64 linkrecov; 373 linkrecov = ipath_snap_cntr(dd, 374 dd->ipath_cregs->cr_iblinkerrrecovcnt); 375 if (linkrecov != dd->ipath_lastlinkrecov) { 376 ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n", 377 ibcs, ib_linkstate(dd, ibcs), 378 ipath_ibcstatus_str[ltstate], 379 linkrecov); 380 /* and no more until active again */ 381 dd->ipath_lastlinkrecov = 0; 382 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN); 383 goto skip_ibchange; 384 } 385 } 386 387 if (ibstate == init || ibstate == arm || ibstate == active) { 388 *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE; 389 if (ibstate == init || ibstate == arm) { 390 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 391 if (dd->ipath_flags & IPATH_LINKACTIVE) 392 signal_ib_event(dd, IB_EVENT_PORT_ERR); 393 } 394 if (ibstate == arm) { 395 dd->ipath_flags |= IPATH_LINKARMED; 396 dd->ipath_flags &= ~(IPATH_LINKUNK | 397 IPATH_LINKINIT | IPATH_LINKDOWN | 398 IPATH_LINKACTIVE | IPATH_NOCABLE); 399 ipath_hol_down(dd); 400 } else if (ibstate == init) { 401 /* 402 * set INIT and DOWN. Down is checked by 403 * most of the other code, but INIT is 404 * useful to know in a few places. 405 */ 406 dd->ipath_flags |= IPATH_LINKINIT | 407 IPATH_LINKDOWN; 408 dd->ipath_flags &= ~(IPATH_LINKUNK | 409 IPATH_LINKARMED | IPATH_LINKACTIVE | 410 IPATH_NOCABLE); 411 ipath_hol_down(dd); 412 } else { /* active */ 413 dd->ipath_lastlinkrecov = ipath_snap_cntr(dd, 414 dd->ipath_cregs->cr_iblinkerrrecovcnt); 415 *dd->ipath_statusp |= 416 IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF; 417 dd->ipath_flags |= IPATH_LINKACTIVE; 418 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 419 | IPATH_LINKDOWN | IPATH_LINKARMED | 420 IPATH_NOCABLE); 421 signal_ib_event(dd, IB_EVENT_PORT_ACTIVE); 422 /* LED active not handled in chip _f_updown */ 423 dd->ipath_f_setextled(dd, lstate, ltstate); 424 ipath_hol_up(dd); 425 } 426 427 /* 428 * print after we've already done the work, so as not to 429 * delay the state changes and notifications, for debugging 430 */ 431 if (lstate == lastlstate) 432 ipath_cdbg(LINKVERB, "Unchanged from last: %s " 433 "(%x)\n", ib_linkstate(dd, ibcs), ibstate); 434 else 435 ipath_cdbg(VERBOSE, "Unit %u: link up to %s %s (%x)\n", 436 dd->ipath_unit, ib_linkstate(dd, ibcs), 437 ipath_ibcstatus_str[ltstate], ibstate); 438 } else { /* down */ 439 if (dd->ipath_flags & IPATH_LINKACTIVE) 440 signal_ib_event(dd, IB_EVENT_PORT_ERR); 441 dd->ipath_flags |= IPATH_LINKDOWN; 442 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 443 | IPATH_LINKACTIVE | 444 IPATH_LINKARMED); 445 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 446 dd->ipath_lli_counter = 0; 447 448 if (lastlstate != INFINIPATH_IBCS_L_STATE_DOWN) 449 ipath_cdbg(VERBOSE, "Unit %u link state down " 450 "(state 0x%x), from %s\n", 451 dd->ipath_unit, lstate, 452 ib_linkstate(dd, dd->ipath_lastibcstat)); 453 else 454 ipath_cdbg(LINKVERB, "Unit %u link state changed " 455 "to %s (0x%x) from down (%x)\n", 456 dd->ipath_unit, 457 ipath_ibcstatus_str[ltstate], 458 ibstate, lastlstate); 459 } 460 461skip_ibchange: 462 dd->ipath_lastibcstat = ibcs; 463} 464 465static void handle_supp_msgs(struct ipath_devdata *dd, 466 unsigned supp_msgs, char *msg, int msgsz) 467{ 468 /* 469 * Print the message unless it's ibc status change only, which 470 * happens so often we never want to count it. 471 */ 472 if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) { 473 int iserr; 474 iserr = ipath_decode_err(msg, msgsz, 475 dd->ipath_lasterror & 476 ~INFINIPATH_E_IBSTATUSCHANGED); 477 if (dd->ipath_lasterror & 478 ~(INFINIPATH_E_RRCVEGRFULL | 479 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) 480 ipath_dev_err(dd, "Suppressed %u messages for " 481 "fast-repeating errors (%s) (%llx)\n", 482 supp_msgs, msg, 483 (unsigned long long) 484 dd->ipath_lasterror); 485 else { 486 /* 487 * rcvegrfull and rcvhdrqfull are "normal", for some 488 * types of processes (mostly benchmarks) that send 489 * huge numbers of messages, while not processing 490 * them. So only complain about these at debug 491 * level. 492 */ 493 if (iserr) 494 ipath_dbg("Suppressed %u messages for %s\n", 495 supp_msgs, msg); 496 else 497 ipath_cdbg(ERRPKT, 498 "Suppressed %u messages for %s\n", 499 supp_msgs, msg); 500 } 501 } 502} 503 504static unsigned handle_frequent_errors(struct ipath_devdata *dd, 505 ipath_err_t errs, char *msg, 506 int msgsz, int *noprint) 507{ 508 unsigned long nc; 509 static unsigned long nextmsg_time; 510 static unsigned nmsgs, supp_msgs; 511 512 /* 513 * Throttle back "fast" messages to no more than 10 per 5 seconds. 514 * This isn't perfect, but it's a reasonable heuristic. If we get 515 * more than 10, give a 6x longer delay. 516 */ 517 nc = jiffies; 518 if (nmsgs > 10) { 519 if (time_before(nc, nextmsg_time)) { 520 *noprint = 1; 521 if (!supp_msgs++) 522 nextmsg_time = nc + HZ * 3; 523 } 524 else if (supp_msgs) { 525 handle_supp_msgs(dd, supp_msgs, msg, msgsz); 526 supp_msgs = 0; 527 nmsgs = 0; 528 } 529 } 530 else if (!nmsgs++ || time_after(nc, nextmsg_time)) 531 nextmsg_time = nc + HZ / 2; 532 533 return supp_msgs; 534} 535 536static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs) 537{ 538 char msg[128]; 539 u64 ignore_this_time = 0; 540 int i, iserr = 0; 541 int chkerrpkts = 0, noprint = 0; 542 unsigned supp_msgs; 543 int log_idx; 544 545 supp_msgs = handle_frequent_errors(dd, errs, msg, sizeof msg, &noprint); 546 547 /* don't report errors that are masked */ 548 errs &= ~dd->ipath_maskederrs; 549 550 /* do these first, they are most important */ 551 if (errs & INFINIPATH_E_HARDWARE) { 552 /* reuse same msg buf */ 553 dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg); 554 } else { 555 u64 mask; 556 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) { 557 mask = dd->ipath_eep_st_masks[log_idx].errs_to_log; 558 if (errs & mask) 559 ipath_inc_eeprom_err(dd, log_idx, 1); 560 } 561 } 562 563 if (!noprint && (errs & ~dd->ipath_e_bitsextant)) 564 ipath_dev_err(dd, "error interrupt with unknown errors " 565 "%llx set\n", (unsigned long long) 566 (errs & ~dd->ipath_e_bitsextant)); 567 568 if (errs & E_SUM_ERRS) 569 ignore_this_time = handle_e_sum_errs(dd, errs); 570 else if ((errs & E_SUM_LINK_PKTERRS) && 571 !(dd->ipath_flags & IPATH_LINKACTIVE)) { 572 /* 573 * This can happen when SMA is trying to bring the link 574 * up, but the IB link changes state at the "wrong" time. 575 * The IB logic then complains that the packet isn't 576 * valid. We don't want to confuse people, so we just 577 * don't print them, except at debug 578 */ 579 ipath_dbg("Ignoring packet errors %llx, because link not " 580 "ACTIVE\n", (unsigned long long) errs); 581 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 582 } 583 584 if (supp_msgs == 250000) { 585 int s_iserr; 586 /* 587 * It's not entirely reasonable assuming that the errors set 588 * in the last clear period are all responsible for the 589 * problem, but the alternative is to assume it's the only 590 * ones on this particular interrupt, which also isn't great 591 */ 592 dd->ipath_maskederrs |= dd->ipath_lasterror | errs; 593 594 dd->ipath_errormask &= ~dd->ipath_maskederrs; 595 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 596 dd->ipath_errormask); 597 s_iserr = ipath_decode_err(msg, sizeof msg, 598 dd->ipath_maskederrs); 599 600 if (dd->ipath_maskederrs & 601 ~(INFINIPATH_E_RRCVEGRFULL | 602 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) 603 ipath_dev_err(dd, "Temporarily disabling " 604 "error(s) %llx reporting; too frequent (%s)\n", 605 (unsigned long long) dd->ipath_maskederrs, 606 msg); 607 else { 608 /* 609 * rcvegrfull and rcvhdrqfull are "normal", 610 * for some types of processes (mostly benchmarks) 611 * that send huge numbers of messages, while not 612 * processing them. So only complain about 613 * these at debug level. 614 */ 615 if (s_iserr) 616 ipath_dbg("Temporarily disabling reporting " 617 "too frequent queue full errors (%s)\n", 618 msg); 619 else 620 ipath_cdbg(ERRPKT, 621 "Temporarily disabling reporting too" 622 " frequent packet errors (%s)\n", 623 msg); 624 } 625 626 /* 627 * Re-enable the masked errors after around 3 minutes. in 628 * ipath_get_faststats(). If we have a series of fast 629 * repeating but different errors, the interval will keep 630 * stretching out, but that's OK, as that's pretty 631 * catastrophic. 632 */ 633 dd->ipath_unmasktime = jiffies + HZ * 180; 634 } 635 636 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs); 637 if (ignore_this_time) 638 errs &= ~ignore_this_time; 639 if (errs & ~dd->ipath_lasterror) { 640 errs &= ~dd->ipath_lasterror; 641 /* never suppress duplicate hwerrors or ibstatuschange */ 642 dd->ipath_lasterror |= errs & 643 ~(INFINIPATH_E_HARDWARE | 644 INFINIPATH_E_IBSTATUSCHANGED); 645 } 646 647 /* likely due to cancel, so suppress */ 648 if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) && 649 dd->ipath_lastcancel > jiffies) { 650 ipath_dbg("Suppressed armlaunch/spktlen after error send cancel\n"); 651 errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN); 652 } 653 654 if (!errs) 655 return 0; 656 657 if (!noprint) 658 /* 659 * the ones we mask off are handled specially below or above 660 */ 661 ipath_decode_err(msg, sizeof msg, 662 errs & ~(INFINIPATH_E_IBSTATUSCHANGED | 663 INFINIPATH_E_RRCVEGRFULL | 664 INFINIPATH_E_RRCVHDRFULL | 665 INFINIPATH_E_HARDWARE)); 666 else 667 /* so we don't need if (!noprint) at strlcat's below */ 668 *msg = 0; 669 670 if (errs & E_SUM_PKTERRS) { 671 ipath_stats.sps_pkterrs++; 672 chkerrpkts = 1; 673 } 674 if (errs & E_SUM_ERRS) 675 ipath_stats.sps_errs++; 676 677 if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) { 678 ipath_stats.sps_crcerrs++; 679 chkerrpkts = 1; 680 } 681 iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS); 682 683 684 /* 685 * We don't want to print these two as they happen, or we can make 686 * the situation even worse, because it takes so long to print 687 * messages to serial consoles. Kernel ports get printed from 688 * fast_stats, no more than every 5 seconds, user ports get printed 689 * on close 690 */ 691 if (errs & INFINIPATH_E_RRCVHDRFULL) { 692 u32 hd, tl; 693 ipath_stats.sps_hdrqfull++; 694 for (i = 0; i < dd->ipath_cfgports; i++) { 695 struct ipath_portdata *pd = dd->ipath_pd[i]; 696 if (i == 0) { 697 hd = pd->port_head; 698 tl = ipath_get_hdrqtail(pd); 699 } else if (pd && pd->port_cnt && 700 pd->port_rcvhdrtail_kvaddr) { 701 /* 702 * don't report same point multiple times, 703 * except kernel 704 */ 705 tl = *(u64 *) pd->port_rcvhdrtail_kvaddr; 706 if (tl == pd->port_lastrcvhdrqtail) 707 continue; 708 hd = ipath_read_ureg32(dd, ur_rcvhdrhead, 709 i); 710 } else 711 continue; 712 if (hd == (tl + 1) || 713 (!hd && tl == dd->ipath_hdrqlast)) { 714 if (i == 0) 715 chkerrpkts = 1; 716 pd->port_lastrcvhdrqtail = tl; 717 pd->port_hdrqfull++; 718 /* flush hdrqfull so that poll() sees it */ 719 wmb(); 720 wake_up_interruptible(&pd->port_wait); 721 } 722 } 723 } 724 if (errs & INFINIPATH_E_RRCVEGRFULL) { 725 struct ipath_portdata *pd = dd->ipath_pd[0]; 726 727 /* 728 * since this is of less importance and not likely to 729 * happen without also getting hdrfull, only count 730 * occurrences; don't check each port (or even the kernel 731 * vs user) 732 */ 733 ipath_stats.sps_etidfull++; 734 if (pd->port_head != ipath_get_hdrqtail(pd)) 735 chkerrpkts = 1; 736 } 737 738 /* 739 * do this before IBSTATUSCHANGED, in case both bits set in a single 740 * interrupt; we want the STATUSCHANGE to "win", so we do our 741 * internal copy of state machine correctly 742 */ 743 if (errs & INFINIPATH_E_RIBLOSTLINK) { 744 /* 745 * force through block below 746 */ 747 errs |= INFINIPATH_E_IBSTATUSCHANGED; 748 ipath_stats.sps_iblink++; 749 dd->ipath_flags |= IPATH_LINKDOWN; 750 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 751 | IPATH_LINKARMED | IPATH_LINKACTIVE); 752 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 753 754 ipath_dbg("Lost link, link now down (%s)\n", 755 ipath_ibcstatus_str[ipath_read_kreg64(dd, 756 dd->ipath_kregs->kr_ibcstatus) & 0xf]); 757 } 758 if (errs & INFINIPATH_E_IBSTATUSCHANGED) 759 handle_e_ibstatuschanged(dd, errs); 760 761 if (errs & INFINIPATH_E_RESET) { 762 if (!noprint) 763 ipath_dev_err(dd, "Got reset, requires re-init " 764 "(unload and reload driver)\n"); 765 dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */ 766 /* mark as having had error */ 767 *dd->ipath_statusp |= IPATH_STATUS_HWERROR; 768 *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF; 769 } 770 771 if (!noprint && *msg) { 772 if (iserr) 773 ipath_dev_err(dd, "%s error\n", msg); 774 else 775 dev_info(&dd->pcidev->dev, "%s packet problems\n", 776 msg); 777 } 778 if (dd->ipath_state_wanted & dd->ipath_flags) { 779 ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, " 780 "waking\n", dd->ipath_state_wanted, 781 dd->ipath_flags); 782 wake_up_interruptible(&ipath_state_wait); 783 } 784 785 return chkerrpkts; 786} 787 788/* 789 * try to cleanup as much as possible for anything that might have gone 790 * wrong while in freeze mode, such as pio buffers being written by user 791 * processes (causing armlaunch), send errors due to going into freeze mode, 792 * etc., and try to avoid causing extra interrupts while doing so. 793 * Forcibly update the in-memory pioavail register copies after cleanup 794 * because the chip won't do it for anything changing while in freeze mode 795 * (we don't want to wait for the next pio buffer state change). 796 * Make sure that we don't lose any important interrupts by using the chip 797 * feature that says that writing 0 to a bit in *clear that is set in 798 * *status will cause an interrupt to be generated again (if allowed by 799 * the *mask value). 800 */ 801void ipath_clear_freeze(struct ipath_devdata *dd) 802{ 803 int i, im; 804 u64 val; 805 806 /* disable error interrupts, to avoid confusion */ 807 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 0ULL); 808 809 /* also disable interrupts; errormask is sometimes overwriten */ 810 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); 811 812 /* 813 * clear all sends, because they have may been 814 * completed by usercode while in freeze mode, and 815 * therefore would not be sent, and eventually 816 * might cause the process to run out of bufs 817 */ 818 ipath_cancel_sends(dd, 0); 819 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 820 dd->ipath_control); 821 822 /* ensure pio avail updates continue */ 823 ipath_force_pio_avail_update(dd); 824 825 /* 826 * We just enabled pioavailupdate, so dma copy is almost certainly 827 * not yet right, so read the registers directly. Similar to init 828 */ 829 for (i = 0; i < dd->ipath_pioavregs; i++) { 830 /* deal with 6110 chip bug */ 831 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ? 832 i ^ 1 : i; 833 val = ipath_read_kreg64(dd, (0x1000 / sizeof(u64)) + im); 834 dd->ipath_pioavailregs_dma[i] = cpu_to_le64(val); 835 dd->ipath_pioavailshadow[i] = val | 836 (~dd->ipath_pioavailkernel[i] << 837 INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT); 838 } 839 840 /* 841 * force new interrupt if any hwerr, error or interrupt bits are 842 * still set, and clear "safe" send packet errors related to freeze 843 * and cancelling sends. Re-enable error interrupts before possible 844 * force of re-interrupt on pending interrupts. 845 */ 846 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 0ULL); 847 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, 848 E_SPKT_ERRS_IGNORE); 849 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 850 dd->ipath_errormask); 851 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, -1LL); 852 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL); 853} 854 855 856/* this is separate to allow for better optimization of ipath_intr() */ 857 858static noinline void ipath_bad_intr(struct ipath_devdata *dd, u32 *unexpectp) 859{ 860 /* 861 * sometimes happen during driver init and unload, don't want 862 * to process any interrupts at that point 863 */ 864 865 /* this is just a bandaid, not a fix, if something goes badly 866 * wrong */ 867 if (++*unexpectp > 100) { 868 if (++*unexpectp > 105) { 869 /* 870 * ok, we must be taking somebody else's interrupts, 871 * due to a messed up mptable and/or PIRQ table, so 872 * unregister the interrupt. We've seen this during 873 * linuxbios development work, and it may happen in 874 * the future again. 875 */ 876 if (dd->pcidev && dd->ipath_irq) { 877 ipath_dev_err(dd, "Now %u unexpected " 878 "interrupts, unregistering " 879 "interrupt handler\n", 880 *unexpectp); 881 ipath_dbg("free_irq of irq %d\n", 882 dd->ipath_irq); 883 dd->ipath_f_free_irq(dd); 884 } 885 } 886 if (ipath_read_ireg(dd, dd->ipath_kregs->kr_intmask)) { 887 ipath_dev_err(dd, "%u unexpected interrupts, " 888 "disabling interrupts completely\n", 889 *unexpectp); 890 /* 891 * disable all interrupts, something is very wrong 892 */ 893 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 894 0ULL); 895 } 896 } else if (*unexpectp > 1) 897 ipath_dbg("Interrupt when not ready, should not happen, " 898 "ignoring\n"); 899} 900 901static noinline void ipath_bad_regread(struct ipath_devdata *dd) 902{ 903 static int allbits; 904 905 /* separate routine, for better optimization of ipath_intr() */ 906 907 /* 908 * We print the message and disable interrupts, in hope of 909 * having a better chance of debugging the problem. 910 */ 911 ipath_dev_err(dd, 912 "Read of interrupt status failed (all bits set)\n"); 913 if (allbits++) { 914 /* disable all interrupts, something is very wrong */ 915 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); 916 if (allbits == 2) { 917 ipath_dev_err(dd, "Still bad interrupt status, " 918 "unregistering interrupt\n"); 919 dd->ipath_f_free_irq(dd); 920 } else if (allbits > 2) { 921 if ((allbits % 10000) == 0) 922 printk("."); 923 } else 924 ipath_dev_err(dd, "Disabling interrupts, " 925 "multiple errors\n"); 926 } 927} 928 929static void handle_layer_pioavail(struct ipath_devdata *dd) 930{ 931 unsigned long flags; 932 int ret; 933 934 ret = ipath_ib_piobufavail(dd->verbs_dev); 935 if (ret > 0) 936 goto set; 937 938 return; 939set: 940 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); 941 dd->ipath_sendctrl |= INFINIPATH_S_PIOINTBUFAVAIL; 942 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 943 dd->ipath_sendctrl); 944 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); 945 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); 946} 947 948/* 949 * Handle receive interrupts for user ports; this means a user 950 * process was waiting for a packet to arrive, and didn't want 951 * to poll 952 */ 953static void handle_urcv(struct ipath_devdata *dd, u64 istat) 954{ 955 u64 portr; 956 int i; 957 int rcvdint = 0; 958 959 /* 960 * test_and_clear_bit(IPATH_PORT_WAITING_RCV) and 961 * test_and_clear_bit(IPATH_PORT_WAITING_URG) below 962 * would both like timely updates of the bits so that 963 * we don't pass them by unnecessarily. the rmb() 964 * here ensures that we see them promptly -- the 965 * corresponding wmb()'s are in ipath_poll_urgent() 966 * and ipath_poll_next()... 967 */ 968 rmb(); 969 portr = ((istat >> dd->ipath_i_rcvavail_shift) & 970 dd->ipath_i_rcvavail_mask) | 971 ((istat >> dd->ipath_i_rcvurg_shift) & 972 dd->ipath_i_rcvurg_mask); 973 for (i = 1; i < dd->ipath_cfgports; i++) { 974 struct ipath_portdata *pd = dd->ipath_pd[i]; 975 976 if (portr & (1 << i) && pd && pd->port_cnt) { 977 if (test_and_clear_bit(IPATH_PORT_WAITING_RCV, 978 &pd->port_flag)) { 979 clear_bit(i + dd->ipath_r_intravail_shift, 980 &dd->ipath_rcvctrl); 981 wake_up_interruptible(&pd->port_wait); 982 rcvdint = 1; 983 } else if (test_and_clear_bit(IPATH_PORT_WAITING_URG, 984 &pd->port_flag)) { 985 pd->port_urgent++; 986 wake_up_interruptible(&pd->port_wait); 987 } 988 } 989 } 990 if (rcvdint) { 991 /* only want to take one interrupt, so turn off the rcv 992 * interrupt for all the ports that we set the rcv_waiting 993 * (but never for kernel port) 994 */ 995 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 996 dd->ipath_rcvctrl); 997 } 998} 999 1000irqreturn_t ipath_intr(int irq, void *data) 1001{ 1002 struct ipath_devdata *dd = data; 1003 u32 istat, chk0rcv = 0; 1004 ipath_err_t estat = 0; 1005 irqreturn_t ret; 1006 static unsigned unexpected = 0; 1007 u64 kportrbits; 1008 1009 ipath_stats.sps_ints++; 1010 1011 if (dd->ipath_int_counter != (u32) -1) 1012 dd->ipath_int_counter++; 1013 1014 if (!(dd->ipath_flags & IPATH_PRESENT)) { 1015 /* 1016 * This return value is not great, but we do not want the 1017 * interrupt core code to remove our interrupt handler 1018 * because we don't appear to be handling an interrupt 1019 * during a chip reset. 1020 */ 1021 return IRQ_HANDLED; 1022 } 1023 1024 /* 1025 * this needs to be flags&initted, not statusp, so we keep 1026 * taking interrupts even after link goes down, etc. 1027 * Also, we *must* clear the interrupt at some point, or we won't 1028 * take it again, which can be real bad for errors, etc... 1029 */ 1030 1031 if (!(dd->ipath_flags & IPATH_INITTED)) { 1032 ipath_bad_intr(dd, &unexpected); 1033 ret = IRQ_NONE; 1034 goto bail; 1035 } 1036 1037 istat = ipath_read_ireg(dd, dd->ipath_kregs->kr_intstatus); 1038 1039 if (unlikely(!istat)) { 1040 ipath_stats.sps_nullintr++; 1041 ret = IRQ_NONE; /* not our interrupt, or already handled */ 1042 goto bail; 1043 } 1044 if (unlikely(istat == -1)) { 1045 ipath_bad_regread(dd); 1046 /* don't know if it was our interrupt or not */ 1047 ret = IRQ_NONE; 1048 goto bail; 1049 } 1050 1051 if (unexpected) 1052 unexpected = 0; 1053 1054 if (unlikely(istat & ~dd->ipath_i_bitsextant)) 1055 ipath_dev_err(dd, 1056 "interrupt with unknown interrupts %x set\n", 1057 istat & (u32) ~ dd->ipath_i_bitsextant); 1058 else 1059 ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat); 1060 1061 if (unlikely(istat & INFINIPATH_I_ERROR)) { 1062 ipath_stats.sps_errints++; 1063 estat = ipath_read_kreg64(dd, 1064 dd->ipath_kregs->kr_errorstatus); 1065 if (!estat) 1066 dev_info(&dd->pcidev->dev, "error interrupt (%x), " 1067 "but no error bits set!\n", istat); 1068 else if (estat == -1LL) 1069 /* 1070 * should we try clearing all, or hope next read 1071 * works? 1072 */ 1073 ipath_dev_err(dd, "Read of error status failed " 1074 "(all bits set); ignoring\n"); 1075 else 1076 chk0rcv |= handle_errors(dd, estat); 1077 } 1078 1079 if (istat & INFINIPATH_I_GPIO) { 1080 /* 1081 * GPIO interrupts fall in two broad classes: 1082 * GPIO_2 indicates (on some HT4xx boards) that a packet 1083 * has arrived for Port 0. Checking for this 1084 * is controlled by flag IPATH_GPIO_INTR. 1085 * GPIO_3..5 on IBA6120 Rev2 and IBA6110 Rev4 chips indicate 1086 * errors that we need to count. Checking for this 1087 * is controlled by flag IPATH_GPIO_ERRINTRS. 1088 */ 1089 u32 gpiostatus; 1090 u32 to_clear = 0; 1091 1092 gpiostatus = ipath_read_kreg32( 1093 dd, dd->ipath_kregs->kr_gpio_status); 1094 /* First the error-counter case. */ 1095 if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) && 1096 (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) { 1097 /* want to clear the bits we see asserted. */ 1098 to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK); 1099 1100 /* 1101 * Count appropriately, clear bits out of our copy, 1102 * as they have been "handled". 1103 */ 1104 if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) { 1105 ipath_dbg("FlowCtl on UnsupVL\n"); 1106 dd->ipath_rxfc_unsupvl_errs++; 1107 } 1108 if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) { 1109 ipath_dbg("Overrun Threshold exceeded\n"); 1110 dd->ipath_overrun_thresh_errs++; 1111 } 1112 if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) { 1113 ipath_dbg("Local Link Integrity error\n"); 1114 dd->ipath_lli_errs++; 1115 } 1116 gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK; 1117 } 1118 /* Now the Port0 Receive case */ 1119 if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) && 1120 (dd->ipath_flags & IPATH_GPIO_INTR)) { 1121 /* 1122 * GPIO status bit 2 is set, and we expected it. 1123 * clear it and indicate in p0bits. 1124 * This probably only happens if a Port0 pkt 1125 * arrives at _just_ the wrong time, and we 1126 * handle that by seting chk0rcv; 1127 */ 1128 to_clear |= (1 << IPATH_GPIO_PORT0_BIT); 1129 gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT); 1130 chk0rcv = 1; 1131 } 1132 if (gpiostatus) { 1133 /* 1134 * Some unexpected bits remain. If they could have 1135 * caused the interrupt, complain and clear. 1136 * To avoid repetition of this condition, also clear 1137 * the mask. It is almost certainly due to error. 1138 */ 1139 const u32 mask = (u32) dd->ipath_gpio_mask; 1140 1141 if (mask & gpiostatus) { 1142 ipath_dbg("Unexpected GPIO IRQ bits %x\n", 1143 gpiostatus & mask); 1144 to_clear |= (gpiostatus & mask); 1145 dd->ipath_gpio_mask &= ~(gpiostatus & mask); 1146 ipath_write_kreg(dd, 1147 dd->ipath_kregs->kr_gpio_mask, 1148 dd->ipath_gpio_mask); 1149 } 1150 } 1151 if (to_clear) { 1152 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear, 1153 (u64) to_clear); 1154 } 1155 } 1156 1157 /* 1158 * Clear the interrupt bits we found set, unless they are receive 1159 * related, in which case we already cleared them above, and don't 1160 * want to clear them again, because we might lose an interrupt. 1161 * Clear it early, so we "know" know the chip will have seen this by 1162 * the time we process the queue, and will re-interrupt if necessary. 1163 * The processor itself won't take the interrupt again until we return. 1164 */ 1165 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat); 1166 1167 /* 1168 * Handle kernel receive queues before checking for pio buffers 1169 * available since receives can overflow; piobuf waiters can afford 1170 * a few extra cycles, since they were waiting anyway, and user's 1171 * waiting for receive are at the bottom. 1172 */ 1173 kportrbits = (1ULL << dd->ipath_i_rcvavail_shift) | 1174 (1ULL << dd->ipath_i_rcvurg_shift); 1175 if (chk0rcv || (istat & kportrbits)) { 1176 istat &= ~kportrbits; 1177 ipath_kreceive(dd->ipath_pd[0]); 1178 } 1179 1180 if (istat & ((dd->ipath_i_rcvavail_mask << dd->ipath_i_rcvavail_shift) | 1181 (dd->ipath_i_rcvurg_mask << dd->ipath_i_rcvurg_shift))) 1182 handle_urcv(dd, istat); 1183 1184 if (istat & INFINIPATH_I_SPIOBUFAVAIL) { 1185 unsigned long flags; 1186 1187 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); 1188 dd->ipath_sendctrl &= ~INFINIPATH_S_PIOINTBUFAVAIL; 1189 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 1190 dd->ipath_sendctrl); 1191 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); 1192 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); 1193 1194 handle_layer_pioavail(dd); 1195 } 1196 1197 ret = IRQ_HANDLED; 1198 1199bail: 1200 return ret; 1201} 1202