ipath_intr.c revision 9380068fc2f230e7840ff87d3f1e6030ae2ee5e8
1/* 2 * Copyright (c) 2006 QLogic, Inc. All rights reserved. 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34#include <linux/pci.h> 35 36#include "ipath_kernel.h" 37#include "ipath_verbs.h" 38#include "ipath_common.h" 39 40/* 41 * clear (write) a pio buffer, to clear a parity error. This routine 42 * should only be called when in freeze mode, and the buffer should be 43 * canceled afterwards. 44 */ 45static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum) 46{ 47 u32 __iomem *pbuf; 48 u32 dwcnt; /* dword count to write */ 49 if (pnum < dd->ipath_piobcnt2k) { 50 pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum * 51 dd->ipath_palign); 52 dwcnt = dd->ipath_piosize2k >> 2; 53 } 54 else { 55 pbuf = (u32 __iomem *) (dd->ipath_pio4kbase + 56 (pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign); 57 dwcnt = dd->ipath_piosize4k >> 2; 58 } 59 dev_info(&dd->pcidev->dev, 60 "Rewrite PIO buffer %u, to recover from parity error\n", 61 pnum); 62 *pbuf = dwcnt+1; /* no flush required, since already in freeze */ 63 while(--dwcnt) 64 *pbuf++ = 0; 65} 66 67/* 68 * Called when we might have an error that is specific to a particular 69 * PIO buffer, and may need to cancel that buffer, so it can be re-used. 70 * If rewrite is true, and bits are set in the sendbufferror registers, 71 * we'll write to the buffer, for error recovery on parity errors. 72 */ 73void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite) 74{ 75 u32 piobcnt; 76 unsigned long sbuf[4]; 77 /* 78 * it's possible that sendbuffererror could have bits set; might 79 * have already done this as a result of hardware error handling 80 */ 81 piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; 82 /* read these before writing errorclear */ 83 sbuf[0] = ipath_read_kreg64( 84 dd, dd->ipath_kregs->kr_sendbuffererror); 85 sbuf[1] = ipath_read_kreg64( 86 dd, dd->ipath_kregs->kr_sendbuffererror + 1); 87 if (piobcnt > 128) { 88 sbuf[2] = ipath_read_kreg64( 89 dd, dd->ipath_kregs->kr_sendbuffererror + 2); 90 sbuf[3] = ipath_read_kreg64( 91 dd, dd->ipath_kregs->kr_sendbuffererror + 3); 92 } 93 94 if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) { 95 int i; 96 if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) && 97 dd->ipath_lastcancel > jiffies) { 98 __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG, 99 "SendbufErrs %lx %lx", sbuf[0], 100 sbuf[1]); 101 if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128) 102 printk(" %lx %lx ", sbuf[2], sbuf[3]); 103 printk("\n"); 104 } 105 106 for (i = 0; i < piobcnt; i++) 107 if (test_bit(i, sbuf)) { 108 if (rewrite) 109 ipath_clrpiobuf(dd, i); 110 ipath_disarm_piobufs(dd, i, 1); 111 } 112 /* ignore armlaunch errs for a bit */ 113 dd->ipath_lastcancel = jiffies+3; 114 } 115} 116 117 118/* These are all rcv-related errors which we want to count for stats */ 119#define E_SUM_PKTERRS \ 120 (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \ 121 INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \ 122 INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \ 123 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \ 124 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \ 125 INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP) 126 127/* These are all send-related errors which we want to count for stats */ 128#define E_SUM_ERRS \ 129 (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \ 130 INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 131 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \ 132 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ 133 INFINIPATH_E_INVALIDADDR) 134 135/* 136 * these are errors that can occur when the link changes state while 137 * a packet is being sent or received. This doesn't cover things 138 * like EBP or VCRC that can be the result of a sending having the 139 * link change state, so we receive a "known bad" packet. 140 */ 141#define E_SUM_LINK_PKTERRS \ 142 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 143 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ 144 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \ 145 INFINIPATH_E_RUNEXPCHAR) 146 147static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs) 148{ 149 u64 ignore_this_time = 0; 150 151 ipath_disarm_senderrbufs(dd, 0); 152 if ((errs & E_SUM_LINK_PKTERRS) && 153 !(dd->ipath_flags & IPATH_LINKACTIVE)) { 154 /* 155 * This can happen when SMA is trying to bring the link 156 * up, but the IB link changes state at the "wrong" time. 157 * The IB logic then complains that the packet isn't 158 * valid. We don't want to confuse people, so we just 159 * don't print them, except at debug 160 */ 161 ipath_dbg("Ignoring packet errors %llx, because link not " 162 "ACTIVE\n", (unsigned long long) errs); 163 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 164 } 165 166 return ignore_this_time; 167} 168 169/* generic hw error messages... */ 170#define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \ 171 { \ 172 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \ 173 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \ 174 .msg = "TXE " #a " Memory Parity" \ 175 } 176#define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \ 177 { \ 178 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \ 179 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \ 180 .msg = "RXE " #a " Memory Parity" \ 181 } 182 183static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = { 184 INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"), 185 INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"), 186 187 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF), 188 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC), 189 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO), 190 191 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF), 192 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ), 193 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID), 194 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID), 195 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF), 196 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO), 197 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO), 198}; 199 200/** 201 * ipath_format_hwmsg - format a single hwerror message 202 * @msg message buffer 203 * @msgl length of message buffer 204 * @hwmsg message to add to message buffer 205 */ 206static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg) 207{ 208 strlcat(msg, "[", msgl); 209 strlcat(msg, hwmsg, msgl); 210 strlcat(msg, "]", msgl); 211} 212 213/** 214 * ipath_format_hwerrors - format hardware error messages for display 215 * @hwerrs hardware errors bit vector 216 * @hwerrmsgs hardware error descriptions 217 * @nhwerrmsgs number of hwerrmsgs 218 * @msg message buffer 219 * @msgl message buffer length 220 */ 221void ipath_format_hwerrors(u64 hwerrs, 222 const struct ipath_hwerror_msgs *hwerrmsgs, 223 size_t nhwerrmsgs, 224 char *msg, size_t msgl) 225{ 226 int i; 227 const int glen = 228 sizeof(ipath_generic_hwerror_msgs) / 229 sizeof(ipath_generic_hwerror_msgs[0]); 230 231 for (i=0; i<glen; i++) { 232 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) { 233 ipath_format_hwmsg(msg, msgl, 234 ipath_generic_hwerror_msgs[i].msg); 235 } 236 } 237 238 for (i=0; i<nhwerrmsgs; i++) { 239 if (hwerrs & hwerrmsgs[i].mask) { 240 ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg); 241 } 242 } 243} 244 245/* return the strings for the most common link states */ 246static char *ib_linkstate(u32 linkstate) 247{ 248 char *ret; 249 250 switch (linkstate) { 251 case IPATH_IBSTATE_INIT: 252 ret = "Init"; 253 break; 254 case IPATH_IBSTATE_ARM: 255 ret = "Arm"; 256 break; 257 case IPATH_IBSTATE_ACTIVE: 258 ret = "Active"; 259 break; 260 default: 261 ret = "Down"; 262 } 263 264 return ret; 265} 266 267static void handle_e_ibstatuschanged(struct ipath_devdata *dd, 268 ipath_err_t errs, int noprint) 269{ 270 u64 val; 271 u32 ltstate, lstate; 272 273 /* 274 * even if diags are enabled, we want to notice LINKINIT, etc. 275 * We just don't want to change the LED state, or 276 * dd->ipath_kregs->kr_ibcctrl 277 */ 278 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus); 279 lstate = val & IPATH_IBSTATE_MASK; 280 281 /* 282 * this is confusing enough when it happens that I want to always put it 283 * on the console and in the logs. If it was a requested state change, 284 * we'll have already cleared the flags, so we won't print this warning 285 */ 286 if ((lstate != IPATH_IBSTATE_ARM && lstate != IPATH_IBSTATE_ACTIVE) 287 && (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) { 288 dev_info(&dd->pcidev->dev, "Link state changed from %s to %s\n", 289 (dd->ipath_flags & IPATH_LINKARMED) ? "ARM" : "ACTIVE", 290 ib_linkstate(lstate)); 291 /* 292 * Flush all queued sends when link went to DOWN or INIT, 293 * to be sure that they don't block SMA and other MAD packets 294 */ 295 ipath_cancel_sends(dd); 296 } 297 else if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM || 298 lstate == IPATH_IBSTATE_ACTIVE) { 299 /* 300 * only print at SMA if there is a change, debug if not 301 * (sometimes we want to know that, usually not). 302 */ 303 if (lstate == ((unsigned) dd->ipath_lastibcstat 304 & IPATH_IBSTATE_MASK)) { 305 ipath_dbg("Status change intr but no change (%s)\n", 306 ib_linkstate(lstate)); 307 } 308 else 309 ipath_cdbg(VERBOSE, "Unit %u link state %s, last " 310 "was %s\n", dd->ipath_unit, 311 ib_linkstate(lstate), 312 ib_linkstate((unsigned) 313 dd->ipath_lastibcstat 314 & IPATH_IBSTATE_MASK)); 315 } 316 else { 317 lstate = dd->ipath_lastibcstat & IPATH_IBSTATE_MASK; 318 if (lstate == IPATH_IBSTATE_INIT || 319 lstate == IPATH_IBSTATE_ARM || 320 lstate == IPATH_IBSTATE_ACTIVE) 321 ipath_cdbg(VERBOSE, "Unit %u link state down" 322 " (state 0x%x), from %s\n", 323 dd->ipath_unit, 324 (u32)val & IPATH_IBSTATE_MASK, 325 ib_linkstate(lstate)); 326 else 327 ipath_cdbg(VERBOSE, "Unit %u link state changed " 328 "to 0x%x from down (%x)\n", 329 dd->ipath_unit, (u32) val, lstate); 330 } 331 ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) & 332 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK; 333 lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) & 334 INFINIPATH_IBCS_LINKSTATE_MASK; 335 336 if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE || 337 ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) { 338 u32 last_ltstate; 339 340 /* 341 * Ignore cycling back and forth from Polling.Active 342 * to Polling.Quiet while waiting for the other end of 343 * the link to come up. We will cycle back and forth 344 * between them if no cable is plugged in, 345 * the other device is powered off or disabled, etc. 346 */ 347 last_ltstate = (dd->ipath_lastibcstat >> 348 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) 349 & INFINIPATH_IBCS_LINKTRAININGSTATE_MASK; 350 if (last_ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE 351 || last_ltstate == 352 INFINIPATH_IBCS_LT_STATE_POLLQUIET) { 353 if (dd->ipath_ibpollcnt > 40) { 354 dd->ipath_flags |= IPATH_NOCABLE; 355 *dd->ipath_statusp |= 356 IPATH_STATUS_IB_NOCABLE; 357 } else 358 dd->ipath_ibpollcnt++; 359 goto skip_ibchange; 360 } 361 } 362 dd->ipath_ibpollcnt = 0; /* some state other than 2 or 3 */ 363 ipath_stats.sps_iblink++; 364 if (ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) { 365 dd->ipath_flags |= IPATH_LINKDOWN; 366 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 367 | IPATH_LINKACTIVE | 368 IPATH_LINKARMED); 369 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 370 dd->ipath_lli_counter = 0; 371 if (!noprint) { 372 if (((dd->ipath_lastibcstat >> 373 INFINIPATH_IBCS_LINKSTATE_SHIFT) & 374 INFINIPATH_IBCS_LINKSTATE_MASK) 375 == INFINIPATH_IBCS_L_STATE_ACTIVE) 376 /* if from up to down be more vocal */ 377 ipath_cdbg(VERBOSE, 378 "Unit %u link now down (%s)\n", 379 dd->ipath_unit, 380 ipath_ibcstatus_str[ltstate]); 381 else 382 ipath_cdbg(VERBOSE, "Unit %u link is " 383 "down (%s)\n", dd->ipath_unit, 384 ipath_ibcstatus_str[ltstate]); 385 } 386 387 dd->ipath_f_setextled(dd, lstate, ltstate); 388 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ACTIVE) { 389 dd->ipath_flags |= IPATH_LINKACTIVE; 390 dd->ipath_flags &= 391 ~(IPATH_LINKUNK | IPATH_LINKINIT | IPATH_LINKDOWN | 392 IPATH_LINKARMED | IPATH_NOCABLE); 393 *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE; 394 *dd->ipath_statusp |= 395 IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF; 396 dd->ipath_f_setextled(dd, lstate, ltstate); 397 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_INIT) { 398 /* 399 * set INIT and DOWN. Down is checked by most of the other 400 * code, but INIT is useful to know in a few places. 401 */ 402 dd->ipath_flags |= IPATH_LINKINIT | IPATH_LINKDOWN; 403 dd->ipath_flags &= 404 ~(IPATH_LINKUNK | IPATH_LINKACTIVE | IPATH_LINKARMED 405 | IPATH_NOCABLE); 406 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE 407 | IPATH_STATUS_IB_READY); 408 dd->ipath_f_setextled(dd, lstate, ltstate); 409 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ARM) { 410 dd->ipath_flags |= IPATH_LINKARMED; 411 dd->ipath_flags &= 412 ~(IPATH_LINKUNK | IPATH_LINKDOWN | IPATH_LINKINIT | 413 IPATH_LINKACTIVE | IPATH_NOCABLE); 414 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE 415 | IPATH_STATUS_IB_READY); 416 dd->ipath_f_setextled(dd, lstate, ltstate); 417 } else { 418 if (!noprint) 419 ipath_dbg("IBstatuschange unit %u: %s (%x)\n", 420 dd->ipath_unit, 421 ipath_ibcstatus_str[ltstate], ltstate); 422 } 423skip_ibchange: 424 dd->ipath_lastibcstat = val; 425} 426 427static void handle_supp_msgs(struct ipath_devdata *dd, 428 unsigned supp_msgs, char msg[512]) 429{ 430 /* 431 * Print the message unless it's ibc status change only, which 432 * happens so often we never want to count it. 433 */ 434 if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) { 435 int iserr; 436 iserr = ipath_decode_err(msg, sizeof msg, 437 dd->ipath_lasterror & 438 ~INFINIPATH_E_IBSTATUSCHANGED); 439 if (dd->ipath_lasterror & 440 ~(INFINIPATH_E_RRCVEGRFULL | 441 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) 442 ipath_dev_err(dd, "Suppressed %u messages for " 443 "fast-repeating errors (%s) (%llx)\n", 444 supp_msgs, msg, 445 (unsigned long long) 446 dd->ipath_lasterror); 447 else { 448 /* 449 * rcvegrfull and rcvhdrqfull are "normal", for some 450 * types of processes (mostly benchmarks) that send 451 * huge numbers of messages, while not processing 452 * them. So only complain about these at debug 453 * level. 454 */ 455 if (iserr) 456 ipath_dbg("Suppressed %u messages for %s\n", 457 supp_msgs, msg); 458 else 459 ipath_cdbg(ERRPKT, 460 "Suppressed %u messages for %s\n", 461 supp_msgs, msg); 462 } 463 } 464} 465 466static unsigned handle_frequent_errors(struct ipath_devdata *dd, 467 ipath_err_t errs, char msg[512], 468 int *noprint) 469{ 470 unsigned long nc; 471 static unsigned long nextmsg_time; 472 static unsigned nmsgs, supp_msgs; 473 474 /* 475 * Throttle back "fast" messages to no more than 10 per 5 seconds. 476 * This isn't perfect, but it's a reasonable heuristic. If we get 477 * more than 10, give a 6x longer delay. 478 */ 479 nc = jiffies; 480 if (nmsgs > 10) { 481 if (time_before(nc, nextmsg_time)) { 482 *noprint = 1; 483 if (!supp_msgs++) 484 nextmsg_time = nc + HZ * 3; 485 } 486 else if (supp_msgs) { 487 handle_supp_msgs(dd, supp_msgs, msg); 488 supp_msgs = 0; 489 nmsgs = 0; 490 } 491 } 492 else if (!nmsgs++ || time_after(nc, nextmsg_time)) 493 nextmsg_time = nc + HZ / 2; 494 495 return supp_msgs; 496} 497 498static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs) 499{ 500 char msg[512]; 501 u64 ignore_this_time = 0; 502 int i, iserr = 0; 503 int chkerrpkts = 0, noprint = 0; 504 unsigned supp_msgs; 505 int log_idx; 506 507 supp_msgs = handle_frequent_errors(dd, errs, msg, &noprint); 508 509 /* 510 * don't report errors that are masked (includes those always 511 * ignored) 512 */ 513 errs &= ~dd->ipath_maskederrs; 514 515 /* do these first, they are most important */ 516 if (errs & INFINIPATH_E_HARDWARE) { 517 /* reuse same msg buf */ 518 dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg); 519 } else { 520 u64 mask; 521 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) { 522 mask = dd->ipath_eep_st_masks[log_idx].errs_to_log; 523 if (errs & mask) 524 ipath_inc_eeprom_err(dd, log_idx, 1); 525 } 526 } 527 528 if (!noprint && (errs & ~dd->ipath_e_bitsextant)) 529 ipath_dev_err(dd, "error interrupt with unknown errors " 530 "%llx set\n", (unsigned long long) 531 (errs & ~dd->ipath_e_bitsextant)); 532 533 if (errs & E_SUM_ERRS) 534 ignore_this_time = handle_e_sum_errs(dd, errs); 535 else if ((errs & E_SUM_LINK_PKTERRS) && 536 !(dd->ipath_flags & IPATH_LINKACTIVE)) { 537 /* 538 * This can happen when SMA is trying to bring the link 539 * up, but the IB link changes state at the "wrong" time. 540 * The IB logic then complains that the packet isn't 541 * valid. We don't want to confuse people, so we just 542 * don't print them, except at debug 543 */ 544 ipath_dbg("Ignoring packet errors %llx, because link not " 545 "ACTIVE\n", (unsigned long long) errs); 546 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 547 } 548 549 if (supp_msgs == 250000) { 550 int s_iserr; 551 /* 552 * It's not entirely reasonable assuming that the errors set 553 * in the last clear period are all responsible for the 554 * problem, but the alternative is to assume it's the only 555 * ones on this particular interrupt, which also isn't great 556 */ 557 dd->ipath_maskederrs |= dd->ipath_lasterror | errs; 558 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 559 ~dd->ipath_maskederrs); 560 s_iserr = ipath_decode_err(msg, sizeof msg, 561 (dd->ipath_maskederrs & ~dd-> 562 ipath_ignorederrs)); 563 564 if ((dd->ipath_maskederrs & ~dd->ipath_ignorederrs) & 565 ~(INFINIPATH_E_RRCVEGRFULL | 566 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) 567 ipath_dev_err(dd, "Temporarily disabling " 568 "error(s) %llx reporting; too frequent (%s)\n", 569 (unsigned long long) (dd->ipath_maskederrs & 570 ~dd->ipath_ignorederrs), msg); 571 else { 572 /* 573 * rcvegrfull and rcvhdrqfull are "normal", 574 * for some types of processes (mostly benchmarks) 575 * that send huge numbers of messages, while not 576 * processing them. So only complain about 577 * these at debug level. 578 */ 579 if (s_iserr) 580 ipath_dbg("Temporarily disabling reporting " 581 "too frequent queue full errors (%s)\n", 582 msg); 583 else 584 ipath_cdbg(ERRPKT, 585 "Temporarily disabling reporting too" 586 " frequent packet errors (%s)\n", 587 msg); 588 } 589 590 /* 591 * Re-enable the masked errors after around 3 minutes. in 592 * ipath_get_faststats(). If we have a series of fast 593 * repeating but different errors, the interval will keep 594 * stretching out, but that's OK, as that's pretty 595 * catastrophic. 596 */ 597 dd->ipath_unmasktime = jiffies + HZ * 180; 598 } 599 600 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs); 601 if (ignore_this_time) 602 errs &= ~ignore_this_time; 603 if (errs & ~dd->ipath_lasterror) { 604 errs &= ~dd->ipath_lasterror; 605 /* never suppress duplicate hwerrors or ibstatuschange */ 606 dd->ipath_lasterror |= errs & 607 ~(INFINIPATH_E_HARDWARE | 608 INFINIPATH_E_IBSTATUSCHANGED); 609 } 610 611 /* likely due to cancel, so suppress */ 612 if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) && 613 dd->ipath_lastcancel > jiffies) { 614 ipath_dbg("Suppressed armlaunch/spktlen after error send cancel\n"); 615 errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN); 616 } 617 618 if (!errs) 619 return 0; 620 621 if (!noprint) 622 /* 623 * the ones we mask off are handled specially below or above 624 */ 625 ipath_decode_err(msg, sizeof msg, 626 errs & ~(INFINIPATH_E_IBSTATUSCHANGED | 627 INFINIPATH_E_RRCVEGRFULL | 628 INFINIPATH_E_RRCVHDRFULL | 629 INFINIPATH_E_HARDWARE)); 630 else 631 /* so we don't need if (!noprint) at strlcat's below */ 632 *msg = 0; 633 634 if (errs & E_SUM_PKTERRS) { 635 ipath_stats.sps_pkterrs++; 636 chkerrpkts = 1; 637 } 638 if (errs & E_SUM_ERRS) 639 ipath_stats.sps_errs++; 640 641 if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) { 642 ipath_stats.sps_crcerrs++; 643 chkerrpkts = 1; 644 } 645 iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS); 646 647 648 /* 649 * We don't want to print these two as they happen, or we can make 650 * the situation even worse, because it takes so long to print 651 * messages to serial consoles. Kernel ports get printed from 652 * fast_stats, no more than every 5 seconds, user ports get printed 653 * on close 654 */ 655 if (errs & INFINIPATH_E_RRCVHDRFULL) { 656 u32 hd, tl; 657 ipath_stats.sps_hdrqfull++; 658 for (i = 0; i < dd->ipath_cfgports; i++) { 659 struct ipath_portdata *pd = dd->ipath_pd[i]; 660 if (i == 0) { 661 hd = dd->ipath_port0head; 662 tl = (u32) le64_to_cpu( 663 *dd->ipath_hdrqtailptr); 664 } else if (pd && pd->port_cnt && 665 pd->port_rcvhdrtail_kvaddr) { 666 /* 667 * don't report same point multiple times, 668 * except kernel 669 */ 670 tl = *(u64 *) pd->port_rcvhdrtail_kvaddr; 671 if (tl == dd->ipath_lastrcvhdrqtails[i]) 672 continue; 673 hd = ipath_read_ureg32(dd, ur_rcvhdrhead, 674 i); 675 } else 676 continue; 677 if (hd == (tl + 1) || 678 (!hd && tl == dd->ipath_hdrqlast)) { 679 if (i == 0) 680 chkerrpkts = 1; 681 dd->ipath_lastrcvhdrqtails[i] = tl; 682 pd->port_hdrqfull++; 683 } 684 } 685 } 686 if (errs & INFINIPATH_E_RRCVEGRFULL) { 687 /* 688 * since this is of less importance and not likely to 689 * happen without also getting hdrfull, only count 690 * occurrences; don't check each port (or even the kernel 691 * vs user) 692 */ 693 ipath_stats.sps_etidfull++; 694 if (dd->ipath_port0head != 695 (u32) le64_to_cpu(*dd->ipath_hdrqtailptr)) 696 chkerrpkts = 1; 697 } 698 699 /* 700 * do this before IBSTATUSCHANGED, in case both bits set in a single 701 * interrupt; we want the STATUSCHANGE to "win", so we do our 702 * internal copy of state machine correctly 703 */ 704 if (errs & INFINIPATH_E_RIBLOSTLINK) { 705 /* 706 * force through block below 707 */ 708 errs |= INFINIPATH_E_IBSTATUSCHANGED; 709 ipath_stats.sps_iblink++; 710 dd->ipath_flags |= IPATH_LINKDOWN; 711 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 712 | IPATH_LINKARMED | IPATH_LINKACTIVE); 713 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 714 if (!noprint) { 715 u64 st = ipath_read_kreg64( 716 dd, dd->ipath_kregs->kr_ibcstatus); 717 718 ipath_dbg("Lost link, link now down (%s)\n", 719 ipath_ibcstatus_str[st & 0xf]); 720 } 721 } 722 if (errs & INFINIPATH_E_IBSTATUSCHANGED) 723 handle_e_ibstatuschanged(dd, errs, noprint); 724 725 if (errs & INFINIPATH_E_RESET) { 726 if (!noprint) 727 ipath_dev_err(dd, "Got reset, requires re-init " 728 "(unload and reload driver)\n"); 729 dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */ 730 /* mark as having had error */ 731 *dd->ipath_statusp |= IPATH_STATUS_HWERROR; 732 *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF; 733 } 734 735 if (!noprint && *msg) { 736 if (iserr) 737 ipath_dev_err(dd, "%s error\n", msg); 738 else 739 dev_info(&dd->pcidev->dev, "%s packet problems\n", 740 msg); 741 } 742 if (dd->ipath_state_wanted & dd->ipath_flags) { 743 ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, " 744 "waking\n", dd->ipath_state_wanted, 745 dd->ipath_flags); 746 wake_up_interruptible(&ipath_state_wait); 747 } 748 749 return chkerrpkts; 750} 751 752/* this is separate to allow for better optimization of ipath_intr() */ 753 754static void ipath_bad_intr(struct ipath_devdata *dd, u32 * unexpectp) 755{ 756 /* 757 * sometimes happen during driver init and unload, don't want 758 * to process any interrupts at that point 759 */ 760 761 /* this is just a bandaid, not a fix, if something goes badly 762 * wrong */ 763 if (++*unexpectp > 100) { 764 if (++*unexpectp > 105) { 765 /* 766 * ok, we must be taking somebody else's interrupts, 767 * due to a messed up mptable and/or PIRQ table, so 768 * unregister the interrupt. We've seen this during 769 * linuxbios development work, and it may happen in 770 * the future again. 771 */ 772 if (dd->pcidev && dd->ipath_irq) { 773 ipath_dev_err(dd, "Now %u unexpected " 774 "interrupts, unregistering " 775 "interrupt handler\n", 776 *unexpectp); 777 ipath_dbg("free_irq of irq %d\n", 778 dd->ipath_irq); 779 dd->ipath_f_free_irq(dd); 780 } 781 } 782 if (ipath_read_kreg32(dd, dd->ipath_kregs->kr_intmask)) { 783 ipath_dev_err(dd, "%u unexpected interrupts, " 784 "disabling interrupts completely\n", 785 *unexpectp); 786 /* 787 * disable all interrupts, something is very wrong 788 */ 789 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 790 0ULL); 791 } 792 } else if (*unexpectp > 1) 793 ipath_dbg("Interrupt when not ready, should not happen, " 794 "ignoring\n"); 795} 796 797static void ipath_bad_regread(struct ipath_devdata *dd) 798{ 799 static int allbits; 800 801 /* separate routine, for better optimization of ipath_intr() */ 802 803 /* 804 * We print the message and disable interrupts, in hope of 805 * having a better chance of debugging the problem. 806 */ 807 ipath_dev_err(dd, 808 "Read of interrupt status failed (all bits set)\n"); 809 if (allbits++) { 810 /* disable all interrupts, something is very wrong */ 811 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); 812 if (allbits == 2) { 813 ipath_dev_err(dd, "Still bad interrupt status, " 814 "unregistering interrupt\n"); 815 dd->ipath_f_free_irq(dd); 816 } else if (allbits > 2) { 817 if ((allbits % 10000) == 0) 818 printk("."); 819 } else 820 ipath_dev_err(dd, "Disabling interrupts, " 821 "multiple errors\n"); 822 } 823} 824 825static void handle_port_pioavail(struct ipath_devdata *dd) 826{ 827 u32 i; 828 /* 829 * start from port 1, since for now port 0 is never using 830 * wait_event for PIO 831 */ 832 for (i = 1; dd->ipath_portpiowait && i < dd->ipath_cfgports; i++) { 833 struct ipath_portdata *pd = dd->ipath_pd[i]; 834 835 if (pd && pd->port_cnt && 836 dd->ipath_portpiowait & (1U << i)) { 837 clear_bit(i, &dd->ipath_portpiowait); 838 if (test_bit(IPATH_PORT_WAITING_PIO, 839 &pd->port_flag)) { 840 clear_bit(IPATH_PORT_WAITING_PIO, 841 &pd->port_flag); 842 wake_up_interruptible(&pd->port_wait); 843 } 844 } 845 } 846} 847 848static void handle_layer_pioavail(struct ipath_devdata *dd) 849{ 850 int ret; 851 852 ret = ipath_ib_piobufavail(dd->verbs_dev); 853 if (ret > 0) 854 goto set; 855 856 return; 857set: 858 set_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl); 859 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 860 dd->ipath_sendctrl); 861} 862 863/* 864 * Handle receive interrupts for user ports; this means a user 865 * process was waiting for a packet to arrive, and didn't want 866 * to poll 867 */ 868static void handle_urcv(struct ipath_devdata *dd, u32 istat) 869{ 870 u64 portr; 871 int i; 872 int rcvdint = 0; 873 874 portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) & 875 dd->ipath_i_rcvavail_mask) 876 | ((istat >> INFINIPATH_I_RCVURG_SHIFT) & 877 dd->ipath_i_rcvurg_mask); 878 for (i = 1; i < dd->ipath_cfgports; i++) { 879 struct ipath_portdata *pd = dd->ipath_pd[i]; 880 if (portr & (1 << i) && pd && pd->port_cnt && 881 test_bit(IPATH_PORT_WAITING_RCV, &pd->port_flag)) { 882 clear_bit(IPATH_PORT_WAITING_RCV, 883 &pd->port_flag); 884 clear_bit(i + INFINIPATH_R_INTRAVAIL_SHIFT, 885 &dd->ipath_rcvctrl); 886 wake_up_interruptible(&pd->port_wait); 887 rcvdint = 1; 888 } 889 } 890 if (rcvdint) { 891 /* only want to take one interrupt, so turn off the rcv 892 * interrupt for all the ports that we did the wakeup on 893 * (but never for kernel port) 894 */ 895 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 896 dd->ipath_rcvctrl); 897 } 898} 899 900irqreturn_t ipath_intr(int irq, void *data) 901{ 902 struct ipath_devdata *dd = data; 903 u32 istat, chk0rcv = 0; 904 ipath_err_t estat = 0; 905 irqreturn_t ret; 906 u32 oldhead, curtail; 907 static unsigned unexpected = 0; 908 static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) | 909 (1U<<INFINIPATH_I_RCVURG_SHIFT); 910 911 ipath_stats.sps_ints++; 912 913 if (!(dd->ipath_flags & IPATH_PRESENT)) { 914 /* 915 * This return value is not great, but we do not want the 916 * interrupt core code to remove our interrupt handler 917 * because we don't appear to be handling an interrupt 918 * during a chip reset. 919 */ 920 return IRQ_HANDLED; 921 } 922 923 /* 924 * this needs to be flags&initted, not statusp, so we keep 925 * taking interrupts even after link goes down, etc. 926 * Also, we *must* clear the interrupt at some point, or we won't 927 * take it again, which can be real bad for errors, etc... 928 */ 929 930 if (!(dd->ipath_flags & IPATH_INITTED)) { 931 ipath_bad_intr(dd, &unexpected); 932 ret = IRQ_NONE; 933 goto bail; 934 } 935 936 /* 937 * We try to avoid reading the interrupt status register, since 938 * that's a PIO read, and stalls the processor for up to about 939 * ~0.25 usec. The idea is that if we processed a port0 packet, 940 * we blindly clear the port 0 receive interrupt bits, and nothing 941 * else, then return. If other interrupts are pending, the chip 942 * will re-interrupt us as soon as we write the intclear register. 943 * We then won't process any more kernel packets (if not the 2nd 944 * time, then the 3rd or 4th) and we'll then handle the other 945 * interrupts. We clear the interrupts first so that we don't 946 * lose intr for later packets that arrive while we are processing. 947 */ 948 oldhead = dd->ipath_port0head; 949 curtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr); 950 if (oldhead != curtail) { 951 if (dd->ipath_flags & IPATH_GPIO_INTR) { 952 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear, 953 (u64) (1 << IPATH_GPIO_PORT0_BIT)); 954 istat = port0rbits | INFINIPATH_I_GPIO; 955 } 956 else 957 istat = port0rbits; 958 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat); 959 ipath_kreceive(dd); 960 if (oldhead != dd->ipath_port0head) { 961 ipath_stats.sps_fastrcvint++; 962 goto done; 963 } 964 } 965 966 istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus); 967 968 if (unlikely(!istat)) { 969 ipath_stats.sps_nullintr++; 970 ret = IRQ_NONE; /* not our interrupt, or already handled */ 971 goto bail; 972 } 973 if (unlikely(istat == -1)) { 974 ipath_bad_regread(dd); 975 /* don't know if it was our interrupt or not */ 976 ret = IRQ_NONE; 977 goto bail; 978 } 979 980 if (unexpected) 981 unexpected = 0; 982 983 if (unlikely(istat & ~dd->ipath_i_bitsextant)) 984 ipath_dev_err(dd, 985 "interrupt with unknown interrupts %x set\n", 986 istat & (u32) ~ dd->ipath_i_bitsextant); 987 else 988 ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat); 989 990 if (unlikely(istat & INFINIPATH_I_ERROR)) { 991 ipath_stats.sps_errints++; 992 estat = ipath_read_kreg64(dd, 993 dd->ipath_kregs->kr_errorstatus); 994 if (!estat) 995 dev_info(&dd->pcidev->dev, "error interrupt (%x), " 996 "but no error bits set!\n", istat); 997 else if (estat == -1LL) 998 /* 999 * should we try clearing all, or hope next read 1000 * works? 1001 */ 1002 ipath_dev_err(dd, "Read of error status failed " 1003 "(all bits set); ignoring\n"); 1004 else 1005 if (handle_errors(dd, estat)) 1006 /* force calling ipath_kreceive() */ 1007 chk0rcv = 1; 1008 } 1009 1010 if (istat & INFINIPATH_I_GPIO) { 1011 /* 1012 * GPIO interrupts fall in two broad classes: 1013 * GPIO_2 indicates (on some HT4xx boards) that a packet 1014 * has arrived for Port 0. Checking for this 1015 * is controlled by flag IPATH_GPIO_INTR. 1016 * GPIO_3..5 on IBA6120 Rev2 chips indicate errors 1017 * that we need to count. Checking for this 1018 * is controlled by flag IPATH_GPIO_ERRINTRS. 1019 */ 1020 u32 gpiostatus; 1021 u32 to_clear = 0; 1022 1023 gpiostatus = ipath_read_kreg32( 1024 dd, dd->ipath_kregs->kr_gpio_status); 1025 /* First the error-counter case. 1026 */ 1027 if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) && 1028 (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) { 1029 /* want to clear the bits we see asserted. */ 1030 to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK); 1031 1032 /* 1033 * Count appropriately, clear bits out of our copy, 1034 * as they have been "handled". 1035 */ 1036 if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) { 1037 ipath_dbg("FlowCtl on UnsupVL\n"); 1038 dd->ipath_rxfc_unsupvl_errs++; 1039 } 1040 if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) { 1041 ipath_dbg("Overrun Threshold exceeded\n"); 1042 dd->ipath_overrun_thresh_errs++; 1043 } 1044 if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) { 1045 ipath_dbg("Local Link Integrity error\n"); 1046 dd->ipath_lli_errs++; 1047 } 1048 gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK; 1049 } 1050 /* Now the Port0 Receive case */ 1051 if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) && 1052 (dd->ipath_flags & IPATH_GPIO_INTR)) { 1053 /* 1054 * GPIO status bit 2 is set, and we expected it. 1055 * clear it and indicate in p0bits. 1056 * This probably only happens if a Port0 pkt 1057 * arrives at _just_ the wrong time, and we 1058 * handle that by seting chk0rcv; 1059 */ 1060 to_clear |= (1 << IPATH_GPIO_PORT0_BIT); 1061 gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT); 1062 chk0rcv = 1; 1063 } 1064 if (gpiostatus) { 1065 /* 1066 * Some unexpected bits remain. If they could have 1067 * caused the interrupt, complain and clear. 1068 * MEA: this is almost certainly non-ideal. 1069 * we should look into auto-disable of unexpected 1070 * GPIO interrupts, possibly on a "three strikes" 1071 * basis. 1072 */ 1073 const u32 mask = (u32) dd->ipath_gpio_mask; 1074 1075 if (mask & gpiostatus) { 1076 ipath_dbg("Unexpected GPIO IRQ bits %x\n", 1077 gpiostatus & mask); 1078 to_clear |= (gpiostatus & mask); 1079 } 1080 } 1081 if (to_clear) { 1082 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear, 1083 (u64) to_clear); 1084 } 1085 } 1086 chk0rcv |= istat & port0rbits; 1087 1088 /* 1089 * Clear the interrupt bits we found set, unless they are receive 1090 * related, in which case we already cleared them above, and don't 1091 * want to clear them again, because we might lose an interrupt. 1092 * Clear it early, so we "know" know the chip will have seen this by 1093 * the time we process the queue, and will re-interrupt if necessary. 1094 * The processor itself won't take the interrupt again until we return. 1095 */ 1096 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat); 1097 1098 /* 1099 * handle port0 receive before checking for pio buffers available, 1100 * since receives can overflow; piobuf waiters can afford a few 1101 * extra cycles, since they were waiting anyway, and user's waiting 1102 * for receive are at the bottom. 1103 */ 1104 if (chk0rcv) { 1105 ipath_kreceive(dd); 1106 istat &= ~port0rbits; 1107 } 1108 1109 if (istat & ((dd->ipath_i_rcvavail_mask << 1110 INFINIPATH_I_RCVAVAIL_SHIFT) 1111 | (dd->ipath_i_rcvurg_mask << 1112 INFINIPATH_I_RCVURG_SHIFT))) 1113 handle_urcv(dd, istat); 1114 1115 if (istat & INFINIPATH_I_SPIOBUFAVAIL) { 1116 clear_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl); 1117 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 1118 dd->ipath_sendctrl); 1119 1120 if (dd->ipath_portpiowait) 1121 handle_port_pioavail(dd); 1122 1123 handle_layer_pioavail(dd); 1124 } 1125 1126done: 1127 ret = IRQ_HANDLED; 1128 1129bail: 1130 return ret; 1131} 1132