ipath_intr.c revision aecd3b5ab19624ca9644b9df9c61615282d8923f
1/* 2 * Copyright (c) 2006 QLogic, Inc. All rights reserved. 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34#include <linux/pci.h> 35 36#include "ipath_kernel.h" 37#include "ipath_verbs.h" 38#include "ipath_common.h" 39 40/* 41 * clear (write) a pio buffer, to clear a parity error. This routine 42 * should only be called when in freeze mode, and the buffer should be 43 * canceled afterwards. 44 */ 45static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum) 46{ 47 u32 __iomem *pbuf; 48 u32 dwcnt; /* dword count to write */ 49 if (pnum < dd->ipath_piobcnt2k) { 50 pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum * 51 dd->ipath_palign); 52 dwcnt = dd->ipath_piosize2k >> 2; 53 } 54 else { 55 pbuf = (u32 __iomem *) (dd->ipath_pio4kbase + 56 (pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign); 57 dwcnt = dd->ipath_piosize4k >> 2; 58 } 59 dev_info(&dd->pcidev->dev, 60 "Rewrite PIO buffer %u, to recover from parity error\n", 61 pnum); 62 *pbuf = dwcnt+1; /* no flush required, since already in freeze */ 63 while(--dwcnt) 64 *pbuf++ = 0; 65} 66 67/* 68 * Called when we might have an error that is specific to a particular 69 * PIO buffer, and may need to cancel that buffer, so it can be re-used. 70 * If rewrite is true, and bits are set in the sendbufferror registers, 71 * we'll write to the buffer, for error recovery on parity errors. 72 */ 73void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite) 74{ 75 u32 piobcnt; 76 unsigned long sbuf[4]; 77 /* 78 * it's possible that sendbuffererror could have bits set; might 79 * have already done this as a result of hardware error handling 80 */ 81 piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; 82 /* read these before writing errorclear */ 83 sbuf[0] = ipath_read_kreg64( 84 dd, dd->ipath_kregs->kr_sendbuffererror); 85 sbuf[1] = ipath_read_kreg64( 86 dd, dd->ipath_kregs->kr_sendbuffererror + 1); 87 if (piobcnt > 128) { 88 sbuf[2] = ipath_read_kreg64( 89 dd, dd->ipath_kregs->kr_sendbuffererror + 2); 90 sbuf[3] = ipath_read_kreg64( 91 dd, dd->ipath_kregs->kr_sendbuffererror + 3); 92 } 93 94 if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) { 95 int i; 96 if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG)) { 97 __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG, 98 "SendbufErrs %lx %lx", sbuf[0], 99 sbuf[1]); 100 if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128) 101 printk(" %lx %lx ", sbuf[2], sbuf[3]); 102 printk("\n"); 103 } 104 105 for (i = 0; i < piobcnt; i++) 106 if (test_bit(i, sbuf)) { 107 if (rewrite) 108 ipath_clrpiobuf(dd, i); 109 ipath_disarm_piobufs(dd, i, 1); 110 } 111 dd->ipath_lastcancel = jiffies+3; /* no armlaunch for a bit */ 112 } 113} 114 115 116/* These are all rcv-related errors which we want to count for stats */ 117#define E_SUM_PKTERRS \ 118 (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \ 119 INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \ 120 INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \ 121 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \ 122 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \ 123 INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP) 124 125/* These are all send-related errors which we want to count for stats */ 126#define E_SUM_ERRS \ 127 (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \ 128 INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 129 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \ 130 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ 131 INFINIPATH_E_INVALIDADDR) 132 133/* 134 * these are errors that can occur when the link changes state while 135 * a packet is being sent or received. This doesn't cover things 136 * like EBP or VCRC that can be the result of a sending having the 137 * link change state, so we receive a "known bad" packet. 138 */ 139#define E_SUM_LINK_PKTERRS \ 140 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ 141 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ 142 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \ 143 INFINIPATH_E_RUNEXPCHAR) 144 145static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs) 146{ 147 u64 ignore_this_time = 0; 148 149 ipath_disarm_senderrbufs(dd, 0); 150 if ((errs & E_SUM_LINK_PKTERRS) && 151 !(dd->ipath_flags & IPATH_LINKACTIVE)) { 152 /* 153 * This can happen when SMA is trying to bring the link 154 * up, but the IB link changes state at the "wrong" time. 155 * The IB logic then complains that the packet isn't 156 * valid. We don't want to confuse people, so we just 157 * don't print them, except at debug 158 */ 159 ipath_dbg("Ignoring packet errors %llx, because link not " 160 "ACTIVE\n", (unsigned long long) errs); 161 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 162 } 163 164 return ignore_this_time; 165} 166 167/* generic hw error messages... */ 168#define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \ 169 { \ 170 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \ 171 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \ 172 .msg = "TXE " #a " Memory Parity" \ 173 } 174#define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \ 175 { \ 176 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \ 177 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \ 178 .msg = "RXE " #a " Memory Parity" \ 179 } 180 181static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = { 182 INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"), 183 INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"), 184 185 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF), 186 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC), 187 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO), 188 189 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF), 190 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ), 191 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID), 192 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID), 193 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF), 194 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO), 195 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO), 196}; 197 198/** 199 * ipath_format_hwmsg - format a single hwerror message 200 * @msg message buffer 201 * @msgl length of message buffer 202 * @hwmsg message to add to message buffer 203 */ 204static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg) 205{ 206 strlcat(msg, "[", msgl); 207 strlcat(msg, hwmsg, msgl); 208 strlcat(msg, "]", msgl); 209} 210 211/** 212 * ipath_format_hwerrors - format hardware error messages for display 213 * @hwerrs hardware errors bit vector 214 * @hwerrmsgs hardware error descriptions 215 * @nhwerrmsgs number of hwerrmsgs 216 * @msg message buffer 217 * @msgl message buffer length 218 */ 219void ipath_format_hwerrors(u64 hwerrs, 220 const struct ipath_hwerror_msgs *hwerrmsgs, 221 size_t nhwerrmsgs, 222 char *msg, size_t msgl) 223{ 224 int i; 225 const int glen = 226 sizeof(ipath_generic_hwerror_msgs) / 227 sizeof(ipath_generic_hwerror_msgs[0]); 228 229 for (i=0; i<glen; i++) { 230 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) { 231 ipath_format_hwmsg(msg, msgl, 232 ipath_generic_hwerror_msgs[i].msg); 233 } 234 } 235 236 for (i=0; i<nhwerrmsgs; i++) { 237 if (hwerrs & hwerrmsgs[i].mask) { 238 ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg); 239 } 240 } 241} 242 243/* return the strings for the most common link states */ 244static char *ib_linkstate(u32 linkstate) 245{ 246 char *ret; 247 248 switch (linkstate) { 249 case IPATH_IBSTATE_INIT: 250 ret = "Init"; 251 break; 252 case IPATH_IBSTATE_ARM: 253 ret = "Arm"; 254 break; 255 case IPATH_IBSTATE_ACTIVE: 256 ret = "Active"; 257 break; 258 default: 259 ret = "Down"; 260 } 261 262 return ret; 263} 264 265static void handle_e_ibstatuschanged(struct ipath_devdata *dd, 266 ipath_err_t errs, int noprint) 267{ 268 u64 val; 269 u32 ltstate, lstate; 270 271 /* 272 * even if diags are enabled, we want to notice LINKINIT, etc. 273 * We just don't want to change the LED state, or 274 * dd->ipath_kregs->kr_ibcctrl 275 */ 276 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus); 277 lstate = val & IPATH_IBSTATE_MASK; 278 279 /* 280 * this is confusing enough when it happens that I want to always put it 281 * on the console and in the logs. If it was a requested state change, 282 * we'll have already cleared the flags, so we won't print this warning 283 */ 284 if ((lstate != IPATH_IBSTATE_ARM && lstate != IPATH_IBSTATE_ACTIVE) 285 && (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) { 286 dev_info(&dd->pcidev->dev, "Link state changed from %s to %s\n", 287 (dd->ipath_flags & IPATH_LINKARMED) ? "ARM" : "ACTIVE", 288 ib_linkstate(lstate)); 289 /* 290 * Flush all queued sends when link went to DOWN or INIT, 291 * to be sure that they don't block SMA and other MAD packets 292 */ 293 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 294 INFINIPATH_S_ABORT); 295 ipath_disarm_piobufs(dd, dd->ipath_lastport_piobuf, 296 (unsigned)(dd->ipath_piobcnt2k + 297 dd->ipath_piobcnt4k) - 298 dd->ipath_lastport_piobuf); 299 } 300 else if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM || 301 lstate == IPATH_IBSTATE_ACTIVE) { 302 /* 303 * only print at SMA if there is a change, debug if not 304 * (sometimes we want to know that, usually not). 305 */ 306 if (lstate == ((unsigned) dd->ipath_lastibcstat 307 & IPATH_IBSTATE_MASK)) { 308 ipath_dbg("Status change intr but no change (%s)\n", 309 ib_linkstate(lstate)); 310 } 311 else 312 ipath_cdbg(VERBOSE, "Unit %u link state %s, last " 313 "was %s\n", dd->ipath_unit, 314 ib_linkstate(lstate), 315 ib_linkstate((unsigned) 316 dd->ipath_lastibcstat 317 & IPATH_IBSTATE_MASK)); 318 } 319 else { 320 lstate = dd->ipath_lastibcstat & IPATH_IBSTATE_MASK; 321 if (lstate == IPATH_IBSTATE_INIT || 322 lstate == IPATH_IBSTATE_ARM || 323 lstate == IPATH_IBSTATE_ACTIVE) 324 ipath_cdbg(VERBOSE, "Unit %u link state down" 325 " (state 0x%x), from %s\n", 326 dd->ipath_unit, 327 (u32)val & IPATH_IBSTATE_MASK, 328 ib_linkstate(lstate)); 329 else 330 ipath_cdbg(VERBOSE, "Unit %u link state changed " 331 "to 0x%x from down (%x)\n", 332 dd->ipath_unit, (u32) val, lstate); 333 } 334 ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) & 335 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK; 336 lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) & 337 INFINIPATH_IBCS_LINKSTATE_MASK; 338 339 if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE || 340 ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) { 341 u32 last_ltstate; 342 343 /* 344 * Ignore cycling back and forth from Polling.Active 345 * to Polling.Quiet while waiting for the other end of 346 * the link to come up. We will cycle back and forth 347 * between them if no cable is plugged in, 348 * the other device is powered off or disabled, etc. 349 */ 350 last_ltstate = (dd->ipath_lastibcstat >> 351 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) 352 & INFINIPATH_IBCS_LINKTRAININGSTATE_MASK; 353 if (last_ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE 354 || last_ltstate == 355 INFINIPATH_IBCS_LT_STATE_POLLQUIET) { 356 if (dd->ipath_ibpollcnt > 40) { 357 dd->ipath_flags |= IPATH_NOCABLE; 358 *dd->ipath_statusp |= 359 IPATH_STATUS_IB_NOCABLE; 360 } else 361 dd->ipath_ibpollcnt++; 362 goto skip_ibchange; 363 } 364 } 365 dd->ipath_ibpollcnt = 0; /* some state other than 2 or 3 */ 366 ipath_stats.sps_iblink++; 367 if (ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) { 368 dd->ipath_flags |= IPATH_LINKDOWN; 369 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 370 | IPATH_LINKACTIVE | 371 IPATH_LINKARMED); 372 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 373 dd->ipath_lli_counter = 0; 374 if (!noprint) { 375 if (((dd->ipath_lastibcstat >> 376 INFINIPATH_IBCS_LINKSTATE_SHIFT) & 377 INFINIPATH_IBCS_LINKSTATE_MASK) 378 == INFINIPATH_IBCS_L_STATE_ACTIVE) 379 /* if from up to down be more vocal */ 380 ipath_cdbg(VERBOSE, 381 "Unit %u link now down (%s)\n", 382 dd->ipath_unit, 383 ipath_ibcstatus_str[ltstate]); 384 else 385 ipath_cdbg(VERBOSE, "Unit %u link is " 386 "down (%s)\n", dd->ipath_unit, 387 ipath_ibcstatus_str[ltstate]); 388 } 389 390 dd->ipath_f_setextled(dd, lstate, ltstate); 391 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ACTIVE) { 392 dd->ipath_flags |= IPATH_LINKACTIVE; 393 dd->ipath_flags &= 394 ~(IPATH_LINKUNK | IPATH_LINKINIT | IPATH_LINKDOWN | 395 IPATH_LINKARMED | IPATH_NOCABLE); 396 *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE; 397 *dd->ipath_statusp |= 398 IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF; 399 dd->ipath_f_setextled(dd, lstate, ltstate); 400 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_INIT) { 401 /* 402 * set INIT and DOWN. Down is checked by most of the other 403 * code, but INIT is useful to know in a few places. 404 */ 405 dd->ipath_flags |= IPATH_LINKINIT | IPATH_LINKDOWN; 406 dd->ipath_flags &= 407 ~(IPATH_LINKUNK | IPATH_LINKACTIVE | IPATH_LINKARMED 408 | IPATH_NOCABLE); 409 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE 410 | IPATH_STATUS_IB_READY); 411 dd->ipath_f_setextled(dd, lstate, ltstate); 412 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ARM) { 413 dd->ipath_flags |= IPATH_LINKARMED; 414 dd->ipath_flags &= 415 ~(IPATH_LINKUNK | IPATH_LINKDOWN | IPATH_LINKINIT | 416 IPATH_LINKACTIVE | IPATH_NOCABLE); 417 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE 418 | IPATH_STATUS_IB_READY); 419 dd->ipath_f_setextled(dd, lstate, ltstate); 420 } else { 421 if (!noprint) 422 ipath_dbg("IBstatuschange unit %u: %s (%x)\n", 423 dd->ipath_unit, 424 ipath_ibcstatus_str[ltstate], ltstate); 425 } 426skip_ibchange: 427 dd->ipath_lastibcstat = val; 428} 429 430static void handle_supp_msgs(struct ipath_devdata *dd, 431 unsigned supp_msgs, char msg[512]) 432{ 433 /* 434 * Print the message unless it's ibc status change only, which 435 * happens so often we never want to count it. 436 */ 437 if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) { 438 int iserr; 439 iserr = ipath_decode_err(msg, sizeof msg, 440 dd->ipath_lasterror & 441 ~INFINIPATH_E_IBSTATUSCHANGED); 442 if (dd->ipath_lasterror & 443 ~(INFINIPATH_E_RRCVEGRFULL | 444 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) 445 ipath_dev_err(dd, "Suppressed %u messages for " 446 "fast-repeating errors (%s) (%llx)\n", 447 supp_msgs, msg, 448 (unsigned long long) 449 dd->ipath_lasterror); 450 else { 451 /* 452 * rcvegrfull and rcvhdrqfull are "normal", for some 453 * types of processes (mostly benchmarks) that send 454 * huge numbers of messages, while not processing 455 * them. So only complain about these at debug 456 * level. 457 */ 458 if (iserr) 459 ipath_dbg("Suppressed %u messages for %s\n", 460 supp_msgs, msg); 461 else 462 ipath_cdbg(ERRPKT, 463 "Suppressed %u messages for %s\n", 464 supp_msgs, msg); 465 } 466 } 467} 468 469static unsigned handle_frequent_errors(struct ipath_devdata *dd, 470 ipath_err_t errs, char msg[512], 471 int *noprint) 472{ 473 unsigned long nc; 474 static unsigned long nextmsg_time; 475 static unsigned nmsgs, supp_msgs; 476 477 /* 478 * Throttle back "fast" messages to no more than 10 per 5 seconds. 479 * This isn't perfect, but it's a reasonable heuristic. If we get 480 * more than 10, give a 6x longer delay. 481 */ 482 nc = jiffies; 483 if (nmsgs > 10) { 484 if (time_before(nc, nextmsg_time)) { 485 *noprint = 1; 486 if (!supp_msgs++) 487 nextmsg_time = nc + HZ * 3; 488 } 489 else if (supp_msgs) { 490 handle_supp_msgs(dd, supp_msgs, msg); 491 supp_msgs = 0; 492 nmsgs = 0; 493 } 494 } 495 else if (!nmsgs++ || time_after(nc, nextmsg_time)) 496 nextmsg_time = nc + HZ / 2; 497 498 return supp_msgs; 499} 500 501static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs) 502{ 503 char msg[512]; 504 u64 ignore_this_time = 0; 505 int i, iserr = 0; 506 int chkerrpkts = 0, noprint = 0; 507 unsigned supp_msgs; 508 int log_idx; 509 510 supp_msgs = handle_frequent_errors(dd, errs, msg, &noprint); 511 512 /* 513 * don't report errors that are masked (includes those always 514 * ignored) 515 */ 516 errs &= ~dd->ipath_maskederrs; 517 518 /* do these first, they are most important */ 519 if (errs & INFINIPATH_E_HARDWARE) { 520 /* reuse same msg buf */ 521 dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg); 522 } else { 523 u64 mask; 524 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) { 525 mask = dd->ipath_eep_st_masks[log_idx].errs_to_log; 526 if (errs & mask) 527 ipath_inc_eeprom_err(dd, log_idx, 1); 528 } 529 } 530 531 if (!noprint && (errs & ~dd->ipath_e_bitsextant)) 532 ipath_dev_err(dd, "error interrupt with unknown errors " 533 "%llx set\n", (unsigned long long) 534 (errs & ~dd->ipath_e_bitsextant)); 535 536 if (errs & E_SUM_ERRS) 537 ignore_this_time = handle_e_sum_errs(dd, errs); 538 else if ((errs & E_SUM_LINK_PKTERRS) && 539 !(dd->ipath_flags & IPATH_LINKACTIVE)) { 540 /* 541 * This can happen when SMA is trying to bring the link 542 * up, but the IB link changes state at the "wrong" time. 543 * The IB logic then complains that the packet isn't 544 * valid. We don't want to confuse people, so we just 545 * don't print them, except at debug 546 */ 547 ipath_dbg("Ignoring packet errors %llx, because link not " 548 "ACTIVE\n", (unsigned long long) errs); 549 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 550 } 551 552 if (supp_msgs == 250000) { 553 int s_iserr; 554 /* 555 * It's not entirely reasonable assuming that the errors set 556 * in the last clear period are all responsible for the 557 * problem, but the alternative is to assume it's the only 558 * ones on this particular interrupt, which also isn't great 559 */ 560 dd->ipath_maskederrs |= dd->ipath_lasterror | errs; 561 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 562 ~dd->ipath_maskederrs); 563 s_iserr = ipath_decode_err(msg, sizeof msg, 564 (dd->ipath_maskederrs & ~dd-> 565 ipath_ignorederrs)); 566 567 if ((dd->ipath_maskederrs & ~dd->ipath_ignorederrs) & 568 ~(INFINIPATH_E_RRCVEGRFULL | 569 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) 570 ipath_dev_err(dd, "Temporarily disabling " 571 "error(s) %llx reporting; too frequent (%s)\n", 572 (unsigned long long) (dd->ipath_maskederrs & 573 ~dd->ipath_ignorederrs), msg); 574 else { 575 /* 576 * rcvegrfull and rcvhdrqfull are "normal", 577 * for some types of processes (mostly benchmarks) 578 * that send huge numbers of messages, while not 579 * processing them. So only complain about 580 * these at debug level. 581 */ 582 if (s_iserr) 583 ipath_dbg("Temporarily disabling reporting " 584 "too frequent queue full errors (%s)\n", 585 msg); 586 else 587 ipath_cdbg(ERRPKT, 588 "Temporarily disabling reporting too" 589 " frequent packet errors (%s)\n", 590 msg); 591 } 592 593 /* 594 * Re-enable the masked errors after around 3 minutes. in 595 * ipath_get_faststats(). If we have a series of fast 596 * repeating but different errors, the interval will keep 597 * stretching out, but that's OK, as that's pretty 598 * catastrophic. 599 */ 600 dd->ipath_unmasktime = jiffies + HZ * 180; 601 } 602 603 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs); 604 if (ignore_this_time) 605 errs &= ~ignore_this_time; 606 if (errs & ~dd->ipath_lasterror) { 607 errs &= ~dd->ipath_lasterror; 608 /* never suppress duplicate hwerrors or ibstatuschange */ 609 dd->ipath_lasterror |= errs & 610 ~(INFINIPATH_E_HARDWARE | 611 INFINIPATH_E_IBSTATUSCHANGED); 612 } 613 614 /* likely due to cancel, so suppress */ 615 if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) && 616 dd->ipath_lastcancel > jiffies) { 617 ipath_dbg("Suppressed armlaunch/spktlen after error send cancel\n"); 618 errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN); 619 } 620 621 if (!errs) 622 return 0; 623 624 if (!noprint) 625 /* 626 * the ones we mask off are handled specially below or above 627 */ 628 ipath_decode_err(msg, sizeof msg, 629 errs & ~(INFINIPATH_E_IBSTATUSCHANGED | 630 INFINIPATH_E_RRCVEGRFULL | 631 INFINIPATH_E_RRCVHDRFULL | 632 INFINIPATH_E_HARDWARE)); 633 else 634 /* so we don't need if (!noprint) at strlcat's below */ 635 *msg = 0; 636 637 if (errs & E_SUM_PKTERRS) { 638 ipath_stats.sps_pkterrs++; 639 chkerrpkts = 1; 640 } 641 if (errs & E_SUM_ERRS) 642 ipath_stats.sps_errs++; 643 644 if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) { 645 ipath_stats.sps_crcerrs++; 646 chkerrpkts = 1; 647 } 648 iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS); 649 650 651 /* 652 * We don't want to print these two as they happen, or we can make 653 * the situation even worse, because it takes so long to print 654 * messages to serial consoles. Kernel ports get printed from 655 * fast_stats, no more than every 5 seconds, user ports get printed 656 * on close 657 */ 658 if (errs & INFINIPATH_E_RRCVHDRFULL) { 659 u32 hd, tl; 660 ipath_stats.sps_hdrqfull++; 661 for (i = 0; i < dd->ipath_cfgports; i++) { 662 struct ipath_portdata *pd = dd->ipath_pd[i]; 663 if (i == 0) { 664 hd = dd->ipath_port0head; 665 tl = (u32) le64_to_cpu( 666 *dd->ipath_hdrqtailptr); 667 } else if (pd && pd->port_cnt && 668 pd->port_rcvhdrtail_kvaddr) { 669 /* 670 * don't report same point multiple times, 671 * except kernel 672 */ 673 tl = *(u64 *) pd->port_rcvhdrtail_kvaddr; 674 if (tl == dd->ipath_lastrcvhdrqtails[i]) 675 continue; 676 hd = ipath_read_ureg32(dd, ur_rcvhdrhead, 677 i); 678 } else 679 continue; 680 if (hd == (tl + 1) || 681 (!hd && tl == dd->ipath_hdrqlast)) { 682 if (i == 0) 683 chkerrpkts = 1; 684 dd->ipath_lastrcvhdrqtails[i] = tl; 685 pd->port_hdrqfull++; 686 } 687 } 688 } 689 if (errs & INFINIPATH_E_RRCVEGRFULL) { 690 /* 691 * since this is of less importance and not likely to 692 * happen without also getting hdrfull, only count 693 * occurrences; don't check each port (or even the kernel 694 * vs user) 695 */ 696 ipath_stats.sps_etidfull++; 697 if (dd->ipath_port0head != 698 (u32) le64_to_cpu(*dd->ipath_hdrqtailptr)) 699 chkerrpkts = 1; 700 } 701 702 /* 703 * do this before IBSTATUSCHANGED, in case both bits set in a single 704 * interrupt; we want the STATUSCHANGE to "win", so we do our 705 * internal copy of state machine correctly 706 */ 707 if (errs & INFINIPATH_E_RIBLOSTLINK) { 708 /* 709 * force through block below 710 */ 711 errs |= INFINIPATH_E_IBSTATUSCHANGED; 712 ipath_stats.sps_iblink++; 713 dd->ipath_flags |= IPATH_LINKDOWN; 714 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT 715 | IPATH_LINKARMED | IPATH_LINKACTIVE); 716 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 717 if (!noprint) { 718 u64 st = ipath_read_kreg64( 719 dd, dd->ipath_kregs->kr_ibcstatus); 720 721 ipath_dbg("Lost link, link now down (%s)\n", 722 ipath_ibcstatus_str[st & 0xf]); 723 } 724 } 725 if (errs & INFINIPATH_E_IBSTATUSCHANGED) 726 handle_e_ibstatuschanged(dd, errs, noprint); 727 728 if (errs & INFINIPATH_E_RESET) { 729 if (!noprint) 730 ipath_dev_err(dd, "Got reset, requires re-init " 731 "(unload and reload driver)\n"); 732 dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */ 733 /* mark as having had error */ 734 *dd->ipath_statusp |= IPATH_STATUS_HWERROR; 735 *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF; 736 } 737 738 if (!noprint && *msg) { 739 if (iserr) 740 ipath_dev_err(dd, "%s error\n", msg); 741 else 742 dev_info(&dd->pcidev->dev, "%s packet problems\n", 743 msg); 744 } 745 if (dd->ipath_state_wanted & dd->ipath_flags) { 746 ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, " 747 "waking\n", dd->ipath_state_wanted, 748 dd->ipath_flags); 749 wake_up_interruptible(&ipath_state_wait); 750 } 751 752 return chkerrpkts; 753} 754 755/* this is separate to allow for better optimization of ipath_intr() */ 756 757static void ipath_bad_intr(struct ipath_devdata *dd, u32 * unexpectp) 758{ 759 /* 760 * sometimes happen during driver init and unload, don't want 761 * to process any interrupts at that point 762 */ 763 764 /* this is just a bandaid, not a fix, if something goes badly 765 * wrong */ 766 if (++*unexpectp > 100) { 767 if (++*unexpectp > 105) { 768 /* 769 * ok, we must be taking somebody else's interrupts, 770 * due to a messed up mptable and/or PIRQ table, so 771 * unregister the interrupt. We've seen this during 772 * linuxbios development work, and it may happen in 773 * the future again. 774 */ 775 if (dd->pcidev && dd->ipath_irq) { 776 ipath_dev_err(dd, "Now %u unexpected " 777 "interrupts, unregistering " 778 "interrupt handler\n", 779 *unexpectp); 780 ipath_dbg("free_irq of irq %d\n", 781 dd->ipath_irq); 782 dd->ipath_f_free_irq(dd); 783 } 784 } 785 if (ipath_read_kreg32(dd, dd->ipath_kregs->kr_intmask)) { 786 ipath_dev_err(dd, "%u unexpected interrupts, " 787 "disabling interrupts completely\n", 788 *unexpectp); 789 /* 790 * disable all interrupts, something is very wrong 791 */ 792 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 793 0ULL); 794 } 795 } else if (*unexpectp > 1) 796 ipath_dbg("Interrupt when not ready, should not happen, " 797 "ignoring\n"); 798} 799 800static void ipath_bad_regread(struct ipath_devdata *dd) 801{ 802 static int allbits; 803 804 /* separate routine, for better optimization of ipath_intr() */ 805 806 /* 807 * We print the message and disable interrupts, in hope of 808 * having a better chance of debugging the problem. 809 */ 810 ipath_dev_err(dd, 811 "Read of interrupt status failed (all bits set)\n"); 812 if (allbits++) { 813 /* disable all interrupts, something is very wrong */ 814 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); 815 if (allbits == 2) { 816 ipath_dev_err(dd, "Still bad interrupt status, " 817 "unregistering interrupt\n"); 818 dd->ipath_f_free_irq(dd); 819 } else if (allbits > 2) { 820 if ((allbits % 10000) == 0) 821 printk("."); 822 } else 823 ipath_dev_err(dd, "Disabling interrupts, " 824 "multiple errors\n"); 825 } 826} 827 828static void handle_port_pioavail(struct ipath_devdata *dd) 829{ 830 u32 i; 831 /* 832 * start from port 1, since for now port 0 is never using 833 * wait_event for PIO 834 */ 835 for (i = 1; dd->ipath_portpiowait && i < dd->ipath_cfgports; i++) { 836 struct ipath_portdata *pd = dd->ipath_pd[i]; 837 838 if (pd && pd->port_cnt && 839 dd->ipath_portpiowait & (1U << i)) { 840 clear_bit(i, &dd->ipath_portpiowait); 841 if (test_bit(IPATH_PORT_WAITING_PIO, 842 &pd->port_flag)) { 843 clear_bit(IPATH_PORT_WAITING_PIO, 844 &pd->port_flag); 845 wake_up_interruptible(&pd->port_wait); 846 } 847 } 848 } 849} 850 851static void handle_layer_pioavail(struct ipath_devdata *dd) 852{ 853 int ret; 854 855 ret = ipath_ib_piobufavail(dd->verbs_dev); 856 if (ret > 0) 857 goto set; 858 859 return; 860set: 861 set_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl); 862 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 863 dd->ipath_sendctrl); 864} 865 866/* 867 * Handle receive interrupts for user ports; this means a user 868 * process was waiting for a packet to arrive, and didn't want 869 * to poll 870 */ 871static void handle_urcv(struct ipath_devdata *dd, u32 istat) 872{ 873 u64 portr; 874 int i; 875 int rcvdint = 0; 876 877 portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) & 878 dd->ipath_i_rcvavail_mask) 879 | ((istat >> INFINIPATH_I_RCVURG_SHIFT) & 880 dd->ipath_i_rcvurg_mask); 881 for (i = 1; i < dd->ipath_cfgports; i++) { 882 struct ipath_portdata *pd = dd->ipath_pd[i]; 883 if (portr & (1 << i) && pd && pd->port_cnt && 884 test_bit(IPATH_PORT_WAITING_RCV, &pd->port_flag)) { 885 clear_bit(IPATH_PORT_WAITING_RCV, 886 &pd->port_flag); 887 clear_bit(i + INFINIPATH_R_INTRAVAIL_SHIFT, 888 &dd->ipath_rcvctrl); 889 wake_up_interruptible(&pd->port_wait); 890 rcvdint = 1; 891 } 892 } 893 if (rcvdint) { 894 /* only want to take one interrupt, so turn off the rcv 895 * interrupt for all the ports that we did the wakeup on 896 * (but never for kernel port) 897 */ 898 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 899 dd->ipath_rcvctrl); 900 } 901} 902 903irqreturn_t ipath_intr(int irq, void *data) 904{ 905 struct ipath_devdata *dd = data; 906 u32 istat, chk0rcv = 0; 907 ipath_err_t estat = 0; 908 irqreturn_t ret; 909 u32 oldhead, curtail; 910 static unsigned unexpected = 0; 911 static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) | 912 (1U<<INFINIPATH_I_RCVURG_SHIFT); 913 914 ipath_stats.sps_ints++; 915 916 if (!(dd->ipath_flags & IPATH_PRESENT)) { 917 /* 918 * This return value is not great, but we do not want the 919 * interrupt core code to remove our interrupt handler 920 * because we don't appear to be handling an interrupt 921 * during a chip reset. 922 */ 923 return IRQ_HANDLED; 924 } 925 926 /* 927 * this needs to be flags&initted, not statusp, so we keep 928 * taking interrupts even after link goes down, etc. 929 * Also, we *must* clear the interrupt at some point, or we won't 930 * take it again, which can be real bad for errors, etc... 931 */ 932 933 if (!(dd->ipath_flags & IPATH_INITTED)) { 934 ipath_bad_intr(dd, &unexpected); 935 ret = IRQ_NONE; 936 goto bail; 937 } 938 939 /* 940 * We try to avoid reading the interrupt status register, since 941 * that's a PIO read, and stalls the processor for up to about 942 * ~0.25 usec. The idea is that if we processed a port0 packet, 943 * we blindly clear the port 0 receive interrupt bits, and nothing 944 * else, then return. If other interrupts are pending, the chip 945 * will re-interrupt us as soon as we write the intclear register. 946 * We then won't process any more kernel packets (if not the 2nd 947 * time, then the 3rd or 4th) and we'll then handle the other 948 * interrupts. We clear the interrupts first so that we don't 949 * lose intr for later packets that arrive while we are processing. 950 */ 951 oldhead = dd->ipath_port0head; 952 curtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr); 953 if (oldhead != curtail) { 954 if (dd->ipath_flags & IPATH_GPIO_INTR) { 955 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear, 956 (u64) (1 << IPATH_GPIO_PORT0_BIT)); 957 istat = port0rbits | INFINIPATH_I_GPIO; 958 } 959 else 960 istat = port0rbits; 961 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat); 962 ipath_kreceive(dd); 963 if (oldhead != dd->ipath_port0head) { 964 ipath_stats.sps_fastrcvint++; 965 goto done; 966 } 967 } 968 969 istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus); 970 971 if (unlikely(!istat)) { 972 ipath_stats.sps_nullintr++; 973 ret = IRQ_NONE; /* not our interrupt, or already handled */ 974 goto bail; 975 } 976 if (unlikely(istat == -1)) { 977 ipath_bad_regread(dd); 978 /* don't know if it was our interrupt or not */ 979 ret = IRQ_NONE; 980 goto bail; 981 } 982 983 if (unexpected) 984 unexpected = 0; 985 986 if (unlikely(istat & ~dd->ipath_i_bitsextant)) 987 ipath_dev_err(dd, 988 "interrupt with unknown interrupts %x set\n", 989 istat & (u32) ~ dd->ipath_i_bitsextant); 990 else 991 ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat); 992 993 if (unlikely(istat & INFINIPATH_I_ERROR)) { 994 ipath_stats.sps_errints++; 995 estat = ipath_read_kreg64(dd, 996 dd->ipath_kregs->kr_errorstatus); 997 if (!estat) 998 dev_info(&dd->pcidev->dev, "error interrupt (%x), " 999 "but no error bits set!\n", istat); 1000 else if (estat == -1LL) 1001 /* 1002 * should we try clearing all, or hope next read 1003 * works? 1004 */ 1005 ipath_dev_err(dd, "Read of error status failed " 1006 "(all bits set); ignoring\n"); 1007 else 1008 if (handle_errors(dd, estat)) 1009 /* force calling ipath_kreceive() */ 1010 chk0rcv = 1; 1011 } 1012 1013 if (istat & INFINIPATH_I_GPIO) { 1014 /* 1015 * GPIO interrupts fall in two broad classes: 1016 * GPIO_2 indicates (on some HT4xx boards) that a packet 1017 * has arrived for Port 0. Checking for this 1018 * is controlled by flag IPATH_GPIO_INTR. 1019 * GPIO_3..5 on IBA6120 Rev2 chips indicate errors 1020 * that we need to count. Checking for this 1021 * is controlled by flag IPATH_GPIO_ERRINTRS. 1022 */ 1023 u32 gpiostatus; 1024 u32 to_clear = 0; 1025 1026 gpiostatus = ipath_read_kreg32( 1027 dd, dd->ipath_kregs->kr_gpio_status); 1028 /* First the error-counter case. 1029 */ 1030 if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) && 1031 (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) { 1032 /* want to clear the bits we see asserted. */ 1033 to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK); 1034 1035 /* 1036 * Count appropriately, clear bits out of our copy, 1037 * as they have been "handled". 1038 */ 1039 if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) { 1040 ipath_dbg("FlowCtl on UnsupVL\n"); 1041 dd->ipath_rxfc_unsupvl_errs++; 1042 } 1043 if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) { 1044 ipath_dbg("Overrun Threshold exceeded\n"); 1045 dd->ipath_overrun_thresh_errs++; 1046 } 1047 if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) { 1048 ipath_dbg("Local Link Integrity error\n"); 1049 dd->ipath_lli_errs++; 1050 } 1051 gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK; 1052 } 1053 /* Now the Port0 Receive case */ 1054 if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) && 1055 (dd->ipath_flags & IPATH_GPIO_INTR)) { 1056 /* 1057 * GPIO status bit 2 is set, and we expected it. 1058 * clear it and indicate in p0bits. 1059 * This probably only happens if a Port0 pkt 1060 * arrives at _just_ the wrong time, and we 1061 * handle that by seting chk0rcv; 1062 */ 1063 to_clear |= (1 << IPATH_GPIO_PORT0_BIT); 1064 gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT); 1065 chk0rcv = 1; 1066 } 1067 if (gpiostatus) { 1068 /* 1069 * Some unexpected bits remain. If they could have 1070 * caused the interrupt, complain and clear. 1071 * MEA: this is almost certainly non-ideal. 1072 * we should look into auto-disable of unexpected 1073 * GPIO interrupts, possibly on a "three strikes" 1074 * basis. 1075 */ 1076 const u32 mask = (u32) dd->ipath_gpio_mask; 1077 1078 if (mask & gpiostatus) { 1079 ipath_dbg("Unexpected GPIO IRQ bits %x\n", 1080 gpiostatus & mask); 1081 to_clear |= (gpiostatus & mask); 1082 } 1083 } 1084 if (to_clear) { 1085 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear, 1086 (u64) to_clear); 1087 } 1088 } 1089 chk0rcv |= istat & port0rbits; 1090 1091 /* 1092 * Clear the interrupt bits we found set, unless they are receive 1093 * related, in which case we already cleared them above, and don't 1094 * want to clear them again, because we might lose an interrupt. 1095 * Clear it early, so we "know" know the chip will have seen this by 1096 * the time we process the queue, and will re-interrupt if necessary. 1097 * The processor itself won't take the interrupt again until we return. 1098 */ 1099 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat); 1100 1101 /* 1102 * handle port0 receive before checking for pio buffers available, 1103 * since receives can overflow; piobuf waiters can afford a few 1104 * extra cycles, since they were waiting anyway, and user's waiting 1105 * for receive are at the bottom. 1106 */ 1107 if (chk0rcv) { 1108 ipath_kreceive(dd); 1109 istat &= ~port0rbits; 1110 } 1111 1112 if (istat & ((dd->ipath_i_rcvavail_mask << 1113 INFINIPATH_I_RCVAVAIL_SHIFT) 1114 | (dd->ipath_i_rcvurg_mask << 1115 INFINIPATH_I_RCVURG_SHIFT))) 1116 handle_urcv(dd, istat); 1117 1118 if (istat & INFINIPATH_I_SPIOBUFAVAIL) { 1119 clear_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl); 1120 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 1121 dd->ipath_sendctrl); 1122 1123 if (dd->ipath_portpiowait) 1124 handle_port_pioavail(dd); 1125 1126 handle_layer_pioavail(dd); 1127 } 1128 1129done: 1130 ret = IRQ_HANDLED; 1131 1132bail: 1133 return ret; 1134} 1135