mthca_srq.c revision 1d368c546566e249da8181e933c53788093965cf
1/* 2 * Copyright (c) 2005 Cisco Systems. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 * $Id: mthca_srq.c 3047 2005-08-10 03:59:35Z roland $ 33 */ 34 35#include <linux/slab.h> 36#include <linux/string.h> 37#include <linux/sched.h> 38 39#include <asm/io.h> 40 41#include "mthca_dev.h" 42#include "mthca_cmd.h" 43#include "mthca_memfree.h" 44#include "mthca_wqe.h" 45 46enum { 47 MTHCA_MAX_DIRECT_SRQ_SIZE = 4 * PAGE_SIZE 48}; 49 50struct mthca_tavor_srq_context { 51 __be64 wqe_base_ds; /* low 6 bits is descriptor size */ 52 __be32 state_pd; 53 __be32 lkey; 54 __be32 uar; 55 __be16 limit_watermark; 56 __be16 wqe_cnt; 57 u32 reserved[2]; 58}; 59 60struct mthca_arbel_srq_context { 61 __be32 state_logsize_srqn; 62 __be32 lkey; 63 __be32 db_index; 64 __be32 logstride_usrpage; 65 __be64 wqe_base; 66 __be32 eq_pd; 67 __be16 limit_watermark; 68 __be16 wqe_cnt; 69 u16 reserved1; 70 __be16 wqe_counter; 71 u32 reserved2[3]; 72}; 73 74static void *get_wqe(struct mthca_srq *srq, int n) 75{ 76 if (srq->is_direct) 77 return srq->queue.direct.buf + (n << srq->wqe_shift); 78 else 79 return srq->queue.page_list[(n << srq->wqe_shift) >> PAGE_SHIFT].buf + 80 ((n << srq->wqe_shift) & (PAGE_SIZE - 1)); 81} 82 83/* 84 * Return a pointer to the location within a WQE that we're using as a 85 * link when the WQE is in the free list. We use the imm field 86 * because in the Tavor case, posting a WQE may overwrite the next 87 * segment of the previous WQE, but a receive WQE will never touch the 88 * imm field. This avoids corrupting our free list if the previous 89 * WQE has already completed and been put on the free list when we 90 * post the next WQE. 91 */ 92static inline int *wqe_to_link(void *wqe) 93{ 94 return (int *) (wqe + offsetof(struct mthca_next_seg, imm)); 95} 96 97static void mthca_tavor_init_srq_context(struct mthca_dev *dev, 98 struct mthca_pd *pd, 99 struct mthca_srq *srq, 100 struct mthca_tavor_srq_context *context) 101{ 102 memset(context, 0, sizeof *context); 103 104 context->wqe_base_ds = cpu_to_be64(1 << (srq->wqe_shift - 4)); 105 context->state_pd = cpu_to_be32(pd->pd_num); 106 context->lkey = cpu_to_be32(srq->mr.ibmr.lkey); 107 108 if (pd->ibpd.uobject) 109 context->uar = 110 cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index); 111 else 112 context->uar = cpu_to_be32(dev->driver_uar.index); 113} 114 115static void mthca_arbel_init_srq_context(struct mthca_dev *dev, 116 struct mthca_pd *pd, 117 struct mthca_srq *srq, 118 struct mthca_arbel_srq_context *context) 119{ 120 int logsize, max; 121 122 memset(context, 0, sizeof *context); 123 124 /* 125 * Put max in a temporary variable to work around gcc bug 126 * triggered by ilog2() on sparc64. 127 */ 128 max = srq->max; 129 logsize = ilog2(max); 130 context->state_logsize_srqn = cpu_to_be32(logsize << 24 | srq->srqn); 131 context->lkey = cpu_to_be32(srq->mr.ibmr.lkey); 132 context->db_index = cpu_to_be32(srq->db_index); 133 context->logstride_usrpage = cpu_to_be32((srq->wqe_shift - 4) << 29); 134 if (pd->ibpd.uobject) 135 context->logstride_usrpage |= 136 cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index); 137 else 138 context->logstride_usrpage |= cpu_to_be32(dev->driver_uar.index); 139 context->eq_pd = cpu_to_be32(MTHCA_EQ_ASYNC << 24 | pd->pd_num); 140} 141 142static void mthca_free_srq_buf(struct mthca_dev *dev, struct mthca_srq *srq) 143{ 144 mthca_buf_free(dev, srq->max << srq->wqe_shift, &srq->queue, 145 srq->is_direct, &srq->mr); 146 kfree(srq->wrid); 147} 148 149static int mthca_alloc_srq_buf(struct mthca_dev *dev, struct mthca_pd *pd, 150 struct mthca_srq *srq) 151{ 152 struct mthca_data_seg *scatter; 153 void *wqe; 154 int err; 155 int i; 156 157 if (pd->ibpd.uobject) 158 return 0; 159 160 srq->wrid = kmalloc(srq->max * sizeof (u64), GFP_KERNEL); 161 if (!srq->wrid) 162 return -ENOMEM; 163 164 err = mthca_buf_alloc(dev, srq->max << srq->wqe_shift, 165 MTHCA_MAX_DIRECT_SRQ_SIZE, 166 &srq->queue, &srq->is_direct, pd, 1, &srq->mr); 167 if (err) { 168 kfree(srq->wrid); 169 return err; 170 } 171 172 /* 173 * Now initialize the SRQ buffer so that all of the WQEs are 174 * linked into the list of free WQEs. In addition, set the 175 * scatter list L_Keys to the sentry value of 0x100. 176 */ 177 for (i = 0; i < srq->max; ++i) { 178 struct mthca_next_seg *next; 179 180 next = wqe = get_wqe(srq, i); 181 182 if (i < srq->max - 1) { 183 *wqe_to_link(wqe) = i + 1; 184 next->nda_op = htonl(((i + 1) << srq->wqe_shift) | 1); 185 } else { 186 *wqe_to_link(wqe) = -1; 187 next->nda_op = 0; 188 } 189 190 for (scatter = wqe + sizeof (struct mthca_next_seg); 191 (void *) scatter < wqe + (1 << srq->wqe_shift); 192 ++scatter) 193 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); 194 } 195 196 srq->last = get_wqe(srq, srq->max - 1); 197 198 return 0; 199} 200 201int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd, 202 struct ib_srq_attr *attr, struct mthca_srq *srq) 203{ 204 struct mthca_mailbox *mailbox; 205 u8 status; 206 int ds; 207 int err; 208 209 /* Sanity check SRQ size before proceeding */ 210 if (attr->max_wr > dev->limits.max_srq_wqes || 211 attr->max_sge > dev->limits.max_srq_sge) 212 return -EINVAL; 213 214 srq->max = attr->max_wr; 215 srq->max_gs = attr->max_sge; 216 srq->counter = 0; 217 218 if (mthca_is_memfree(dev)) 219 srq->max = roundup_pow_of_two(srq->max + 1); 220 else 221 srq->max = srq->max + 1; 222 223 ds = max(64UL, 224 roundup_pow_of_two(sizeof (struct mthca_next_seg) + 225 srq->max_gs * sizeof (struct mthca_data_seg))); 226 227 if (!mthca_is_memfree(dev) && (ds > dev->limits.max_desc_sz)) 228 return -EINVAL; 229 230 srq->wqe_shift = ilog2(ds); 231 232 srq->srqn = mthca_alloc(&dev->srq_table.alloc); 233 if (srq->srqn == -1) 234 return -ENOMEM; 235 236 if (mthca_is_memfree(dev)) { 237 err = mthca_table_get(dev, dev->srq_table.table, srq->srqn); 238 if (err) 239 goto err_out; 240 241 if (!pd->ibpd.uobject) { 242 srq->db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SRQ, 243 srq->srqn, &srq->db); 244 if (srq->db_index < 0) { 245 err = -ENOMEM; 246 goto err_out_icm; 247 } 248 } 249 } 250 251 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 252 if (IS_ERR(mailbox)) { 253 err = PTR_ERR(mailbox); 254 goto err_out_db; 255 } 256 257 err = mthca_alloc_srq_buf(dev, pd, srq); 258 if (err) 259 goto err_out_mailbox; 260 261 spin_lock_init(&srq->lock); 262 srq->refcount = 1; 263 init_waitqueue_head(&srq->wait); 264 mutex_init(&srq->mutex); 265 266 if (mthca_is_memfree(dev)) 267 mthca_arbel_init_srq_context(dev, pd, srq, mailbox->buf); 268 else 269 mthca_tavor_init_srq_context(dev, pd, srq, mailbox->buf); 270 271 err = mthca_SW2HW_SRQ(dev, mailbox, srq->srqn, &status); 272 273 if (err) { 274 mthca_warn(dev, "SW2HW_SRQ failed (%d)\n", err); 275 goto err_out_free_buf; 276 } 277 if (status) { 278 mthca_warn(dev, "SW2HW_SRQ returned status 0x%02x\n", 279 status); 280 err = -EINVAL; 281 goto err_out_free_buf; 282 } 283 284 spin_lock_irq(&dev->srq_table.lock); 285 if (mthca_array_set(&dev->srq_table.srq, 286 srq->srqn & (dev->limits.num_srqs - 1), 287 srq)) { 288 spin_unlock_irq(&dev->srq_table.lock); 289 goto err_out_free_srq; 290 } 291 spin_unlock_irq(&dev->srq_table.lock); 292 293 mthca_free_mailbox(dev, mailbox); 294 295 srq->first_free = 0; 296 srq->last_free = srq->max - 1; 297 298 attr->max_wr = srq->max - 1; 299 attr->max_sge = srq->max_gs; 300 301 return 0; 302 303err_out_free_srq: 304 err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status); 305 if (err) 306 mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err); 307 else if (status) 308 mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status); 309 310err_out_free_buf: 311 if (!pd->ibpd.uobject) 312 mthca_free_srq_buf(dev, srq); 313 314err_out_mailbox: 315 mthca_free_mailbox(dev, mailbox); 316 317err_out_db: 318 if (!pd->ibpd.uobject && mthca_is_memfree(dev)) 319 mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index); 320 321err_out_icm: 322 mthca_table_put(dev, dev->srq_table.table, srq->srqn); 323 324err_out: 325 mthca_free(&dev->srq_table.alloc, srq->srqn); 326 327 return err; 328} 329 330static inline int get_srq_refcount(struct mthca_dev *dev, struct mthca_srq *srq) 331{ 332 int c; 333 334 spin_lock_irq(&dev->srq_table.lock); 335 c = srq->refcount; 336 spin_unlock_irq(&dev->srq_table.lock); 337 338 return c; 339} 340 341void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq) 342{ 343 struct mthca_mailbox *mailbox; 344 int err; 345 u8 status; 346 347 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 348 if (IS_ERR(mailbox)) { 349 mthca_warn(dev, "No memory for mailbox to free SRQ.\n"); 350 return; 351 } 352 353 err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status); 354 if (err) 355 mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err); 356 else if (status) 357 mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status); 358 359 spin_lock_irq(&dev->srq_table.lock); 360 mthca_array_clear(&dev->srq_table.srq, 361 srq->srqn & (dev->limits.num_srqs - 1)); 362 --srq->refcount; 363 spin_unlock_irq(&dev->srq_table.lock); 364 365 wait_event(srq->wait, !get_srq_refcount(dev, srq)); 366 367 if (!srq->ibsrq.uobject) { 368 mthca_free_srq_buf(dev, srq); 369 if (mthca_is_memfree(dev)) 370 mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index); 371 } 372 373 mthca_table_put(dev, dev->srq_table.table, srq->srqn); 374 mthca_free(&dev->srq_table.alloc, srq->srqn); 375 mthca_free_mailbox(dev, mailbox); 376} 377 378int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 379 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata) 380{ 381 struct mthca_dev *dev = to_mdev(ibsrq->device); 382 struct mthca_srq *srq = to_msrq(ibsrq); 383 int ret; 384 u8 status; 385 386 /* We don't support resizing SRQs (yet?) */ 387 if (attr_mask & IB_SRQ_MAX_WR) 388 return -EINVAL; 389 390 if (attr_mask & IB_SRQ_LIMIT) { 391 u32 max_wr = mthca_is_memfree(dev) ? srq->max - 1 : srq->max; 392 if (attr->srq_limit > max_wr) 393 return -EINVAL; 394 395 mutex_lock(&srq->mutex); 396 ret = mthca_ARM_SRQ(dev, srq->srqn, attr->srq_limit, &status); 397 mutex_unlock(&srq->mutex); 398 399 if (ret) 400 return ret; 401 if (status) 402 return -EINVAL; 403 } 404 405 return 0; 406} 407 408int mthca_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr) 409{ 410 struct mthca_dev *dev = to_mdev(ibsrq->device); 411 struct mthca_srq *srq = to_msrq(ibsrq); 412 struct mthca_mailbox *mailbox; 413 struct mthca_arbel_srq_context *arbel_ctx; 414 struct mthca_tavor_srq_context *tavor_ctx; 415 u8 status; 416 int err; 417 418 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 419 if (IS_ERR(mailbox)) 420 return PTR_ERR(mailbox); 421 422 err = mthca_QUERY_SRQ(dev, srq->srqn, mailbox, &status); 423 if (err) 424 goto out; 425 426 if (mthca_is_memfree(dev)) { 427 arbel_ctx = mailbox->buf; 428 srq_attr->srq_limit = be16_to_cpu(arbel_ctx->limit_watermark); 429 } else { 430 tavor_ctx = mailbox->buf; 431 srq_attr->srq_limit = be16_to_cpu(tavor_ctx->limit_watermark); 432 } 433 434 srq_attr->max_wr = srq->max - 1; 435 srq_attr->max_sge = srq->max_gs; 436 437out: 438 mthca_free_mailbox(dev, mailbox); 439 440 return err; 441} 442 443void mthca_srq_event(struct mthca_dev *dev, u32 srqn, 444 enum ib_event_type event_type) 445{ 446 struct mthca_srq *srq; 447 struct ib_event event; 448 449 spin_lock(&dev->srq_table.lock); 450 srq = mthca_array_get(&dev->srq_table.srq, srqn & (dev->limits.num_srqs - 1)); 451 if (srq) 452 ++srq->refcount; 453 spin_unlock(&dev->srq_table.lock); 454 455 if (!srq) { 456 mthca_warn(dev, "Async event for bogus SRQ %08x\n", srqn); 457 return; 458 } 459 460 if (!srq->ibsrq.event_handler) 461 goto out; 462 463 event.device = &dev->ib_dev; 464 event.event = event_type; 465 event.element.srq = &srq->ibsrq; 466 srq->ibsrq.event_handler(&event, srq->ibsrq.srq_context); 467 468out: 469 spin_lock(&dev->srq_table.lock); 470 if (!--srq->refcount) 471 wake_up(&srq->wait); 472 spin_unlock(&dev->srq_table.lock); 473} 474 475/* 476 * This function must be called with IRQs disabled. 477 */ 478void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr) 479{ 480 int ind; 481 struct mthca_next_seg *last_free; 482 483 ind = wqe_addr >> srq->wqe_shift; 484 485 spin_lock(&srq->lock); 486 487 last_free = get_wqe(srq, srq->last_free); 488 *wqe_to_link(last_free) = ind; 489 last_free->nda_op = htonl((ind << srq->wqe_shift) | 1); 490 *wqe_to_link(get_wqe(srq, ind)) = -1; 491 srq->last_free = ind; 492 493 spin_unlock(&srq->lock); 494} 495 496int mthca_tavor_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 497 struct ib_recv_wr **bad_wr) 498{ 499 struct mthca_dev *dev = to_mdev(ibsrq->device); 500 struct mthca_srq *srq = to_msrq(ibsrq); 501 unsigned long flags; 502 int err = 0; 503 int first_ind; 504 int ind; 505 int next_ind; 506 int nreq; 507 int i; 508 void *wqe; 509 void *prev_wqe; 510 511 spin_lock_irqsave(&srq->lock, flags); 512 513 first_ind = srq->first_free; 514 515 for (nreq = 0; wr; wr = wr->next) { 516 ind = srq->first_free; 517 wqe = get_wqe(srq, ind); 518 next_ind = *wqe_to_link(wqe); 519 520 if (unlikely(next_ind < 0)) { 521 mthca_err(dev, "SRQ %06x full\n", srq->srqn); 522 err = -ENOMEM; 523 *bad_wr = wr; 524 break; 525 } 526 527 prev_wqe = srq->last; 528 srq->last = wqe; 529 530 ((struct mthca_next_seg *) wqe)->ee_nds = 0; 531 /* flags field will always remain 0 */ 532 533 wqe += sizeof (struct mthca_next_seg); 534 535 if (unlikely(wr->num_sge > srq->max_gs)) { 536 err = -EINVAL; 537 *bad_wr = wr; 538 srq->last = prev_wqe; 539 break; 540 } 541 542 for (i = 0; i < wr->num_sge; ++i) { 543 mthca_set_data_seg(wqe, wr->sg_list + i); 544 wqe += sizeof (struct mthca_data_seg); 545 } 546 547 if (i < srq->max_gs) 548 mthca_set_data_seg_inval(wqe); 549 550 ((struct mthca_next_seg *) prev_wqe)->ee_nds = 551 cpu_to_be32(MTHCA_NEXT_DBD); 552 553 srq->wrid[ind] = wr->wr_id; 554 srq->first_free = next_ind; 555 556 ++nreq; 557 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) { 558 nreq = 0; 559 560 /* 561 * Make sure that descriptors are written 562 * before doorbell is rung. 563 */ 564 wmb(); 565 566 mthca_write64(first_ind << srq->wqe_shift, srq->srqn << 8, 567 dev->kar + MTHCA_RECEIVE_DOORBELL, 568 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 569 570 first_ind = srq->first_free; 571 } 572 } 573 574 if (likely(nreq)) { 575 /* 576 * Make sure that descriptors are written before 577 * doorbell is rung. 578 */ 579 wmb(); 580 581 mthca_write64(first_ind << srq->wqe_shift, (srq->srqn << 8) | nreq, 582 dev->kar + MTHCA_RECEIVE_DOORBELL, 583 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 584 } 585 586 /* 587 * Make sure doorbells don't leak out of SRQ spinlock and 588 * reach the HCA out of order: 589 */ 590 mmiowb(); 591 592 spin_unlock_irqrestore(&srq->lock, flags); 593 return err; 594} 595 596int mthca_arbel_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 597 struct ib_recv_wr **bad_wr) 598{ 599 struct mthca_dev *dev = to_mdev(ibsrq->device); 600 struct mthca_srq *srq = to_msrq(ibsrq); 601 unsigned long flags; 602 int err = 0; 603 int ind; 604 int next_ind; 605 int nreq; 606 int i; 607 void *wqe; 608 609 spin_lock_irqsave(&srq->lock, flags); 610 611 for (nreq = 0; wr; ++nreq, wr = wr->next) { 612 ind = srq->first_free; 613 wqe = get_wqe(srq, ind); 614 next_ind = *wqe_to_link(wqe); 615 616 if (unlikely(next_ind < 0)) { 617 mthca_err(dev, "SRQ %06x full\n", srq->srqn); 618 err = -ENOMEM; 619 *bad_wr = wr; 620 break; 621 } 622 623 ((struct mthca_next_seg *) wqe)->ee_nds = 0; 624 /* flags field will always remain 0 */ 625 626 wqe += sizeof (struct mthca_next_seg); 627 628 if (unlikely(wr->num_sge > srq->max_gs)) { 629 err = -EINVAL; 630 *bad_wr = wr; 631 break; 632 } 633 634 for (i = 0; i < wr->num_sge; ++i) { 635 mthca_set_data_seg(wqe, wr->sg_list + i); 636 wqe += sizeof (struct mthca_data_seg); 637 } 638 639 if (i < srq->max_gs) 640 mthca_set_data_seg_inval(wqe); 641 642 srq->wrid[ind] = wr->wr_id; 643 srq->first_free = next_ind; 644 } 645 646 if (likely(nreq)) { 647 srq->counter += nreq; 648 649 /* 650 * Make sure that descriptors are written before 651 * we write doorbell record. 652 */ 653 wmb(); 654 *srq->db = cpu_to_be32(srq->counter); 655 } 656 657 spin_unlock_irqrestore(&srq->lock, flags); 658 return err; 659} 660 661int mthca_max_srq_sge(struct mthca_dev *dev) 662{ 663 if (mthca_is_memfree(dev)) 664 return dev->limits.max_sg; 665 666 /* 667 * SRQ allocations are based on powers of 2 for Tavor, 668 * (although they only need to be multiples of 16 bytes). 669 * 670 * Therefore, we need to base the max number of sg entries on 671 * the largest power of 2 descriptor size that is <= to the 672 * actual max WQE descriptor size, rather than return the 673 * max_sg value given by the firmware (which is based on WQE 674 * sizes as multiples of 16, not powers of 2). 675 * 676 * If SRQ implementation is changed for Tavor to be based on 677 * multiples of 16, the calculation below can be deleted and 678 * the FW max_sg value returned. 679 */ 680 return min_t(int, dev->limits.max_sg, 681 ((1 << (fls(dev->limits.max_desc_sz) - 1)) - 682 sizeof (struct mthca_next_seg)) / 683 sizeof (struct mthca_data_seg)); 684} 685 686int mthca_init_srq_table(struct mthca_dev *dev) 687{ 688 int err; 689 690 if (!(dev->mthca_flags & MTHCA_FLAG_SRQ)) 691 return 0; 692 693 spin_lock_init(&dev->srq_table.lock); 694 695 err = mthca_alloc_init(&dev->srq_table.alloc, 696 dev->limits.num_srqs, 697 dev->limits.num_srqs - 1, 698 dev->limits.reserved_srqs); 699 if (err) 700 return err; 701 702 err = mthca_array_init(&dev->srq_table.srq, 703 dev->limits.num_srqs); 704 if (err) 705 mthca_alloc_cleanup(&dev->srq_table.alloc); 706 707 return err; 708} 709 710void mthca_cleanup_srq_table(struct mthca_dev *dev) 711{ 712 if (!(dev->mthca_flags & MTHCA_FLAG_SRQ)) 713 return; 714 715 mthca_array_cleanup(&dev->srq_table.srq, dev->limits.num_srqs); 716 mthca_alloc_cleanup(&dev->srq_table.alloc); 717} 718