mthca_srq.c revision 59fef3b1e96217c6e736372ff8cc95cbcca1b6aa
1/* 2 * Copyright (c) 2005 Cisco Systems. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 * $Id: mthca_srq.c 3047 2005-08-10 03:59:35Z roland $ 33 */ 34 35#include <linux/slab.h> 36#include <linux/string.h> 37 38#include "mthca_dev.h" 39#include "mthca_cmd.h" 40#include "mthca_memfree.h" 41#include "mthca_wqe.h" 42 43enum { 44 MTHCA_MAX_DIRECT_SRQ_SIZE = 4 * PAGE_SIZE 45}; 46 47struct mthca_tavor_srq_context { 48 __be64 wqe_base_ds; /* low 6 bits is descriptor size */ 49 __be32 state_pd; 50 __be32 lkey; 51 __be32 uar; 52 __be16 limit_watermark; 53 __be16 wqe_cnt; 54 u32 reserved[2]; 55}; 56 57struct mthca_arbel_srq_context { 58 __be32 state_logsize_srqn; 59 __be32 lkey; 60 __be32 db_index; 61 __be32 logstride_usrpage; 62 __be64 wqe_base; 63 __be32 eq_pd; 64 __be16 limit_watermark; 65 __be16 wqe_cnt; 66 u16 reserved1; 67 __be16 wqe_counter; 68 u32 reserved2[3]; 69}; 70 71static void *get_wqe(struct mthca_srq *srq, int n) 72{ 73 if (srq->is_direct) 74 return srq->queue.direct.buf + (n << srq->wqe_shift); 75 else 76 return srq->queue.page_list[(n << srq->wqe_shift) >> PAGE_SHIFT].buf + 77 ((n << srq->wqe_shift) & (PAGE_SIZE - 1)); 78} 79 80/* 81 * Return a pointer to the location within a WQE that we're using as a 82 * link when the WQE is in the free list. We use the imm field 83 * because in the Tavor case, posting a WQE may overwrite the next 84 * segment of the previous WQE, but a receive WQE will never touch the 85 * imm field. This avoids corrupting our free list if the previous 86 * WQE has already completed and been put on the free list when we 87 * post the next WQE. 88 */ 89static inline int *wqe_to_link(void *wqe) 90{ 91 return (int *) (wqe + offsetof(struct mthca_next_seg, imm)); 92} 93 94static void mthca_tavor_init_srq_context(struct mthca_dev *dev, 95 struct mthca_pd *pd, 96 struct mthca_srq *srq, 97 struct mthca_tavor_srq_context *context) 98{ 99 memset(context, 0, sizeof *context); 100 101 context->wqe_base_ds = cpu_to_be64(1 << (srq->wqe_shift - 4)); 102 context->state_pd = cpu_to_be32(pd->pd_num); 103 context->lkey = cpu_to_be32(srq->mr.ibmr.lkey); 104 105 if (pd->ibpd.uobject) 106 context->uar = 107 cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index); 108 else 109 context->uar = cpu_to_be32(dev->driver_uar.index); 110} 111 112static void mthca_arbel_init_srq_context(struct mthca_dev *dev, 113 struct mthca_pd *pd, 114 struct mthca_srq *srq, 115 struct mthca_arbel_srq_context *context) 116{ 117 int logsize; 118 119 memset(context, 0, sizeof *context); 120 121 logsize = long_log2(srq->max) + srq->wqe_shift; 122 context->state_logsize_srqn = cpu_to_be32(logsize << 24 | srq->srqn); 123 context->lkey = cpu_to_be32(srq->mr.ibmr.lkey); 124 context->db_index = cpu_to_be32(srq->db_index); 125 context->logstride_usrpage = cpu_to_be32((srq->wqe_shift - 4) << 29); 126 if (pd->ibpd.uobject) 127 context->logstride_usrpage |= 128 cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index); 129 else 130 context->logstride_usrpage |= cpu_to_be32(dev->driver_uar.index); 131 context->eq_pd = cpu_to_be32(MTHCA_EQ_ASYNC << 24 | pd->pd_num); 132} 133 134static void mthca_free_srq_buf(struct mthca_dev *dev, struct mthca_srq *srq) 135{ 136 mthca_buf_free(dev, srq->max << srq->wqe_shift, &srq->queue, 137 srq->is_direct, &srq->mr); 138 kfree(srq->wrid); 139} 140 141static int mthca_alloc_srq_buf(struct mthca_dev *dev, struct mthca_pd *pd, 142 struct mthca_srq *srq) 143{ 144 struct mthca_data_seg *scatter; 145 void *wqe; 146 int err; 147 int i; 148 149 if (pd->ibpd.uobject) 150 return 0; 151 152 srq->wrid = kmalloc(srq->max * sizeof (u64), GFP_KERNEL); 153 if (!srq->wrid) 154 return -ENOMEM; 155 156 err = mthca_buf_alloc(dev, srq->max << srq->wqe_shift, 157 MTHCA_MAX_DIRECT_SRQ_SIZE, 158 &srq->queue, &srq->is_direct, pd, 1, &srq->mr); 159 if (err) { 160 kfree(srq->wrid); 161 return err; 162 } 163 164 /* 165 * Now initialize the SRQ buffer so that all of the WQEs are 166 * linked into the list of free WQEs. In addition, set the 167 * scatter list L_Keys to the sentry value of 0x100. 168 */ 169 for (i = 0; i < srq->max; ++i) { 170 wqe = get_wqe(srq, i); 171 172 *wqe_to_link(wqe) = i < srq->max - 1 ? i + 1 : -1; 173 174 for (scatter = wqe + sizeof (struct mthca_next_seg); 175 (void *) scatter < wqe + (1 << srq->wqe_shift); 176 ++scatter) 177 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); 178 } 179 180 srq->last = get_wqe(srq, srq->max - 1); 181 182 return 0; 183} 184 185int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd, 186 struct ib_srq_attr *attr, struct mthca_srq *srq) 187{ 188 struct mthca_mailbox *mailbox; 189 u8 status; 190 int ds; 191 int err; 192 193 /* Sanity check SRQ size before proceeding */ 194 if (attr->max_wr > dev->limits.max_srq_wqes || 195 attr->max_sge > dev->limits.max_srq_sge) 196 return -EINVAL; 197 198 srq->max = attr->max_wr; 199 srq->max_gs = attr->max_sge; 200 srq->counter = 0; 201 202 if (mthca_is_memfree(dev)) 203 srq->max = roundup_pow_of_two(srq->max + 1); 204 205 ds = max(64UL, 206 roundup_pow_of_two(sizeof (struct mthca_next_seg) + 207 srq->max_gs * sizeof (struct mthca_data_seg))); 208 209 if (!mthca_is_memfree(dev) && (ds > dev->limits.max_desc_sz)) 210 return -EINVAL; 211 212 srq->wqe_shift = long_log2(ds); 213 214 srq->srqn = mthca_alloc(&dev->srq_table.alloc); 215 if (srq->srqn == -1) 216 return -ENOMEM; 217 218 if (mthca_is_memfree(dev)) { 219 err = mthca_table_get(dev, dev->srq_table.table, srq->srqn); 220 if (err) 221 goto err_out; 222 223 if (!pd->ibpd.uobject) { 224 srq->db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SRQ, 225 srq->srqn, &srq->db); 226 if (srq->db_index < 0) { 227 err = -ENOMEM; 228 goto err_out_icm; 229 } 230 } 231 } 232 233 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 234 if (IS_ERR(mailbox)) { 235 err = PTR_ERR(mailbox); 236 goto err_out_db; 237 } 238 239 err = mthca_alloc_srq_buf(dev, pd, srq); 240 if (err) 241 goto err_out_mailbox; 242 243 spin_lock_init(&srq->lock); 244 atomic_set(&srq->refcount, 1); 245 init_waitqueue_head(&srq->wait); 246 247 if (mthca_is_memfree(dev)) 248 mthca_arbel_init_srq_context(dev, pd, srq, mailbox->buf); 249 else 250 mthca_tavor_init_srq_context(dev, pd, srq, mailbox->buf); 251 252 err = mthca_SW2HW_SRQ(dev, mailbox, srq->srqn, &status); 253 254 if (err) { 255 mthca_warn(dev, "SW2HW_SRQ failed (%d)\n", err); 256 goto err_out_free_buf; 257 } 258 if (status) { 259 mthca_warn(dev, "SW2HW_SRQ returned status 0x%02x\n", 260 status); 261 err = -EINVAL; 262 goto err_out_free_buf; 263 } 264 265 spin_lock_irq(&dev->srq_table.lock); 266 if (mthca_array_set(&dev->srq_table.srq, 267 srq->srqn & (dev->limits.num_srqs - 1), 268 srq)) { 269 spin_unlock_irq(&dev->srq_table.lock); 270 goto err_out_free_srq; 271 } 272 spin_unlock_irq(&dev->srq_table.lock); 273 274 mthca_free_mailbox(dev, mailbox); 275 276 srq->first_free = 0; 277 srq->last_free = srq->max - 1; 278 279 attr->max_wr = (mthca_is_memfree(dev)) ? srq->max - 1 : srq->max; 280 attr->max_sge = srq->max_gs; 281 282 return 0; 283 284err_out_free_srq: 285 err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status); 286 if (err) 287 mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err); 288 else if (status) 289 mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status); 290 291err_out_free_buf: 292 if (!pd->ibpd.uobject) 293 mthca_free_srq_buf(dev, srq); 294 295err_out_mailbox: 296 mthca_free_mailbox(dev, mailbox); 297 298err_out_db: 299 if (!pd->ibpd.uobject && mthca_is_memfree(dev)) 300 mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index); 301 302err_out_icm: 303 mthca_table_put(dev, dev->srq_table.table, srq->srqn); 304 305err_out: 306 mthca_free(&dev->srq_table.alloc, srq->srqn); 307 308 return err; 309} 310 311void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq) 312{ 313 struct mthca_mailbox *mailbox; 314 int err; 315 u8 status; 316 317 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 318 if (IS_ERR(mailbox)) { 319 mthca_warn(dev, "No memory for mailbox to free SRQ.\n"); 320 return; 321 } 322 323 err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status); 324 if (err) 325 mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err); 326 else if (status) 327 mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status); 328 329 spin_lock_irq(&dev->srq_table.lock); 330 mthca_array_clear(&dev->srq_table.srq, 331 srq->srqn & (dev->limits.num_srqs - 1)); 332 spin_unlock_irq(&dev->srq_table.lock); 333 334 atomic_dec(&srq->refcount); 335 wait_event(srq->wait, !atomic_read(&srq->refcount)); 336 337 if (!srq->ibsrq.uobject) { 338 mthca_free_srq_buf(dev, srq); 339 if (mthca_is_memfree(dev)) 340 mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index); 341 } 342 343 mthca_table_put(dev, dev->srq_table.table, srq->srqn); 344 mthca_free(&dev->srq_table.alloc, srq->srqn); 345 mthca_free_mailbox(dev, mailbox); 346} 347 348int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 349 enum ib_srq_attr_mask attr_mask) 350{ 351 struct mthca_dev *dev = to_mdev(ibsrq->device); 352 struct mthca_srq *srq = to_msrq(ibsrq); 353 int ret; 354 u8 status; 355 356 /* We don't support resizing SRQs (yet?) */ 357 if (attr_mask & IB_SRQ_MAX_WR) 358 return -EINVAL; 359 360 if (attr_mask & IB_SRQ_LIMIT) { 361 if (attr->srq_limit > srq->max) 362 return -EINVAL; 363 ret = mthca_ARM_SRQ(dev, srq->srqn, attr->srq_limit, &status); 364 if (ret) 365 return ret; 366 if (status) 367 return -EINVAL; 368 } 369 370 return 0; 371} 372 373int mthca_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr) 374{ 375 struct mthca_dev *dev = to_mdev(ibsrq->device); 376 struct mthca_srq *srq = to_msrq(ibsrq); 377 struct mthca_mailbox *mailbox; 378 struct mthca_arbel_srq_context *arbel_ctx; 379 struct mthca_tavor_srq_context *tavor_ctx; 380 u8 status; 381 int err; 382 383 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 384 if (IS_ERR(mailbox)) 385 return PTR_ERR(mailbox); 386 387 err = mthca_QUERY_SRQ(dev, srq->srqn, mailbox, &status); 388 if (err) 389 goto out; 390 391 if (mthca_is_memfree(dev)) { 392 arbel_ctx = mailbox->buf; 393 srq_attr->srq_limit = be16_to_cpu(arbel_ctx->limit_watermark); 394 } else { 395 tavor_ctx = mailbox->buf; 396 srq_attr->srq_limit = be16_to_cpu(tavor_ctx->limit_watermark); 397 } 398 399 srq_attr->max_wr = (mthca_is_memfree(dev)) ? srq->max - 1 : srq->max; 400 srq_attr->max_sge = srq->max_gs; 401 402out: 403 mthca_free_mailbox(dev, mailbox); 404 405 return err; 406} 407 408void mthca_srq_event(struct mthca_dev *dev, u32 srqn, 409 enum ib_event_type event_type) 410{ 411 struct mthca_srq *srq; 412 struct ib_event event; 413 414 spin_lock(&dev->srq_table.lock); 415 srq = mthca_array_get(&dev->srq_table.srq, srqn & (dev->limits.num_srqs - 1)); 416 if (srq) 417 atomic_inc(&srq->refcount); 418 spin_unlock(&dev->srq_table.lock); 419 420 if (!srq) { 421 mthca_warn(dev, "Async event for bogus SRQ %08x\n", srqn); 422 return; 423 } 424 425 if (!srq->ibsrq.event_handler) 426 goto out; 427 428 event.device = &dev->ib_dev; 429 event.event = event_type; 430 event.element.srq = &srq->ibsrq; 431 srq->ibsrq.event_handler(&event, srq->ibsrq.srq_context); 432 433out: 434 if (atomic_dec_and_test(&srq->refcount)) 435 wake_up(&srq->wait); 436} 437 438/* 439 * This function must be called with IRQs disabled. 440 */ 441void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr) 442{ 443 int ind; 444 445 ind = wqe_addr >> srq->wqe_shift; 446 447 spin_lock(&srq->lock); 448 449 if (likely(srq->first_free >= 0)) 450 *wqe_to_link(get_wqe(srq, srq->last_free)) = ind; 451 else 452 srq->first_free = ind; 453 454 *wqe_to_link(get_wqe(srq, ind)) = -1; 455 srq->last_free = ind; 456 457 spin_unlock(&srq->lock); 458} 459 460int mthca_tavor_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 461 struct ib_recv_wr **bad_wr) 462{ 463 struct mthca_dev *dev = to_mdev(ibsrq->device); 464 struct mthca_srq *srq = to_msrq(ibsrq); 465 __be32 doorbell[2]; 466 unsigned long flags; 467 int err = 0; 468 int first_ind; 469 int ind; 470 int next_ind; 471 int nreq; 472 int i; 473 void *wqe; 474 void *prev_wqe; 475 476 spin_lock_irqsave(&srq->lock, flags); 477 478 first_ind = srq->first_free; 479 480 for (nreq = 0; wr; ++nreq, wr = wr->next) { 481 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) { 482 nreq = 0; 483 484 doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift); 485 doorbell[1] = cpu_to_be32(srq->srqn << 8); 486 487 /* 488 * Make sure that descriptors are written 489 * before doorbell is rung. 490 */ 491 wmb(); 492 493 mthca_write64(doorbell, 494 dev->kar + MTHCA_RECEIVE_DOORBELL, 495 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 496 497 first_ind = srq->first_free; 498 } 499 500 ind = srq->first_free; 501 502 if (ind < 0) { 503 mthca_err(dev, "SRQ %06x full\n", srq->srqn); 504 err = -ENOMEM; 505 *bad_wr = wr; 506 break; 507 } 508 509 wqe = get_wqe(srq, ind); 510 next_ind = *wqe_to_link(wqe); 511 512 if (next_ind < 0) { 513 mthca_err(dev, "SRQ %06x full\n", srq->srqn); 514 err = -ENOMEM; 515 *bad_wr = wr; 516 break; 517 } 518 519 prev_wqe = srq->last; 520 srq->last = wqe; 521 522 ((struct mthca_next_seg *) wqe)->nda_op = 0; 523 ((struct mthca_next_seg *) wqe)->ee_nds = 0; 524 /* flags field will always remain 0 */ 525 526 wqe += sizeof (struct mthca_next_seg); 527 528 if (unlikely(wr->num_sge > srq->max_gs)) { 529 err = -EINVAL; 530 *bad_wr = wr; 531 srq->last = prev_wqe; 532 break; 533 } 534 535 for (i = 0; i < wr->num_sge; ++i) { 536 ((struct mthca_data_seg *) wqe)->byte_count = 537 cpu_to_be32(wr->sg_list[i].length); 538 ((struct mthca_data_seg *) wqe)->lkey = 539 cpu_to_be32(wr->sg_list[i].lkey); 540 ((struct mthca_data_seg *) wqe)->addr = 541 cpu_to_be64(wr->sg_list[i].addr); 542 wqe += sizeof (struct mthca_data_seg); 543 } 544 545 if (i < srq->max_gs) { 546 ((struct mthca_data_seg *) wqe)->byte_count = 0; 547 ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); 548 ((struct mthca_data_seg *) wqe)->addr = 0; 549 } 550 551 ((struct mthca_next_seg *) prev_wqe)->nda_op = 552 cpu_to_be32((ind << srq->wqe_shift) | 1); 553 wmb(); 554 ((struct mthca_next_seg *) prev_wqe)->ee_nds = 555 cpu_to_be32(MTHCA_NEXT_DBD); 556 557 srq->wrid[ind] = wr->wr_id; 558 srq->first_free = next_ind; 559 } 560 561 if (likely(nreq)) { 562 doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift); 563 doorbell[1] = cpu_to_be32((srq->srqn << 8) | nreq); 564 565 /* 566 * Make sure that descriptors are written before 567 * doorbell is rung. 568 */ 569 wmb(); 570 571 mthca_write64(doorbell, 572 dev->kar + MTHCA_RECEIVE_DOORBELL, 573 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 574 } 575 576 spin_unlock_irqrestore(&srq->lock, flags); 577 return err; 578} 579 580int mthca_arbel_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 581 struct ib_recv_wr **bad_wr) 582{ 583 struct mthca_dev *dev = to_mdev(ibsrq->device); 584 struct mthca_srq *srq = to_msrq(ibsrq); 585 unsigned long flags; 586 int err = 0; 587 int ind; 588 int next_ind; 589 int nreq; 590 int i; 591 void *wqe; 592 593 spin_lock_irqsave(&srq->lock, flags); 594 595 for (nreq = 0; wr; ++nreq, wr = wr->next) { 596 ind = srq->first_free; 597 598 if (ind < 0) { 599 mthca_err(dev, "SRQ %06x full\n", srq->srqn); 600 err = -ENOMEM; 601 *bad_wr = wr; 602 break; 603 } 604 605 wqe = get_wqe(srq, ind); 606 next_ind = *wqe_to_link(wqe); 607 608 if (next_ind < 0) { 609 mthca_err(dev, "SRQ %06x full\n", srq->srqn); 610 err = -ENOMEM; 611 *bad_wr = wr; 612 break; 613 } 614 615 ((struct mthca_next_seg *) wqe)->nda_op = 616 cpu_to_be32((next_ind << srq->wqe_shift) | 1); 617 ((struct mthca_next_seg *) wqe)->ee_nds = 0; 618 /* flags field will always remain 0 */ 619 620 wqe += sizeof (struct mthca_next_seg); 621 622 if (unlikely(wr->num_sge > srq->max_gs)) { 623 err = -EINVAL; 624 *bad_wr = wr; 625 break; 626 } 627 628 for (i = 0; i < wr->num_sge; ++i) { 629 ((struct mthca_data_seg *) wqe)->byte_count = 630 cpu_to_be32(wr->sg_list[i].length); 631 ((struct mthca_data_seg *) wqe)->lkey = 632 cpu_to_be32(wr->sg_list[i].lkey); 633 ((struct mthca_data_seg *) wqe)->addr = 634 cpu_to_be64(wr->sg_list[i].addr); 635 wqe += sizeof (struct mthca_data_seg); 636 } 637 638 if (i < srq->max_gs) { 639 ((struct mthca_data_seg *) wqe)->byte_count = 0; 640 ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); 641 ((struct mthca_data_seg *) wqe)->addr = 0; 642 } 643 644 srq->wrid[ind] = wr->wr_id; 645 srq->first_free = next_ind; 646 } 647 648 if (likely(nreq)) { 649 srq->counter += nreq; 650 651 /* 652 * Make sure that descriptors are written before 653 * we write doorbell record. 654 */ 655 wmb(); 656 *srq->db = cpu_to_be32(srq->counter); 657 } 658 659 spin_unlock_irqrestore(&srq->lock, flags); 660 return err; 661} 662 663int mthca_max_srq_sge(struct mthca_dev *dev) 664{ 665 if (mthca_is_memfree(dev)) 666 return dev->limits.max_sg; 667 668 /* 669 * SRQ allocations are based on powers of 2 for Tavor, 670 * (although they only need to be multiples of 16 bytes). 671 * 672 * Therefore, we need to base the max number of sg entries on 673 * the largest power of 2 descriptor size that is <= to the 674 * actual max WQE descriptor size, rather than return the 675 * max_sg value given by the firmware (which is based on WQE 676 * sizes as multiples of 16, not powers of 2). 677 * 678 * If SRQ implementation is changed for Tavor to be based on 679 * multiples of 16, the calculation below can be deleted and 680 * the FW max_sg value returned. 681 */ 682 return min_t(int, dev->limits.max_sg, 683 ((1 << (fls(dev->limits.max_desc_sz) - 1)) - 684 sizeof (struct mthca_next_seg)) / 685 sizeof (struct mthca_data_seg)); 686} 687 688int __devinit mthca_init_srq_table(struct mthca_dev *dev) 689{ 690 int err; 691 692 if (!(dev->mthca_flags & MTHCA_FLAG_SRQ)) 693 return 0; 694 695 spin_lock_init(&dev->srq_table.lock); 696 697 err = mthca_alloc_init(&dev->srq_table.alloc, 698 dev->limits.num_srqs, 699 dev->limits.num_srqs - 1, 700 dev->limits.reserved_srqs); 701 if (err) 702 return err; 703 704 err = mthca_array_init(&dev->srq_table.srq, 705 dev->limits.num_srqs); 706 if (err) 707 mthca_alloc_cleanup(&dev->srq_table.alloc); 708 709 return err; 710} 711 712void mthca_cleanup_srq_table(struct mthca_dev *dev) 713{ 714 if (!(dev->mthca_flags & MTHCA_FLAG_SRQ)) 715 return; 716 717 mthca_array_cleanup(&dev->srq_table.srq, dev->limits.num_srqs); 718 mthca_alloc_cleanup(&dev->srq_table.alloc); 719} 720