ocrdma_hw.c revision f24ceba6b6454f68f456981be2a337b6390d9aa0
1/******************************************************************* 2 * This file is part of the Emulex RoCE Device Driver for * 3 * RoCE (RDMA over Converged Ethernet) CNA Adapters. * 4 * Copyright (C) 2008-2012 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 * 20 * Contact Information: 21 * linux-drivers@emulex.com 22 * 23 * Emulex 24 * 3333 Susan Street 25 * Costa Mesa, CA 92626 26 *******************************************************************/ 27 28#include <linux/sched.h> 29#include <linux/interrupt.h> 30#include <linux/log2.h> 31#include <linux/dma-mapping.h> 32 33#include <rdma/ib_verbs.h> 34#include <rdma/ib_user_verbs.h> 35#include <rdma/ib_addr.h> 36 37#include "ocrdma.h" 38#include "ocrdma_hw.h" 39#include "ocrdma_verbs.h" 40#include "ocrdma_ah.h" 41 42enum mbx_status { 43 OCRDMA_MBX_STATUS_FAILED = 1, 44 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3, 45 OCRDMA_MBX_STATUS_OOR = 100, 46 OCRDMA_MBX_STATUS_INVALID_PD = 101, 47 OCRDMA_MBX_STATUS_PD_INUSE = 102, 48 OCRDMA_MBX_STATUS_INVALID_CQ = 103, 49 OCRDMA_MBX_STATUS_INVALID_QP = 104, 50 OCRDMA_MBX_STATUS_INVALID_LKEY = 105, 51 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106, 52 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107, 53 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108, 54 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109, 55 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110, 56 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111, 57 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112, 58 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113, 59 OCRDMA_MBX_STATUS_MW_BOUND = 114, 60 OCRDMA_MBX_STATUS_INVALID_VA = 115, 61 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116, 62 OCRDMA_MBX_STATUS_INVALID_FBO = 117, 63 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118, 64 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119, 65 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120, 66 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121, 67 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129, 68 OCRDMA_MBX_STATUS_SRQ_ERROR = 133, 69 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134, 70 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135, 71 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136, 72 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137, 73 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138, 74 OCRDMA_MBX_STATUS_QP_BOUND = 130, 75 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139, 76 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140, 77 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141, 78 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142, 79 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143, 80 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144 81}; 82 83enum additional_status { 84 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22 85}; 86 87enum cqe_status { 88 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1, 89 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2, 90 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3, 91 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4, 92 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5 93}; 94 95static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq) 96{ 97 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe)); 98} 99 100static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq) 101{ 102 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1); 103} 104 105static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev) 106{ 107 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *) 108 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe))); 109 110 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK)) 111 return NULL; 112 return cqe; 113} 114 115static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev) 116{ 117 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1); 118} 119 120static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev) 121{ 122 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe)); 123} 124 125static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev) 126{ 127 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1); 128} 129 130static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev) 131{ 132 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe)); 133} 134 135enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps) 136{ 137 switch (qps) { 138 case OCRDMA_QPS_RST: 139 return IB_QPS_RESET; 140 case OCRDMA_QPS_INIT: 141 return IB_QPS_INIT; 142 case OCRDMA_QPS_RTR: 143 return IB_QPS_RTR; 144 case OCRDMA_QPS_RTS: 145 return IB_QPS_RTS; 146 case OCRDMA_QPS_SQD: 147 case OCRDMA_QPS_SQ_DRAINING: 148 return IB_QPS_SQD; 149 case OCRDMA_QPS_SQE: 150 return IB_QPS_SQE; 151 case OCRDMA_QPS_ERR: 152 return IB_QPS_ERR; 153 }; 154 return IB_QPS_ERR; 155} 156 157static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps) 158{ 159 switch (qps) { 160 case IB_QPS_RESET: 161 return OCRDMA_QPS_RST; 162 case IB_QPS_INIT: 163 return OCRDMA_QPS_INIT; 164 case IB_QPS_RTR: 165 return OCRDMA_QPS_RTR; 166 case IB_QPS_RTS: 167 return OCRDMA_QPS_RTS; 168 case IB_QPS_SQD: 169 return OCRDMA_QPS_SQD; 170 case IB_QPS_SQE: 171 return OCRDMA_QPS_SQE; 172 case IB_QPS_ERR: 173 return OCRDMA_QPS_ERR; 174 }; 175 return OCRDMA_QPS_ERR; 176} 177 178static int ocrdma_get_mbx_errno(u32 status) 179{ 180 int err_num; 181 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >> 182 OCRDMA_MBX_RSP_STATUS_SHIFT; 183 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >> 184 OCRDMA_MBX_RSP_ASTATUS_SHIFT; 185 186 switch (mbox_status) { 187 case OCRDMA_MBX_STATUS_OOR: 188 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS: 189 err_num = -EAGAIN; 190 break; 191 192 case OCRDMA_MBX_STATUS_INVALID_PD: 193 case OCRDMA_MBX_STATUS_INVALID_CQ: 194 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID: 195 case OCRDMA_MBX_STATUS_INVALID_QP: 196 case OCRDMA_MBX_STATUS_INVALID_CHANGE: 197 case OCRDMA_MBX_STATUS_MTU_EXCEEDS: 198 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER: 199 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID: 200 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS: 201 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD: 202 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY: 203 case OCRDMA_MBX_STATUS_INVALID_LKEY: 204 case OCRDMA_MBX_STATUS_INVALID_VA: 205 case OCRDMA_MBX_STATUS_INVALID_LENGTH: 206 case OCRDMA_MBX_STATUS_INVALID_FBO: 207 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS: 208 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE: 209 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP: 210 case OCRDMA_MBX_STATUS_SRQ_ERROR: 211 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS: 212 err_num = -EINVAL; 213 break; 214 215 case OCRDMA_MBX_STATUS_PD_INUSE: 216 case OCRDMA_MBX_STATUS_QP_BOUND: 217 case OCRDMA_MBX_STATUS_MW_STILL_BOUND: 218 case OCRDMA_MBX_STATUS_MW_BOUND: 219 err_num = -EBUSY; 220 break; 221 222 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS: 223 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS: 224 case OCRDMA_MBX_STATUS_RQE_EXCEEDS: 225 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS: 226 case OCRDMA_MBX_STATUS_ORD_EXCEEDS: 227 case OCRDMA_MBX_STATUS_IRD_EXCEEDS: 228 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS: 229 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS: 230 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS: 231 err_num = -ENOBUFS; 232 break; 233 234 case OCRDMA_MBX_STATUS_FAILED: 235 switch (add_status) { 236 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES: 237 err_num = -EAGAIN; 238 break; 239 } 240 default: 241 err_num = -EFAULT; 242 } 243 return err_num; 244} 245 246static int ocrdma_get_mbx_cqe_errno(u16 cqe_status) 247{ 248 int err_num = -EINVAL; 249 250 switch (cqe_status) { 251 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES: 252 err_num = -EPERM; 253 break; 254 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER: 255 err_num = -EINVAL; 256 break; 257 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES: 258 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING: 259 err_num = -EINVAL; 260 break; 261 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED: 262 default: 263 err_num = -EINVAL; 264 break; 265 } 266 return err_num; 267} 268 269void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed, 270 bool solicited, u16 cqe_popped) 271{ 272 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK; 273 274 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) << 275 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT); 276 277 if (armed) 278 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT); 279 if (solicited) 280 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT); 281 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT); 282 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET); 283} 284 285static void ocrdma_ring_mq_db(struct ocrdma_dev *dev) 286{ 287 u32 val = 0; 288 289 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK; 290 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT; 291 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET); 292} 293 294static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id, 295 bool arm, bool clear_int, u16 num_eqe) 296{ 297 u32 val = 0; 298 299 val |= eq_id & OCRDMA_EQ_ID_MASK; 300 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT); 301 if (arm) 302 val |= (1 << OCRDMA_REARM_SHIFT); 303 if (clear_int) 304 val |= (1 << OCRDMA_EQ_CLR_SHIFT); 305 val |= (1 << OCRDMA_EQ_TYPE_SHIFT); 306 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT); 307 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET); 308} 309 310static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr, 311 u8 opcode, u8 subsys, u32 cmd_len) 312{ 313 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT)); 314 cmd_hdr->timeout = 20; /* seconds */ 315 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr); 316} 317 318static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len) 319{ 320 struct ocrdma_mqe *mqe; 321 322 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL); 323 if (!mqe) 324 return NULL; 325 mqe->hdr.spcl_sge_cnt_emb |= 326 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) & 327 OCRDMA_MQE_HDR_EMB_MASK; 328 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr); 329 330 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE, 331 mqe->hdr.pyld_len); 332 return mqe; 333} 334 335static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q) 336{ 337 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma); 338} 339 340static int ocrdma_alloc_q(struct ocrdma_dev *dev, 341 struct ocrdma_queue_info *q, u16 len, u16 entry_size) 342{ 343 memset(q, 0, sizeof(*q)); 344 q->len = len; 345 q->entry_size = entry_size; 346 q->size = len * entry_size; 347 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size, 348 &q->dma, GFP_KERNEL); 349 if (!q->va) 350 return -ENOMEM; 351 memset(q->va, 0, q->size); 352 return 0; 353} 354 355static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt, 356 dma_addr_t host_pa, int hw_page_size) 357{ 358 int i; 359 360 for (i = 0; i < cnt; i++) { 361 q_pa[i].lo = (u32) (host_pa & 0xffffffff); 362 q_pa[i].hi = (u32) upper_32_bits(host_pa); 363 host_pa += hw_page_size; 364 } 365} 366 367static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q, 368 int queue_type) 369{ 370 u8 opcode = 0; 371 int status; 372 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd; 373 374 switch (queue_type) { 375 case QTYPE_MCCQ: 376 opcode = OCRDMA_CMD_DELETE_MQ; 377 break; 378 case QTYPE_CQ: 379 opcode = OCRDMA_CMD_DELETE_CQ; 380 break; 381 case QTYPE_EQ: 382 opcode = OCRDMA_CMD_DELETE_EQ; 383 break; 384 default: 385 BUG(); 386 } 387 memset(cmd, 0, sizeof(*cmd)); 388 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); 389 cmd->id = q->id; 390 391 status = be_roce_mcc_cmd(dev->nic_info.netdev, 392 cmd, sizeof(*cmd), NULL, NULL); 393 if (!status) 394 q->created = false; 395 return status; 396} 397 398static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq) 399{ 400 int status; 401 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd; 402 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd; 403 404 memset(cmd, 0, sizeof(*cmd)); 405 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON, 406 sizeof(*cmd)); 407 408 cmd->req.rsvd_version = 2; 409 cmd->num_pages = 4; 410 cmd->valid = OCRDMA_CREATE_EQ_VALID; 411 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT; 412 413 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma, 414 PAGE_SIZE_4K); 415 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL, 416 NULL); 417 if (!status) { 418 eq->q.id = rsp->vector_eqid & 0xffff; 419 eq->vector = (rsp->vector_eqid >> 16) & 0xffff; 420 eq->q.created = true; 421 } 422 return status; 423} 424 425static int ocrdma_create_eq(struct ocrdma_dev *dev, 426 struct ocrdma_eq *eq, u16 q_len) 427{ 428 int status; 429 430 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN, 431 sizeof(struct ocrdma_eqe)); 432 if (status) 433 return status; 434 435 status = ocrdma_mbx_create_eq(dev, eq); 436 if (status) 437 goto mbx_err; 438 eq->dev = dev; 439 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0); 440 441 return 0; 442mbx_err: 443 ocrdma_free_q(dev, &eq->q); 444 return status; 445} 446 447static int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq) 448{ 449 int irq; 450 451 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) 452 irq = dev->nic_info.pdev->irq; 453 else 454 irq = dev->nic_info.msix.vector_list[eq->vector]; 455 return irq; 456} 457 458static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq) 459{ 460 if (eq->q.created) { 461 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ); 462 ocrdma_free_q(dev, &eq->q); 463 } 464} 465 466static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq) 467{ 468 int irq; 469 470 /* disarm EQ so that interrupts are not generated 471 * during freeing and EQ delete is in progress. 472 */ 473 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0); 474 475 irq = ocrdma_get_irq(dev, eq); 476 free_irq(irq, eq); 477 _ocrdma_destroy_eq(dev, eq); 478} 479 480static void ocrdma_destroy_eqs(struct ocrdma_dev *dev) 481{ 482 int i; 483 484 for (i = 0; i < dev->eq_cnt; i++) 485 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]); 486} 487 488static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev, 489 struct ocrdma_queue_info *cq, 490 struct ocrdma_queue_info *eq) 491{ 492 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd; 493 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd; 494 int status; 495 496 memset(cmd, 0, sizeof(*cmd)); 497 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ, 498 OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); 499 500 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2; 501 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) << 502 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT; 503 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size); 504 505 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS; 506 cmd->eqn = eq->id; 507 cmd->cqe_count = cq->size / sizeof(struct ocrdma_mcqe); 508 509 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE, 510 cq->dma, PAGE_SIZE_4K); 511 status = be_roce_mcc_cmd(dev->nic_info.netdev, 512 cmd, sizeof(*cmd), NULL, NULL); 513 if (!status) { 514 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK); 515 cq->created = true; 516 } 517 return status; 518} 519 520static u32 ocrdma_encoded_q_len(int q_len) 521{ 522 u32 len_encoded = fls(q_len); /* log2(len) + 1 */ 523 524 if (len_encoded == 16) 525 len_encoded = 0; 526 return len_encoded; 527} 528 529static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev, 530 struct ocrdma_queue_info *mq, 531 struct ocrdma_queue_info *cq) 532{ 533 int num_pages, status; 534 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd; 535 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd; 536 struct ocrdma_pa *pa; 537 538 memset(cmd, 0, sizeof(*cmd)); 539 num_pages = PAGES_4K_SPANNED(mq->va, mq->size); 540 541 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT, 542 OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); 543 cmd->req.rsvd_version = 1; 544 cmd->cqid_pages = num_pages; 545 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT); 546 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID; 547 cmd->async_event_bitmap = Bit(20); 548 cmd->async_cqid_ringsize = cq->id; 549 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) << 550 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT); 551 cmd->valid = OCRDMA_CREATE_MQ_VALID; 552 pa = &cmd->pa[0]; 553 554 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K); 555 status = be_roce_mcc_cmd(dev->nic_info.netdev, 556 cmd, sizeof(*cmd), NULL, NULL); 557 if (!status) { 558 mq->id = rsp->id; 559 mq->created = true; 560 } 561 return status; 562} 563 564static int ocrdma_create_mq(struct ocrdma_dev *dev) 565{ 566 int status; 567 568 /* Alloc completion queue for Mailbox queue */ 569 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN, 570 sizeof(struct ocrdma_mcqe)); 571 if (status) 572 goto alloc_err; 573 574 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q); 575 if (status) 576 goto mbx_cq_free; 577 578 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx)); 579 init_waitqueue_head(&dev->mqe_ctx.cmd_wait); 580 mutex_init(&dev->mqe_ctx.lock); 581 582 /* Alloc Mailbox queue */ 583 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN, 584 sizeof(struct ocrdma_mqe)); 585 if (status) 586 goto mbx_cq_destroy; 587 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq); 588 if (status) 589 goto mbx_q_free; 590 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0); 591 return 0; 592 593mbx_q_free: 594 ocrdma_free_q(dev, &dev->mq.sq); 595mbx_cq_destroy: 596 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ); 597mbx_cq_free: 598 ocrdma_free_q(dev, &dev->mq.cq); 599alloc_err: 600 return status; 601} 602 603static void ocrdma_destroy_mq(struct ocrdma_dev *dev) 604{ 605 struct ocrdma_queue_info *mbxq, *cq; 606 607 /* mqe_ctx lock synchronizes with any other pending cmds. */ 608 mutex_lock(&dev->mqe_ctx.lock); 609 mbxq = &dev->mq.sq; 610 if (mbxq->created) { 611 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ); 612 ocrdma_free_q(dev, mbxq); 613 } 614 mutex_unlock(&dev->mqe_ctx.lock); 615 616 cq = &dev->mq.cq; 617 if (cq->created) { 618 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ); 619 ocrdma_free_q(dev, cq); 620 } 621} 622 623static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev, 624 struct ocrdma_qp *qp) 625{ 626 enum ib_qp_state new_ib_qps = IB_QPS_ERR; 627 enum ib_qp_state old_ib_qps; 628 629 if (qp == NULL) 630 BUG(); 631 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps); 632} 633 634static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev, 635 struct ocrdma_ae_mcqe *cqe) 636{ 637 struct ocrdma_qp *qp = NULL; 638 struct ocrdma_cq *cq = NULL; 639 struct ib_event ib_evt; 640 int cq_event = 0; 641 int qp_event = 1; 642 int srq_event = 0; 643 int dev_event = 0; 644 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >> 645 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT; 646 647 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID) 648 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK]; 649 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID) 650 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK]; 651 652 ib_evt.device = &dev->ibdev; 653 654 switch (type) { 655 case OCRDMA_CQ_ERROR: 656 ib_evt.element.cq = &cq->ibcq; 657 ib_evt.event = IB_EVENT_CQ_ERR; 658 cq_event = 1; 659 qp_event = 0; 660 break; 661 case OCRDMA_CQ_OVERRUN_ERROR: 662 ib_evt.element.cq = &cq->ibcq; 663 ib_evt.event = IB_EVENT_CQ_ERR; 664 break; 665 case OCRDMA_CQ_QPCAT_ERROR: 666 ib_evt.element.qp = &qp->ibqp; 667 ib_evt.event = IB_EVENT_QP_FATAL; 668 ocrdma_process_qpcat_error(dev, qp); 669 break; 670 case OCRDMA_QP_ACCESS_ERROR: 671 ib_evt.element.qp = &qp->ibqp; 672 ib_evt.event = IB_EVENT_QP_ACCESS_ERR; 673 break; 674 case OCRDMA_QP_COMM_EST_EVENT: 675 ib_evt.element.qp = &qp->ibqp; 676 ib_evt.event = IB_EVENT_COMM_EST; 677 break; 678 case OCRDMA_SQ_DRAINED_EVENT: 679 ib_evt.element.qp = &qp->ibqp; 680 ib_evt.event = IB_EVENT_SQ_DRAINED; 681 break; 682 case OCRDMA_DEVICE_FATAL_EVENT: 683 ib_evt.element.port_num = 1; 684 ib_evt.event = IB_EVENT_DEVICE_FATAL; 685 qp_event = 0; 686 dev_event = 1; 687 break; 688 case OCRDMA_SRQCAT_ERROR: 689 ib_evt.element.srq = &qp->srq->ibsrq; 690 ib_evt.event = IB_EVENT_SRQ_ERR; 691 srq_event = 1; 692 qp_event = 0; 693 break; 694 case OCRDMA_SRQ_LIMIT_EVENT: 695 ib_evt.element.srq = &qp->srq->ibsrq; 696 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED; 697 srq_event = 1; 698 qp_event = 0; 699 break; 700 case OCRDMA_QP_LAST_WQE_EVENT: 701 ib_evt.element.qp = &qp->ibqp; 702 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED; 703 break; 704 default: 705 cq_event = 0; 706 qp_event = 0; 707 srq_event = 0; 708 dev_event = 0; 709 pr_err("%s() unknown type=0x%x\n", __func__, type); 710 break; 711 } 712 713 if (qp_event) { 714 if (qp->ibqp.event_handler) 715 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context); 716 } else if (cq_event) { 717 if (cq->ibcq.event_handler) 718 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context); 719 } else if (srq_event) { 720 if (qp->srq->ibsrq.event_handler) 721 qp->srq->ibsrq.event_handler(&ib_evt, 722 qp->srq->ibsrq. 723 srq_context); 724 } else if (dev_event) { 725 ib_dispatch_event(&ib_evt); 726 } 727 728} 729 730static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe) 731{ 732 /* async CQE processing */ 733 struct ocrdma_ae_mcqe *cqe = ae_cqe; 734 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >> 735 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT; 736 737 if (evt_code == OCRDMA_ASYNC_EVE_CODE) 738 ocrdma_dispatch_ibevent(dev, cqe); 739 else 740 pr_err("%s(%d) invalid evt code=0x%x\n", __func__, 741 dev->id, evt_code); 742} 743 744static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe) 745{ 746 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) { 747 dev->mqe_ctx.cqe_status = (cqe->status & 748 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT; 749 dev->mqe_ctx.ext_status = 750 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK) 751 >> OCRDMA_MCQE_ESTATUS_SHIFT; 752 dev->mqe_ctx.cmd_done = true; 753 wake_up(&dev->mqe_ctx.cmd_wait); 754 } else 755 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n", 756 __func__, cqe->tag_lo, dev->mqe_ctx.tag); 757} 758 759static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id) 760{ 761 u16 cqe_popped = 0; 762 struct ocrdma_mcqe *cqe; 763 764 while (1) { 765 cqe = ocrdma_get_mcqe(dev); 766 if (cqe == NULL) 767 break; 768 ocrdma_le32_to_cpu(cqe, sizeof(*cqe)); 769 cqe_popped += 1; 770 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK) 771 ocrdma_process_acqe(dev, cqe); 772 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK) 773 ocrdma_process_mcqe(dev, cqe); 774 else 775 pr_err("%s() cqe->compl is not set.\n", __func__); 776 memset(cqe, 0, sizeof(struct ocrdma_mcqe)); 777 ocrdma_mcq_inc_tail(dev); 778 } 779 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped); 780 return 0; 781} 782 783static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev, 784 struct ocrdma_cq *cq) 785{ 786 unsigned long flags; 787 struct ocrdma_qp *qp; 788 bool buddy_cq_found = false; 789 /* Go through list of QPs in error state which are using this CQ 790 * and invoke its callback handler to trigger CQE processing for 791 * error/flushed CQE. It is rare to find more than few entries in 792 * this list as most consumers stops after getting error CQE. 793 * List is traversed only once when a matching buddy cq found for a QP. 794 */ 795 spin_lock_irqsave(&dev->flush_q_lock, flags); 796 list_for_each_entry(qp, &cq->sq_head, sq_entry) { 797 if (qp->srq) 798 continue; 799 /* if wq and rq share the same cq, than comp_handler 800 * is already invoked. 801 */ 802 if (qp->sq_cq == qp->rq_cq) 803 continue; 804 /* if completion came on sq, rq's cq is buddy cq. 805 * if completion came on rq, sq's cq is buddy cq. 806 */ 807 if (qp->sq_cq == cq) 808 cq = qp->rq_cq; 809 else 810 cq = qp->sq_cq; 811 buddy_cq_found = true; 812 break; 813 } 814 spin_unlock_irqrestore(&dev->flush_q_lock, flags); 815 if (buddy_cq_found == false) 816 return; 817 if (cq->ibcq.comp_handler) { 818 spin_lock_irqsave(&cq->comp_handler_lock, flags); 819 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context); 820 spin_unlock_irqrestore(&cq->comp_handler_lock, flags); 821 } 822} 823 824static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx) 825{ 826 unsigned long flags; 827 struct ocrdma_cq *cq; 828 829 if (cq_idx >= OCRDMA_MAX_CQ) 830 BUG(); 831 832 cq = dev->cq_tbl[cq_idx]; 833 if (cq == NULL) { 834 pr_err("%s%d invalid id=0x%x\n", __func__, dev->id, cq_idx); 835 return; 836 } 837 spin_lock_irqsave(&cq->cq_lock, flags); 838 cq->armed = false; 839 cq->solicited = false; 840 spin_unlock_irqrestore(&cq->cq_lock, flags); 841 842 ocrdma_ring_cq_db(dev, cq->id, false, false, 0); 843 844 if (cq->ibcq.comp_handler) { 845 spin_lock_irqsave(&cq->comp_handler_lock, flags); 846 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context); 847 spin_unlock_irqrestore(&cq->comp_handler_lock, flags); 848 } 849 ocrdma_qp_buddy_cq_handler(dev, cq); 850} 851 852static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id) 853{ 854 /* process the MQ-CQE. */ 855 if (cq_id == dev->mq.cq.id) 856 ocrdma_mq_cq_handler(dev, cq_id); 857 else 858 ocrdma_qp_cq_handler(dev, cq_id); 859} 860 861static irqreturn_t ocrdma_irq_handler(int irq, void *handle) 862{ 863 struct ocrdma_eq *eq = handle; 864 struct ocrdma_dev *dev = eq->dev; 865 struct ocrdma_eqe eqe; 866 struct ocrdma_eqe *ptr; 867 u16 eqe_popped = 0; 868 u16 cq_id; 869 while (1) { 870 ptr = ocrdma_get_eqe(eq); 871 eqe = *ptr; 872 ocrdma_le32_to_cpu(&eqe, sizeof(eqe)); 873 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0) 874 break; 875 eqe_popped += 1; 876 ptr->id_valid = 0; 877 /* check whether its CQE or not. */ 878 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) { 879 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT; 880 ocrdma_cq_handler(dev, cq_id); 881 } 882 ocrdma_eq_inc_tail(eq); 883 } 884 ocrdma_ring_eq_db(dev, eq->q.id, true, true, eqe_popped); 885 /* Ring EQ doorbell with num_popped to 0 to enable interrupts again. */ 886 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) 887 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0); 888 return IRQ_HANDLED; 889} 890 891static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd) 892{ 893 struct ocrdma_mqe *mqe; 894 895 dev->mqe_ctx.tag = dev->mq.sq.head; 896 dev->mqe_ctx.cmd_done = false; 897 mqe = ocrdma_get_mqe(dev); 898 cmd->hdr.tag_lo = dev->mq.sq.head; 899 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe)); 900 /* make sure descriptor is written before ringing doorbell */ 901 wmb(); 902 ocrdma_mq_inc_head(dev); 903 ocrdma_ring_mq_db(dev); 904} 905 906static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev) 907{ 908 long status; 909 /* 30 sec timeout */ 910 status = wait_event_timeout(dev->mqe_ctx.cmd_wait, 911 (dev->mqe_ctx.cmd_done != false), 912 msecs_to_jiffies(30000)); 913 if (status) 914 return 0; 915 else 916 return -1; 917} 918 919/* issue a mailbox command on the MQ */ 920static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe) 921{ 922 int status = 0; 923 u16 cqe_status, ext_status; 924 struct ocrdma_mqe *rsp; 925 926 mutex_lock(&dev->mqe_ctx.lock); 927 ocrdma_post_mqe(dev, mqe); 928 status = ocrdma_wait_mqe_cmpl(dev); 929 if (status) 930 goto mbx_err; 931 cqe_status = dev->mqe_ctx.cqe_status; 932 ext_status = dev->mqe_ctx.ext_status; 933 rsp = ocrdma_get_mqe_rsp(dev); 934 ocrdma_copy_le32_to_cpu(mqe, rsp, (sizeof(*mqe))); 935 if (cqe_status || ext_status) { 936 pr_err("%s() opcode=0x%x, cqe_status=0x%x, ext_status=0x%x\n", 937 __func__, 938 (rsp->u.rsp.subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >> 939 OCRDMA_MBX_RSP_OPCODE_SHIFT, cqe_status, ext_status); 940 status = ocrdma_get_mbx_cqe_errno(cqe_status); 941 goto mbx_err; 942 } 943 if (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK) 944 status = ocrdma_get_mbx_errno(mqe->u.rsp.status); 945mbx_err: 946 mutex_unlock(&dev->mqe_ctx.lock); 947 return status; 948} 949 950static void ocrdma_get_attr(struct ocrdma_dev *dev, 951 struct ocrdma_dev_attr *attr, 952 struct ocrdma_mbx_query_config *rsp) 953{ 954 attr->max_pd = 955 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >> 956 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT; 957 attr->max_qp = 958 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >> 959 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT; 960 attr->max_send_sge = ((rsp->max_write_send_sge & 961 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >> 962 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT); 963 attr->max_recv_sge = (rsp->max_write_send_sge & 964 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >> 965 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT; 966 attr->max_srq_sge = (rsp->max_srq_rqe_sge & 967 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >> 968 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET; 969 attr->max_rdma_sge = (rsp->max_write_send_sge & 970 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >> 971 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT; 972 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp & 973 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >> 974 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT; 975 attr->max_srq = 976 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >> 977 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET; 978 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp & 979 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >> 980 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT; 981 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord & 982 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >> 983 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT; 984 attr->srq_supported = (rsp->qp_srq_cq_ird_ord & 985 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >> 986 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT; 987 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay & 988 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >> 989 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT; 990 attr->max_mr = rsp->max_mr; 991 attr->max_mr_size = ~0ull; 992 attr->max_fmr = 0; 993 attr->max_pages_per_frmr = rsp->max_pages_per_frmr; 994 attr->max_num_mr_pbl = rsp->max_num_mr_pbl; 995 attr->max_cqe = rsp->max_cq_cqes_per_cq & 996 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK; 997 attr->max_cq = (rsp->max_cq_cqes_per_cq & 998 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >> 999 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET; 1000 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs & 1001 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >> 1002 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) * 1003 OCRDMA_WQE_STRIDE; 1004 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs & 1005 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >> 1006 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) * 1007 OCRDMA_WQE_STRIDE; 1008 attr->max_inline_data = 1009 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) + 1010 sizeof(struct ocrdma_sge)); 1011 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) { 1012 attr->ird = 1; 1013 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE; 1014 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES; 1015 } 1016 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >> 1017 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET; 1018 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q & 1019 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK; 1020} 1021 1022static int ocrdma_check_fw_config(struct ocrdma_dev *dev, 1023 struct ocrdma_fw_conf_rsp *conf) 1024{ 1025 u32 fn_mode; 1026 1027 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA; 1028 if (fn_mode != OCRDMA_FN_MODE_RDMA) 1029 return -EINVAL; 1030 dev->base_eqid = conf->base_eqid; 1031 dev->max_eq = conf->max_eq; 1032 return 0; 1033} 1034 1035/* can be issued only during init time. */ 1036static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev) 1037{ 1038 int status = -ENOMEM; 1039 struct ocrdma_mqe *cmd; 1040 struct ocrdma_fw_ver_rsp *rsp; 1041 1042 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd)); 1043 if (!cmd) 1044 return -ENOMEM; 1045 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0], 1046 OCRDMA_CMD_GET_FW_VER, 1047 OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); 1048 1049 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1050 if (status) 1051 goto mbx_err; 1052 rsp = (struct ocrdma_fw_ver_rsp *)cmd; 1053 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver)); 1054 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0], 1055 sizeof(rsp->running_ver)); 1056 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver)); 1057mbx_err: 1058 kfree(cmd); 1059 return status; 1060} 1061 1062/* can be issued only during init time. */ 1063static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev) 1064{ 1065 int status = -ENOMEM; 1066 struct ocrdma_mqe *cmd; 1067 struct ocrdma_fw_conf_rsp *rsp; 1068 1069 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd)); 1070 if (!cmd) 1071 return -ENOMEM; 1072 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0], 1073 OCRDMA_CMD_GET_FW_CONFIG, 1074 OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); 1075 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1076 if (status) 1077 goto mbx_err; 1078 rsp = (struct ocrdma_fw_conf_rsp *)cmd; 1079 status = ocrdma_check_fw_config(dev, rsp); 1080mbx_err: 1081 kfree(cmd); 1082 return status; 1083} 1084 1085static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev) 1086{ 1087 int status = -ENOMEM; 1088 struct ocrdma_mbx_query_config *rsp; 1089 struct ocrdma_mqe *cmd; 1090 1091 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd)); 1092 if (!cmd) 1093 return status; 1094 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1095 if (status) 1096 goto mbx_err; 1097 rsp = (struct ocrdma_mbx_query_config *)cmd; 1098 ocrdma_get_attr(dev, &dev->attr, rsp); 1099mbx_err: 1100 kfree(cmd); 1101 return status; 1102} 1103 1104int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed) 1105{ 1106 int status = -ENOMEM; 1107 struct ocrdma_get_link_speed_rsp *rsp; 1108 struct ocrdma_mqe *cmd; 1109 1110 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1, 1111 sizeof(*cmd)); 1112 if (!cmd) 1113 return status; 1114 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0], 1115 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1, 1116 OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); 1117 1118 ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1; 1119 1120 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1121 if (status) 1122 goto mbx_err; 1123 1124 rsp = (struct ocrdma_get_link_speed_rsp *)cmd; 1125 *lnk_speed = rsp->phys_port_speed; 1126 1127mbx_err: 1128 kfree(cmd); 1129 return status; 1130} 1131 1132int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd) 1133{ 1134 int status = -ENOMEM; 1135 struct ocrdma_alloc_pd *cmd; 1136 struct ocrdma_alloc_pd_rsp *rsp; 1137 1138 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd)); 1139 if (!cmd) 1140 return status; 1141 if (pd->dpp_enabled) 1142 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP; 1143 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1144 if (status) 1145 goto mbx_err; 1146 rsp = (struct ocrdma_alloc_pd_rsp *)cmd; 1147 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK; 1148 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) { 1149 pd->dpp_enabled = true; 1150 pd->dpp_page = rsp->dpp_page_pdid >> 1151 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT; 1152 } else { 1153 pd->dpp_enabled = false; 1154 pd->num_dpp_qp = 0; 1155 } 1156mbx_err: 1157 kfree(cmd); 1158 return status; 1159} 1160 1161int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd) 1162{ 1163 int status = -ENOMEM; 1164 struct ocrdma_dealloc_pd *cmd; 1165 1166 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd)); 1167 if (!cmd) 1168 return status; 1169 cmd->id = pd->id; 1170 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1171 kfree(cmd); 1172 return status; 1173} 1174 1175static int ocrdma_build_q_conf(u32 *num_entries, int entry_size, 1176 int *num_pages, int *page_size) 1177{ 1178 int i; 1179 int mem_size; 1180 1181 *num_entries = roundup_pow_of_two(*num_entries); 1182 mem_size = *num_entries * entry_size; 1183 /* find the possible lowest possible multiplier */ 1184 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) { 1185 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i)) 1186 break; 1187 } 1188 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT) 1189 return -EINVAL; 1190 mem_size = roundup(mem_size, 1191 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES)); 1192 *num_pages = 1193 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES); 1194 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES); 1195 *num_entries = mem_size / entry_size; 1196 return 0; 1197} 1198 1199static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev) 1200{ 1201 int i ; 1202 int status = 0; 1203 int max_ah; 1204 struct ocrdma_create_ah_tbl *cmd; 1205 struct ocrdma_create_ah_tbl_rsp *rsp; 1206 struct pci_dev *pdev = dev->nic_info.pdev; 1207 dma_addr_t pa; 1208 struct ocrdma_pbe *pbes; 1209 1210 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd)); 1211 if (!cmd) 1212 return status; 1213 1214 max_ah = OCRDMA_MAX_AH; 1215 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah; 1216 1217 /* number of PBEs in PBL */ 1218 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES << 1219 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) & 1220 OCRDMA_CREATE_AH_NUM_PAGES_MASK; 1221 1222 /* page size */ 1223 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) { 1224 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i)) 1225 break; 1226 } 1227 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) & 1228 OCRDMA_CREATE_AH_PAGE_SIZE_MASK; 1229 1230 /* ah_entry size */ 1231 cmd->ah_conf |= (sizeof(struct ocrdma_av) << 1232 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) & 1233 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK; 1234 1235 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 1236 &dev->av_tbl.pbl.pa, 1237 GFP_KERNEL); 1238 if (dev->av_tbl.pbl.va == NULL) 1239 goto mem_err; 1240 1241 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size, 1242 &pa, GFP_KERNEL); 1243 if (dev->av_tbl.va == NULL) 1244 goto mem_err_ah; 1245 dev->av_tbl.pa = pa; 1246 dev->av_tbl.num_ah = max_ah; 1247 memset(dev->av_tbl.va, 0, dev->av_tbl.size); 1248 1249 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va; 1250 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) { 1251 pbes[i].pa_lo = (u32) (pa & 0xffffffff); 1252 pbes[i].pa_hi = (u32) upper_32_bits(pa); 1253 pa += PAGE_SIZE; 1254 } 1255 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF); 1256 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa); 1257 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1258 if (status) 1259 goto mbx_err; 1260 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd; 1261 dev->av_tbl.ahid = rsp->ahid & 0xFFFF; 1262 kfree(cmd); 1263 return 0; 1264 1265mbx_err: 1266 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va, 1267 dev->av_tbl.pa); 1268 dev->av_tbl.va = NULL; 1269mem_err_ah: 1270 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va, 1271 dev->av_tbl.pbl.pa); 1272 dev->av_tbl.pbl.va = NULL; 1273 dev->av_tbl.size = 0; 1274mem_err: 1275 kfree(cmd); 1276 return status; 1277} 1278 1279static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev) 1280{ 1281 struct ocrdma_delete_ah_tbl *cmd; 1282 struct pci_dev *pdev = dev->nic_info.pdev; 1283 1284 if (dev->av_tbl.va == NULL) 1285 return; 1286 1287 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd)); 1288 if (!cmd) 1289 return; 1290 cmd->ahid = dev->av_tbl.ahid; 1291 1292 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1293 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va, 1294 dev->av_tbl.pa); 1295 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va, 1296 dev->av_tbl.pbl.pa); 1297 kfree(cmd); 1298} 1299 1300/* Multiple CQs uses the EQ. This routine returns least used 1301 * EQ to associate with CQ. This will distributes the interrupt 1302 * processing and CPU load to associated EQ, vector and so to that CPU. 1303 */ 1304static u16 ocrdma_bind_eq(struct ocrdma_dev *dev) 1305{ 1306 int i, selected_eq = 0, cq_cnt = 0; 1307 u16 eq_id; 1308 1309 mutex_lock(&dev->dev_lock); 1310 cq_cnt = dev->eq_tbl[0].cq_cnt; 1311 eq_id = dev->eq_tbl[0].q.id; 1312 /* find the EQ which is has the least number of 1313 * CQs associated with it. 1314 */ 1315 for (i = 0; i < dev->eq_cnt; i++) { 1316 if (dev->eq_tbl[i].cq_cnt < cq_cnt) { 1317 cq_cnt = dev->eq_tbl[i].cq_cnt; 1318 eq_id = dev->eq_tbl[i].q.id; 1319 selected_eq = i; 1320 } 1321 } 1322 dev->eq_tbl[selected_eq].cq_cnt += 1; 1323 mutex_unlock(&dev->dev_lock); 1324 return eq_id; 1325} 1326 1327static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id) 1328{ 1329 int i; 1330 1331 mutex_lock(&dev->dev_lock); 1332 for (i = 0; i < dev->eq_cnt; i++) { 1333 if (dev->eq_tbl[i].q.id != eq_id) 1334 continue; 1335 dev->eq_tbl[i].cq_cnt -= 1; 1336 break; 1337 } 1338 mutex_unlock(&dev->dev_lock); 1339} 1340 1341int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq, 1342 int entries, int dpp_cq, u16 pd_id) 1343{ 1344 int status = -ENOMEM; int max_hw_cqe; 1345 struct pci_dev *pdev = dev->nic_info.pdev; 1346 struct ocrdma_create_cq *cmd; 1347 struct ocrdma_create_cq_rsp *rsp; 1348 u32 hw_pages, cqe_size, page_size, cqe_count; 1349 1350 if (entries > dev->attr.max_cqe) { 1351 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n", 1352 __func__, dev->id, dev->attr.max_cqe, entries); 1353 return -EINVAL; 1354 } 1355 if (dpp_cq && (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY)) 1356 return -EINVAL; 1357 1358 if (dpp_cq) { 1359 cq->max_hw_cqe = 1; 1360 max_hw_cqe = 1; 1361 cqe_size = OCRDMA_DPP_CQE_SIZE; 1362 hw_pages = 1; 1363 } else { 1364 cq->max_hw_cqe = dev->attr.max_cqe; 1365 max_hw_cqe = dev->attr.max_cqe; 1366 cqe_size = sizeof(struct ocrdma_cqe); 1367 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES; 1368 } 1369 1370 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE); 1371 1372 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd)); 1373 if (!cmd) 1374 return -ENOMEM; 1375 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ, 1376 OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); 1377 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL); 1378 if (!cq->va) { 1379 status = -ENOMEM; 1380 goto mem_err; 1381 } 1382 memset(cq->va, 0, cq->len); 1383 page_size = cq->len / hw_pages; 1384 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) << 1385 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT; 1386 cmd->cmd.pgsz_pgcnt |= hw_pages; 1387 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS; 1388 1389 cq->eqn = ocrdma_bind_eq(dev); 1390 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3; 1391 cqe_count = cq->len / cqe_size; 1392 if (cqe_count > 1024) { 1393 /* Set cnt to 3 to indicate more than 1024 cq entries */ 1394 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT); 1395 } else { 1396 u8 count = 0; 1397 switch (cqe_count) { 1398 case 256: 1399 count = 0; 1400 break; 1401 case 512: 1402 count = 1; 1403 break; 1404 case 1024: 1405 count = 2; 1406 break; 1407 default: 1408 goto mbx_err; 1409 } 1410 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT); 1411 } 1412 /* shared eq between all the consumer cqs. */ 1413 cmd->cmd.eqn = cq->eqn; 1414 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) { 1415 if (dpp_cq) 1416 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP << 1417 OCRDMA_CREATE_CQ_TYPE_SHIFT; 1418 cq->phase_change = false; 1419 cmd->cmd.cqe_count = (cq->len / cqe_size); 1420 } else { 1421 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1; 1422 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID; 1423 cq->phase_change = true; 1424 } 1425 1426 cmd->cmd.pd_id = pd_id; /* valid only for v3 */ 1427 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size); 1428 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1429 if (status) 1430 goto mbx_err; 1431 1432 rsp = (struct ocrdma_create_cq_rsp *)cmd; 1433 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK); 1434 kfree(cmd); 1435 return 0; 1436mbx_err: 1437 ocrdma_unbind_eq(dev, cq->eqn); 1438 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa); 1439mem_err: 1440 kfree(cmd); 1441 return status; 1442} 1443 1444int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq) 1445{ 1446 int status = -ENOMEM; 1447 struct ocrdma_destroy_cq *cmd; 1448 1449 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd)); 1450 if (!cmd) 1451 return status; 1452 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ, 1453 OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); 1454 1455 cmd->bypass_flush_qid |= 1456 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) & 1457 OCRDMA_DESTROY_CQ_QID_MASK; 1458 1459 ocrdma_unbind_eq(dev, cq->eqn); 1460 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1461 if (status) 1462 goto mbx_err; 1463 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa); 1464mbx_err: 1465 kfree(cmd); 1466 return status; 1467} 1468 1469int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr, 1470 u32 pdid, int addr_check) 1471{ 1472 int status = -ENOMEM; 1473 struct ocrdma_alloc_lkey *cmd; 1474 struct ocrdma_alloc_lkey_rsp *rsp; 1475 1476 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd)); 1477 if (!cmd) 1478 return status; 1479 cmd->pdid = pdid; 1480 cmd->pbl_sz_flags |= addr_check; 1481 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT); 1482 cmd->pbl_sz_flags |= 1483 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT); 1484 cmd->pbl_sz_flags |= 1485 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT); 1486 cmd->pbl_sz_flags |= 1487 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT); 1488 cmd->pbl_sz_flags |= 1489 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT); 1490 cmd->pbl_sz_flags |= 1491 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT); 1492 1493 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1494 if (status) 1495 goto mbx_err; 1496 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd; 1497 hwmr->lkey = rsp->lrkey; 1498mbx_err: 1499 kfree(cmd); 1500 return status; 1501} 1502 1503int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey) 1504{ 1505 int status = -ENOMEM; 1506 struct ocrdma_dealloc_lkey *cmd; 1507 1508 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd)); 1509 if (!cmd) 1510 return -ENOMEM; 1511 cmd->lkey = lkey; 1512 cmd->rsvd_frmr = fr_mr ? 1 : 0; 1513 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1514 if (status) 1515 goto mbx_err; 1516mbx_err: 1517 kfree(cmd); 1518 return status; 1519} 1520 1521static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr, 1522 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last) 1523{ 1524 int status = -ENOMEM; 1525 int i; 1526 struct ocrdma_reg_nsmr *cmd; 1527 struct ocrdma_reg_nsmr_rsp *rsp; 1528 1529 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd)); 1530 if (!cmd) 1531 return -ENOMEM; 1532 cmd->num_pbl_pdid = 1533 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT); 1534 cmd->fr_mr = hwmr->fr_mr; 1535 1536 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr << 1537 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT); 1538 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd << 1539 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT); 1540 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr << 1541 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT); 1542 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic << 1543 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT); 1544 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind << 1545 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT); 1546 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT); 1547 1548 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE); 1549 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) << 1550 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT; 1551 cmd->totlen_low = hwmr->len; 1552 cmd->totlen_high = upper_32_bits(hwmr->len); 1553 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff); 1554 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo); 1555 cmd->va_loaddr = (u32) hwmr->va; 1556 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va); 1557 1558 for (i = 0; i < pbl_cnt; i++) { 1559 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff); 1560 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa); 1561 } 1562 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1563 if (status) 1564 goto mbx_err; 1565 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd; 1566 hwmr->lkey = rsp->lrkey; 1567mbx_err: 1568 kfree(cmd); 1569 return status; 1570} 1571 1572static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev, 1573 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt, 1574 u32 pbl_offset, u32 last) 1575{ 1576 int status = -ENOMEM; 1577 int i; 1578 struct ocrdma_reg_nsmr_cont *cmd; 1579 1580 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd)); 1581 if (!cmd) 1582 return -ENOMEM; 1583 cmd->lrkey = hwmr->lkey; 1584 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) | 1585 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK); 1586 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT; 1587 1588 for (i = 0; i < pbl_cnt; i++) { 1589 cmd->pbl[i].lo = 1590 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff); 1591 cmd->pbl[i].hi = 1592 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa); 1593 } 1594 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1595 if (status) 1596 goto mbx_err; 1597mbx_err: 1598 kfree(cmd); 1599 return status; 1600} 1601 1602int ocrdma_reg_mr(struct ocrdma_dev *dev, 1603 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc) 1604{ 1605 int status; 1606 u32 last = 0; 1607 u32 cur_pbl_cnt, pbl_offset; 1608 u32 pending_pbl_cnt = hwmr->num_pbls; 1609 1610 pbl_offset = 0; 1611 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL); 1612 if (cur_pbl_cnt == pending_pbl_cnt) 1613 last = 1; 1614 1615 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid, 1616 cur_pbl_cnt, hwmr->pbe_size, last); 1617 if (status) { 1618 pr_err("%s() status=%d\n", __func__, status); 1619 return status; 1620 } 1621 /* if there is no more pbls to register then exit. */ 1622 if (last) 1623 return 0; 1624 1625 while (!last) { 1626 pbl_offset += cur_pbl_cnt; 1627 pending_pbl_cnt -= cur_pbl_cnt; 1628 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL); 1629 /* if we reach the end of the pbls, then need to set the last 1630 * bit, indicating no more pbls to register for this memory key. 1631 */ 1632 if (cur_pbl_cnt == pending_pbl_cnt) 1633 last = 1; 1634 1635 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt, 1636 pbl_offset, last); 1637 if (status) 1638 break; 1639 } 1640 if (status) 1641 pr_err("%s() err. status=%d\n", __func__, status); 1642 1643 return status; 1644} 1645 1646bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp) 1647{ 1648 struct ocrdma_qp *tmp; 1649 bool found = false; 1650 list_for_each_entry(tmp, &cq->sq_head, sq_entry) { 1651 if (qp == tmp) { 1652 found = true; 1653 break; 1654 } 1655 } 1656 return found; 1657} 1658 1659bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp) 1660{ 1661 struct ocrdma_qp *tmp; 1662 bool found = false; 1663 list_for_each_entry(tmp, &cq->rq_head, rq_entry) { 1664 if (qp == tmp) { 1665 found = true; 1666 break; 1667 } 1668 } 1669 return found; 1670} 1671 1672void ocrdma_flush_qp(struct ocrdma_qp *qp) 1673{ 1674 bool found; 1675 unsigned long flags; 1676 1677 spin_lock_irqsave(&qp->dev->flush_q_lock, flags); 1678 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp); 1679 if (!found) 1680 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head); 1681 if (!qp->srq) { 1682 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp); 1683 if (!found) 1684 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head); 1685 } 1686 spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags); 1687} 1688 1689static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp) 1690{ 1691 qp->sq.head = 0; 1692 qp->sq.tail = 0; 1693 qp->rq.head = 0; 1694 qp->rq.tail = 0; 1695} 1696 1697int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state, 1698 enum ib_qp_state *old_ib_state) 1699{ 1700 unsigned long flags; 1701 int status = 0; 1702 enum ocrdma_qp_state new_state; 1703 new_state = get_ocrdma_qp_state(new_ib_state); 1704 1705 /* sync with wqe and rqe posting */ 1706 spin_lock_irqsave(&qp->q_lock, flags); 1707 1708 if (old_ib_state) 1709 *old_ib_state = get_ibqp_state(qp->state); 1710 if (new_state == qp->state) { 1711 spin_unlock_irqrestore(&qp->q_lock, flags); 1712 return 1; 1713 } 1714 1715 1716 if (new_state == OCRDMA_QPS_INIT) { 1717 ocrdma_init_hwq_ptr(qp); 1718 ocrdma_del_flush_qp(qp); 1719 } else if (new_state == OCRDMA_QPS_ERR) { 1720 ocrdma_flush_qp(qp); 1721 } 1722 1723 qp->state = new_state; 1724 1725 spin_unlock_irqrestore(&qp->q_lock, flags); 1726 return status; 1727} 1728 1729static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp) 1730{ 1731 u32 flags = 0; 1732 if (qp->cap_flags & OCRDMA_QP_INB_RD) 1733 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK; 1734 if (qp->cap_flags & OCRDMA_QP_INB_WR) 1735 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK; 1736 if (qp->cap_flags & OCRDMA_QP_MW_BIND) 1737 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK; 1738 if (qp->cap_flags & OCRDMA_QP_LKEY0) 1739 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK; 1740 if (qp->cap_flags & OCRDMA_QP_FAST_REG) 1741 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK; 1742 return flags; 1743} 1744 1745static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd, 1746 struct ib_qp_init_attr *attrs, 1747 struct ocrdma_qp *qp) 1748{ 1749 int status; 1750 u32 len, hw_pages, hw_page_size; 1751 dma_addr_t pa; 1752 struct ocrdma_dev *dev = qp->dev; 1753 struct pci_dev *pdev = dev->nic_info.pdev; 1754 u32 max_wqe_allocated; 1755 u32 max_sges = attrs->cap.max_send_sge; 1756 1757 /* QP1 may exceed 127 */ 1758 max_wqe_allocated = min_t(int, attrs->cap.max_send_wr + 1, 1759 dev->attr.max_wqe); 1760 1761 status = ocrdma_build_q_conf(&max_wqe_allocated, 1762 dev->attr.wqe_size, &hw_pages, &hw_page_size); 1763 if (status) { 1764 pr_err("%s() req. max_send_wr=0x%x\n", __func__, 1765 max_wqe_allocated); 1766 return -EINVAL; 1767 } 1768 qp->sq.max_cnt = max_wqe_allocated; 1769 len = (hw_pages * hw_page_size); 1770 1771 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL); 1772 if (!qp->sq.va) 1773 return -EINVAL; 1774 memset(qp->sq.va, 0, len); 1775 qp->sq.len = len; 1776 qp->sq.pa = pa; 1777 qp->sq.entry_size = dev->attr.wqe_size; 1778 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size); 1779 1780 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) 1781 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT); 1782 cmd->num_wq_rq_pages |= (hw_pages << 1783 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) & 1784 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK; 1785 cmd->max_sge_send_write |= (max_sges << 1786 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) & 1787 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK; 1788 cmd->max_sge_send_write |= (max_sges << 1789 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) & 1790 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK; 1791 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) << 1792 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) & 1793 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK; 1794 cmd->wqe_rqe_size |= (dev->attr.wqe_size << 1795 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) & 1796 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK; 1797 return 0; 1798} 1799 1800static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd, 1801 struct ib_qp_init_attr *attrs, 1802 struct ocrdma_qp *qp) 1803{ 1804 int status; 1805 u32 len, hw_pages, hw_page_size; 1806 dma_addr_t pa = 0; 1807 struct ocrdma_dev *dev = qp->dev; 1808 struct pci_dev *pdev = dev->nic_info.pdev; 1809 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1; 1810 1811 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size, 1812 &hw_pages, &hw_page_size); 1813 if (status) { 1814 pr_err("%s() req. max_recv_wr=0x%x\n", __func__, 1815 attrs->cap.max_recv_wr + 1); 1816 return status; 1817 } 1818 qp->rq.max_cnt = max_rqe_allocated; 1819 len = (hw_pages * hw_page_size); 1820 1821 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL); 1822 if (!qp->rq.va) 1823 return -ENOMEM; 1824 memset(qp->rq.va, 0, len); 1825 qp->rq.pa = pa; 1826 qp->rq.len = len; 1827 qp->rq.entry_size = dev->attr.rqe_size; 1828 1829 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size); 1830 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) << 1831 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT); 1832 cmd->num_wq_rq_pages |= 1833 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) & 1834 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK; 1835 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge << 1836 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) & 1837 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK; 1838 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) << 1839 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) & 1840 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK; 1841 cmd->wqe_rqe_size |= (dev->attr.rqe_size << 1842 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) & 1843 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK; 1844 return 0; 1845} 1846 1847static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd, 1848 struct ocrdma_pd *pd, 1849 struct ocrdma_qp *qp, 1850 u8 enable_dpp_cq, u16 dpp_cq_id) 1851{ 1852 pd->num_dpp_qp--; 1853 qp->dpp_enabled = true; 1854 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK; 1855 if (!enable_dpp_cq) 1856 return; 1857 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK; 1858 cmd->dpp_credits_cqid = dpp_cq_id; 1859 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT << 1860 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT; 1861} 1862 1863static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd, 1864 struct ocrdma_qp *qp) 1865{ 1866 struct ocrdma_dev *dev = qp->dev; 1867 struct pci_dev *pdev = dev->nic_info.pdev; 1868 dma_addr_t pa = 0; 1869 int ird_page_size = dev->attr.ird_page_size; 1870 int ird_q_len = dev->attr.num_ird_pages * ird_page_size; 1871 struct ocrdma_hdr_wqe *rqe; 1872 int i = 0; 1873 1874 if (dev->attr.ird == 0) 1875 return 0; 1876 1877 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len, 1878 &pa, GFP_KERNEL); 1879 if (!qp->ird_q_va) 1880 return -ENOMEM; 1881 memset(qp->ird_q_va, 0, ird_q_len); 1882 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages, 1883 pa, ird_page_size); 1884 for (; i < ird_q_len / dev->attr.rqe_size; i++) { 1885 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va + 1886 (i * dev->attr.rqe_size)); 1887 rqe->cw = 0; 1888 rqe->cw |= 2; 1889 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT); 1890 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT); 1891 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT); 1892 } 1893 return 0; 1894} 1895 1896static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp, 1897 struct ocrdma_qp *qp, 1898 struct ib_qp_init_attr *attrs, 1899 u16 *dpp_offset, u16 *dpp_credit_lmt) 1900{ 1901 u32 max_wqe_allocated, max_rqe_allocated; 1902 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK; 1903 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK; 1904 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT; 1905 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK; 1906 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT); 1907 qp->dpp_enabled = false; 1908 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) { 1909 qp->dpp_enabled = true; 1910 *dpp_credit_lmt = (rsp->dpp_response & 1911 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >> 1912 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT; 1913 *dpp_offset = (rsp->dpp_response & 1914 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >> 1915 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT; 1916 } 1917 max_wqe_allocated = 1918 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT; 1919 max_wqe_allocated = 1 << max_wqe_allocated; 1920 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe); 1921 1922 qp->sq.max_cnt = max_wqe_allocated; 1923 qp->sq.max_wqe_idx = max_wqe_allocated - 1; 1924 1925 if (!attrs->srq) { 1926 qp->rq.max_cnt = max_rqe_allocated; 1927 qp->rq.max_wqe_idx = max_rqe_allocated - 1; 1928 } 1929} 1930 1931int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs, 1932 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset, 1933 u16 *dpp_credit_lmt) 1934{ 1935 int status = -ENOMEM; 1936 u32 flags = 0; 1937 struct ocrdma_dev *dev = qp->dev; 1938 struct ocrdma_pd *pd = qp->pd; 1939 struct pci_dev *pdev = dev->nic_info.pdev; 1940 struct ocrdma_cq *cq; 1941 struct ocrdma_create_qp_req *cmd; 1942 struct ocrdma_create_qp_rsp *rsp; 1943 int qptype; 1944 1945 switch (attrs->qp_type) { 1946 case IB_QPT_GSI: 1947 qptype = OCRDMA_QPT_GSI; 1948 break; 1949 case IB_QPT_RC: 1950 qptype = OCRDMA_QPT_RC; 1951 break; 1952 case IB_QPT_UD: 1953 qptype = OCRDMA_QPT_UD; 1954 break; 1955 default: 1956 return -EINVAL; 1957 }; 1958 1959 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd)); 1960 if (!cmd) 1961 return status; 1962 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) & 1963 OCRDMA_CREATE_QP_REQ_QPT_MASK; 1964 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp); 1965 if (status) 1966 goto sq_err; 1967 1968 if (attrs->srq) { 1969 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq); 1970 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK; 1971 cmd->rq_addr[0].lo = srq->id; 1972 qp->srq = srq; 1973 } else { 1974 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp); 1975 if (status) 1976 goto rq_err; 1977 } 1978 1979 status = ocrdma_set_create_qp_ird_cmd(cmd, qp); 1980 if (status) 1981 goto mbx_err; 1982 1983 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) & 1984 OCRDMA_CREATE_QP_REQ_PD_ID_MASK; 1985 1986 flags = ocrdma_set_create_qp_mbx_access_flags(qp); 1987 1988 cmd->max_sge_recv_flags |= flags; 1989 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp << 1990 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) & 1991 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK; 1992 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp << 1993 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) & 1994 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK; 1995 cq = get_ocrdma_cq(attrs->send_cq); 1996 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) & 1997 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK; 1998 qp->sq_cq = cq; 1999 cq = get_ocrdma_cq(attrs->recv_cq); 2000 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) & 2001 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK; 2002 qp->rq_cq = cq; 2003 2004 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp && 2005 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) { 2006 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq, 2007 dpp_cq_id); 2008 } 2009 2010 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 2011 if (status) 2012 goto mbx_err; 2013 rsp = (struct ocrdma_create_qp_rsp *)cmd; 2014 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt); 2015 qp->state = OCRDMA_QPS_RST; 2016 kfree(cmd); 2017 return 0; 2018mbx_err: 2019 if (qp->rq.va) 2020 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa); 2021rq_err: 2022 pr_err("%s(%d) rq_err\n", __func__, dev->id); 2023 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa); 2024sq_err: 2025 pr_err("%s(%d) sq_err\n", __func__, dev->id); 2026 kfree(cmd); 2027 return status; 2028} 2029 2030int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp, 2031 struct ocrdma_qp_params *param) 2032{ 2033 int status = -ENOMEM; 2034 struct ocrdma_query_qp *cmd; 2035 struct ocrdma_query_qp_rsp *rsp; 2036 2037 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd)); 2038 if (!cmd) 2039 return status; 2040 cmd->qp_id = qp->id; 2041 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 2042 if (status) 2043 goto mbx_err; 2044 rsp = (struct ocrdma_query_qp_rsp *)cmd; 2045 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params)); 2046mbx_err: 2047 kfree(cmd); 2048 return status; 2049} 2050 2051int ocrdma_resolve_dgid(struct ocrdma_dev *dev, union ib_gid *dgid, 2052 u8 *mac_addr) 2053{ 2054 struct in6_addr in6; 2055 2056 memcpy(&in6, dgid, sizeof in6); 2057 if (rdma_is_multicast_addr(&in6)) { 2058 rdma_get_mcast_mac(&in6, mac_addr); 2059 } else if (rdma_link_local_addr(&in6)) { 2060 rdma_get_ll_mac(&in6, mac_addr); 2061 } else { 2062 pr_err("%s() fail to resolve mac_addr.\n", __func__); 2063 return -EINVAL; 2064 } 2065 return 0; 2066} 2067 2068static int ocrdma_set_av_params(struct ocrdma_qp *qp, 2069 struct ocrdma_modify_qp *cmd, 2070 struct ib_qp_attr *attrs) 2071{ 2072 int status; 2073 struct ib_ah_attr *ah_attr = &attrs->ah_attr; 2074 union ib_gid sgid, zgid; 2075 u32 vlan_id; 2076 u8 mac_addr[6]; 2077 2078 if ((ah_attr->ah_flags & IB_AH_GRH) == 0) 2079 return -EINVAL; 2080 cmd->params.tclass_sq_psn |= 2081 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT); 2082 cmd->params.rnt_rc_sl_fl |= 2083 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK); 2084 cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT); 2085 cmd->params.hop_lmt_rq_psn |= 2086 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT); 2087 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID; 2088 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0], 2089 sizeof(cmd->params.dgid)); 2090 status = ocrdma_query_gid(&qp->dev->ibdev, 1, 2091 ah_attr->grh.sgid_index, &sgid); 2092 if (status) 2093 return status; 2094 2095 memset(&zgid, 0, sizeof(zgid)); 2096 if (!memcmp(&sgid, &zgid, sizeof(zgid))) 2097 return -EINVAL; 2098 2099 qp->sgid_idx = ah_attr->grh.sgid_index; 2100 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid)); 2101 ocrdma_resolve_dgid(qp->dev, &ah_attr->grh.dgid, &mac_addr[0]); 2102 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) | 2103 (mac_addr[2] << 16) | (mac_addr[3] << 24); 2104 /* convert them to LE format. */ 2105 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid)); 2106 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid)); 2107 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8); 2108 vlan_id = rdma_get_vlan_id(&sgid); 2109 if (vlan_id && (vlan_id < 0x1000)) { 2110 cmd->params.vlan_dmac_b4_to_b5 |= 2111 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT; 2112 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID; 2113 } 2114 return 0; 2115} 2116 2117static int ocrdma_set_qp_params(struct ocrdma_qp *qp, 2118 struct ocrdma_modify_qp *cmd, 2119 struct ib_qp_attr *attrs, int attr_mask, 2120 enum ib_qp_state old_qps) 2121{ 2122 int status = 0; 2123 2124 if (attr_mask & IB_QP_PKEY_INDEX) { 2125 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index & 2126 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK); 2127 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID; 2128 } 2129 if (attr_mask & IB_QP_QKEY) { 2130 qp->qkey = attrs->qkey; 2131 cmd->params.qkey = attrs->qkey; 2132 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID; 2133 } 2134 if (attr_mask & IB_QP_AV) { 2135 status = ocrdma_set_av_params(qp, cmd, attrs); 2136 if (status) 2137 return status; 2138 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) { 2139 /* set the default mac address for UD, GSI QPs */ 2140 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] | 2141 (qp->dev->nic_info.mac_addr[1] << 8) | 2142 (qp->dev->nic_info.mac_addr[2] << 16) | 2143 (qp->dev->nic_info.mac_addr[3] << 24); 2144 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] | 2145 (qp->dev->nic_info.mac_addr[5] << 8); 2146 } 2147 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) && 2148 attrs->en_sqd_async_notify) { 2149 cmd->params.max_sge_recv_flags |= 2150 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC; 2151 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID; 2152 } 2153 if (attr_mask & IB_QP_DEST_QPN) { 2154 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num & 2155 OCRDMA_QP_PARAMS_DEST_QPN_MASK); 2156 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID; 2157 } 2158 if (attr_mask & IB_QP_PATH_MTU) { 2159 if (attrs->path_mtu < IB_MTU_256 || 2160 attrs->path_mtu > IB_MTU_4096) { 2161 status = -EINVAL; 2162 goto pmtu_err; 2163 } 2164 cmd->params.path_mtu_pkey_indx |= 2165 (ib_mtu_enum_to_int(attrs->path_mtu) << 2166 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) & 2167 OCRDMA_QP_PARAMS_PATH_MTU_MASK; 2168 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID; 2169 } 2170 if (attr_mask & IB_QP_TIMEOUT) { 2171 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout << 2172 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT; 2173 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID; 2174 } 2175 if (attr_mask & IB_QP_RETRY_CNT) { 2176 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt << 2177 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) & 2178 OCRDMA_QP_PARAMS_RETRY_CNT_MASK; 2179 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID; 2180 } 2181 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 2182 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer << 2183 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) & 2184 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK; 2185 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID; 2186 } 2187 if (attr_mask & IB_QP_RNR_RETRY) { 2188 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry << 2189 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT) 2190 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK; 2191 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID; 2192 } 2193 if (attr_mask & IB_QP_SQ_PSN) { 2194 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff); 2195 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID; 2196 } 2197 if (attr_mask & IB_QP_RQ_PSN) { 2198 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff); 2199 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID; 2200 } 2201 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2202 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) { 2203 status = -EINVAL; 2204 goto pmtu_err; 2205 } 2206 qp->max_ord = attrs->max_rd_atomic; 2207 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID; 2208 } 2209 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2210 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) { 2211 status = -EINVAL; 2212 goto pmtu_err; 2213 } 2214 qp->max_ird = attrs->max_dest_rd_atomic; 2215 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID; 2216 } 2217 cmd->params.max_ord_ird = (qp->max_ord << 2218 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) | 2219 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK); 2220pmtu_err: 2221 return status; 2222} 2223 2224int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp, 2225 struct ib_qp_attr *attrs, int attr_mask, 2226 enum ib_qp_state old_qps) 2227{ 2228 int status = -ENOMEM; 2229 struct ocrdma_modify_qp *cmd; 2230 2231 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd)); 2232 if (!cmd) 2233 return status; 2234 2235 cmd->params.id = qp->id; 2236 cmd->flags = 0; 2237 if (attr_mask & IB_QP_STATE) { 2238 cmd->params.max_sge_recv_flags |= 2239 (get_ocrdma_qp_state(attrs->qp_state) << 2240 OCRDMA_QP_PARAMS_STATE_SHIFT) & 2241 OCRDMA_QP_PARAMS_STATE_MASK; 2242 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID; 2243 } else { 2244 cmd->params.max_sge_recv_flags |= 2245 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) & 2246 OCRDMA_QP_PARAMS_STATE_MASK; 2247 } 2248 2249 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask, old_qps); 2250 if (status) 2251 goto mbx_err; 2252 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 2253 if (status) 2254 goto mbx_err; 2255 2256mbx_err: 2257 kfree(cmd); 2258 return status; 2259} 2260 2261int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp) 2262{ 2263 int status = -ENOMEM; 2264 struct ocrdma_destroy_qp *cmd; 2265 struct pci_dev *pdev = dev->nic_info.pdev; 2266 2267 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd)); 2268 if (!cmd) 2269 return status; 2270 cmd->qp_id = qp->id; 2271 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 2272 if (status) 2273 goto mbx_err; 2274 2275mbx_err: 2276 kfree(cmd); 2277 if (qp->sq.va) 2278 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa); 2279 if (!qp->srq && qp->rq.va) 2280 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa); 2281 if (qp->dpp_enabled) 2282 qp->pd->num_dpp_qp++; 2283 return status; 2284} 2285 2286int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq, 2287 struct ib_srq_init_attr *srq_attr, 2288 struct ocrdma_pd *pd) 2289{ 2290 int status = -ENOMEM; 2291 int hw_pages, hw_page_size; 2292 int len; 2293 struct ocrdma_create_srq_rsp *rsp; 2294 struct ocrdma_create_srq *cmd; 2295 dma_addr_t pa; 2296 struct pci_dev *pdev = dev->nic_info.pdev; 2297 u32 max_rqe_allocated; 2298 2299 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd)); 2300 if (!cmd) 2301 return status; 2302 2303 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK; 2304 max_rqe_allocated = srq_attr->attr.max_wr + 1; 2305 status = ocrdma_build_q_conf(&max_rqe_allocated, 2306 dev->attr.rqe_size, 2307 &hw_pages, &hw_page_size); 2308 if (status) { 2309 pr_err("%s() req. max_wr=0x%x\n", __func__, 2310 srq_attr->attr.max_wr); 2311 status = -EINVAL; 2312 goto ret; 2313 } 2314 len = hw_pages * hw_page_size; 2315 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL); 2316 if (!srq->rq.va) { 2317 status = -ENOMEM; 2318 goto ret; 2319 } 2320 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size); 2321 2322 srq->rq.entry_size = dev->attr.rqe_size; 2323 srq->rq.pa = pa; 2324 srq->rq.len = len; 2325 srq->rq.max_cnt = max_rqe_allocated; 2326 2327 cmd->max_sge_rqe = ilog2(max_rqe_allocated); 2328 cmd->max_sge_rqe |= srq_attr->attr.max_sge << 2329 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT; 2330 2331 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) 2332 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT); 2333 cmd->pages_rqe_sz |= (dev->attr.rqe_size 2334 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT) 2335 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK; 2336 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT; 2337 2338 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 2339 if (status) 2340 goto mbx_err; 2341 rsp = (struct ocrdma_create_srq_rsp *)cmd; 2342 srq->id = rsp->id; 2343 srq->rq.dbid = rsp->id; 2344 max_rqe_allocated = ((rsp->max_sge_rqe_allocated & 2345 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >> 2346 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT); 2347 max_rqe_allocated = (1 << max_rqe_allocated); 2348 srq->rq.max_cnt = max_rqe_allocated; 2349 srq->rq.max_wqe_idx = max_rqe_allocated - 1; 2350 srq->rq.max_sges = (rsp->max_sge_rqe_allocated & 2351 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >> 2352 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT; 2353 goto ret; 2354mbx_err: 2355 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa); 2356ret: 2357 kfree(cmd); 2358 return status; 2359} 2360 2361int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr) 2362{ 2363 int status = -ENOMEM; 2364 struct ocrdma_modify_srq *cmd; 2365 struct ocrdma_pd *pd = srq->pd; 2366 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device); 2367 2368 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd)); 2369 if (!cmd) 2370 return status; 2371 cmd->id = srq->id; 2372 cmd->limit_max_rqe |= srq_attr->srq_limit << 2373 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT; 2374 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 2375 kfree(cmd); 2376 return status; 2377} 2378 2379int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr) 2380{ 2381 int status = -ENOMEM; 2382 struct ocrdma_query_srq *cmd; 2383 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device); 2384 2385 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd)); 2386 if (!cmd) 2387 return status; 2388 cmd->id = srq->rq.dbid; 2389 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 2390 if (status == 0) { 2391 struct ocrdma_query_srq_rsp *rsp = 2392 (struct ocrdma_query_srq_rsp *)cmd; 2393 srq_attr->max_sge = 2394 rsp->srq_lmt_max_sge & 2395 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK; 2396 srq_attr->max_wr = 2397 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT; 2398 srq_attr->srq_limit = rsp->srq_lmt_max_sge >> 2399 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT; 2400 } 2401 kfree(cmd); 2402 return status; 2403} 2404 2405int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq) 2406{ 2407 int status = -ENOMEM; 2408 struct ocrdma_destroy_srq *cmd; 2409 struct pci_dev *pdev = dev->nic_info.pdev; 2410 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd)); 2411 if (!cmd) 2412 return status; 2413 cmd->id = srq->id; 2414 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 2415 if (srq->rq.va) 2416 dma_free_coherent(&pdev->dev, srq->rq.len, 2417 srq->rq.va, srq->rq.pa); 2418 kfree(cmd); 2419 return status; 2420} 2421 2422int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah) 2423{ 2424 int i; 2425 int status = -EINVAL; 2426 struct ocrdma_av *av; 2427 unsigned long flags; 2428 2429 av = dev->av_tbl.va; 2430 spin_lock_irqsave(&dev->av_tbl.lock, flags); 2431 for (i = 0; i < dev->av_tbl.num_ah; i++) { 2432 if (av->valid == 0) { 2433 av->valid = OCRDMA_AV_VALID; 2434 ah->av = av; 2435 ah->id = i; 2436 status = 0; 2437 break; 2438 } 2439 av++; 2440 } 2441 if (i == dev->av_tbl.num_ah) 2442 status = -EAGAIN; 2443 spin_unlock_irqrestore(&dev->av_tbl.lock, flags); 2444 return status; 2445} 2446 2447int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah) 2448{ 2449 unsigned long flags; 2450 spin_lock_irqsave(&dev->av_tbl.lock, flags); 2451 ah->av->valid = 0; 2452 spin_unlock_irqrestore(&dev->av_tbl.lock, flags); 2453 return 0; 2454} 2455 2456static int ocrdma_create_eqs(struct ocrdma_dev *dev) 2457{ 2458 int num_eq, i, status = 0; 2459 int irq; 2460 unsigned long flags = 0; 2461 2462 num_eq = dev->nic_info.msix.num_vectors - 2463 dev->nic_info.msix.start_vector; 2464 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) { 2465 num_eq = 1; 2466 flags = IRQF_SHARED; 2467 } else { 2468 num_eq = min_t(u32, num_eq, num_online_cpus()); 2469 } 2470 2471 if (!num_eq) 2472 return -EINVAL; 2473 2474 dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL); 2475 if (!dev->eq_tbl) 2476 return -ENOMEM; 2477 2478 for (i = 0; i < num_eq; i++) { 2479 status = ocrdma_create_eq(dev, &dev->eq_tbl[i], 2480 OCRDMA_EQ_LEN); 2481 if (status) { 2482 status = -EINVAL; 2483 break; 2484 } 2485 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d", 2486 dev->id, i); 2487 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]); 2488 status = request_irq(irq, ocrdma_irq_handler, flags, 2489 dev->eq_tbl[i].irq_name, 2490 &dev->eq_tbl[i]); 2491 if (status) 2492 goto done; 2493 dev->eq_cnt += 1; 2494 } 2495 /* one eq is sufficient for data path to work */ 2496 return 0; 2497done: 2498 ocrdma_destroy_eqs(dev); 2499 return status; 2500} 2501 2502int ocrdma_init_hw(struct ocrdma_dev *dev) 2503{ 2504 int status; 2505 2506 /* create the eqs */ 2507 status = ocrdma_create_eqs(dev); 2508 if (status) 2509 goto qpeq_err; 2510 status = ocrdma_create_mq(dev); 2511 if (status) 2512 goto mq_err; 2513 status = ocrdma_mbx_query_fw_config(dev); 2514 if (status) 2515 goto conf_err; 2516 status = ocrdma_mbx_query_dev(dev); 2517 if (status) 2518 goto conf_err; 2519 status = ocrdma_mbx_query_fw_ver(dev); 2520 if (status) 2521 goto conf_err; 2522 status = ocrdma_mbx_create_ah_tbl(dev); 2523 if (status) 2524 goto conf_err; 2525 return 0; 2526 2527conf_err: 2528 ocrdma_destroy_mq(dev); 2529mq_err: 2530 ocrdma_destroy_eqs(dev); 2531qpeq_err: 2532 pr_err("%s() status=%d\n", __func__, status); 2533 return status; 2534} 2535 2536void ocrdma_cleanup_hw(struct ocrdma_dev *dev) 2537{ 2538 ocrdma_mbx_delete_ah_tbl(dev); 2539 2540 /* cleanup the eqs */ 2541 ocrdma_destroy_eqs(dev); 2542 2543 /* cleanup the control path */ 2544 ocrdma_destroy_mq(dev); 2545} 2546