arm-smmu.c revision 5552ecdbf9fb4f7608c1d7933a8baafcfa1bb337
145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* 245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * IOMMU API for ARM architected SMMU implementations. 345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * This program is free software; you can redistribute it and/or modify 545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * it under the terms of the GNU General Public License version 2 as 645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * published by the Free Software Foundation. 745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * This program is distributed in the hope that it will be useful, 945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * but WITHOUT ANY WARRANTY; without even the implied warranty of 1045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * GNU General Public License for more details. 1245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 1345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * You should have received a copy of the GNU General Public License 1445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * along with this program; if not, write to the Free Software 1545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 1645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 1745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Copyright (C) 2013 ARM Limited 1845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 1945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Author: Will Deacon <will.deacon@arm.com> 2045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 2145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * This driver currently supports: 2245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - SMMUv1 and v2 implementations 2345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - Stream-matching and stream-indexing 2445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - v7/v8 long-descriptor format 2545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - Non-secure access to the SMMU 2645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - 4k and 64k pages, with contiguous pte hints. 2745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - Up to 39-bit addressing 2845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - Context fault reporting 2945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 3045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 3145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define pr_fmt(fmt) "arm-smmu: " fmt 3245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 3345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/delay.h> 3445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/dma-mapping.h> 3545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/err.h> 3645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/interrupt.h> 3745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/io.h> 3845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/iommu.h> 3945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/mm.h> 4045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/module.h> 4145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/of.h> 4245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/platform_device.h> 4345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/slab.h> 4445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/spinlock.h> 4545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 4645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/amba/bus.h> 4745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 4845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <asm/pgalloc.h> 4945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 5045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Maximum number of stream IDs assigned to a single device */ 5145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAX_MASTER_STREAMIDS 8 5245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 5345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Maximum number of context banks per SMMU */ 5445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_MAX_CBS 128 5545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 5645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Maximum number of mapping groups per SMMU */ 5745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_MAX_SMRS 128 5845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 5945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* SMMU global address space */ 6045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0(smmu) ((smmu)->base) 6145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize) 6245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 6345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Page table bits */ 6445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0) 6545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52) 6645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_AF (((pteval_t)1) << 10) 6745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8) 6845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8) 6945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8) 7045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 7145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#if PAGE_SIZE == SZ_4K 7245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT_ENTRIES 16 7345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#elif PAGE_SIZE == SZ_64K 7445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT_ENTRIES 32 7545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#else 7645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT_ENTRIES 1 7745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 7845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 7945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES) 8045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1)) 8145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(pte_t)) 8245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 8345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Stage-1 PTE */ 8445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6) 8545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6) 8645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_ATTRINDX_SHIFT 2 871463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon#define ARM_SMMU_PTE_nG (((pteval_t)1) << 11) 8845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 8945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Stage-2 PTE */ 9045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6) 9145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6) 9245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6) 9345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2) 9445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2) 9545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2) 9645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 9745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Configuration registers */ 9845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sCR0 0x0 9945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_CLIENTPD (1 << 0) 10045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_GFRE (1 << 1) 10145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_GFIE (1 << 2) 10245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_GCFGFRE (1 << 4) 10345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_GCFGFIE (1 << 5) 10445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_USFCFG (1 << 10) 10545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_VMIDPNE (1 << 11) 10645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_PTM (1 << 12) 10745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_FB (1 << 13) 10845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_BSU_SHIFT 14 10945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_BSU_MASK 0x3 11045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 11145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Identification registers */ 11245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID0 0x20 11345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID1 0x24 11445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID2 0x28 11545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID3 0x2c 11645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID4 0x30 11745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID5 0x34 11845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID6 0x38 11945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID7 0x3c 12045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sGFSR 0x48 12145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sGFSYNR0 0x50 12245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sGFSYNR1 0x54 12345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sGFSYNR2 0x58 12445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_PIDR0 0xfe0 12545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_PIDR1 0xfe4 12645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_PIDR2 0xfe8 12745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 12845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_S1TS (1 << 30) 12945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_S2TS (1 << 29) 13045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_NTS (1 << 28) 13145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_SMS (1 << 27) 13245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_PTFS_SHIFT 24 13345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_PTFS_MASK 0x2 13445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_PTFS_V8_ONLY 0x2 13545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_CTTW (1 << 14) 13645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_NUMIRPT_SHIFT 16 13745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_NUMIRPT_MASK 0xff 13845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_NUMSMRG_SHIFT 0 13945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_NUMSMRG_MASK 0xff 14045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 14145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_PAGESIZE (1 << 31) 14245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMPAGENDXB_SHIFT 28 14345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMPAGENDXB_MASK 7 14445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMS2CB_SHIFT 16 14545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMS2CB_MASK 0xff 14645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMCB_SHIFT 0 14745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMCB_MASK 0xff 14845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 14945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_OAS_SHIFT 4 15045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_OAS_MASK 0xf 15145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_IAS_SHIFT 0 15245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_IAS_MASK 0xf 15345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_UBS_SHIFT 8 15445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_UBS_MASK 0xf 15545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_PTFS_4K (1 << 12) 15645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_PTFS_16K (1 << 13) 15745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_PTFS_64K (1 << 14) 15845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 15945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define PIDR2_ARCH_SHIFT 4 16045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define PIDR2_ARCH_MASK 0xf 16145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 16245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Global TLB invalidation */ 16345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_STLBIALL 0x60 16445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_TLBIVMID 0x64 16545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_TLBIALLNSNH 0x68 16645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_TLBIALLH 0x6c 16745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sTLBGSYNC 0x70 16845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sTLBGSTATUS 0x74 16945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sTLBGSTATUS_GSACTIVE (1 << 0) 17045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ 17145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 17245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Stream mapping registers */ 17345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) 17445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SMR_VALID (1 << 31) 17545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SMR_MASK_SHIFT 16 17645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SMR_MASK_MASK 0x7fff 17745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SMR_ID_SHIFT 0 17845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SMR_ID_MASK 0x7fff 17945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 18045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) 18145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_CBNDX_SHIFT 0 18245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_CBNDX_MASK 0xff 18345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_TYPE_SHIFT 16 18445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_TYPE_MASK 0x3 18545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) 18645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) 18745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) 18845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 18945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Context bank attribute registers */ 19045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) 19145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_VMID_SHIFT 0 19245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_VMID_MASK 0xff 19345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_S1_MEMATTR_SHIFT 12 19445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_S1_MEMATTR_MASK 0xf 19545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_S1_MEMATTR_WB 0xf 19645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_SHIFT 16 19745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_MASK 0x3 19845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) 19945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) 20045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) 20145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) 20245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_IRPTNDX_SHIFT 24 20345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_IRPTNDX_MASK 0xff 20445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 20545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) 20645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBA2R_RW64_32BIT (0 << 0) 20745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBA2R_RW64_64BIT (1 << 0) 20845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 20945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Translation context bank */ 21045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) 21145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize) 21245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 21345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_SCTLR 0x0 21445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_RESUME 0x8 21545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_TTBCR2 0x10 21645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_TTBR0_LO 0x20 21745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_TTBR0_HI 0x24 21845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_TTBCR 0x30 21945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_S1_MAIR0 0x38 22045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_FSR 0x58 22145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_FAR_LO 0x60 22245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_FAR_HI 0x64 22345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_FSYNR0 0x68 2241463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon#define ARM_SMMU_CB_S1_TLBIASID 0x610 22545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 22645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_S1_ASIDPNE (1 << 12) 22745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_CFCFG (1 << 7) 22845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_CFIE (1 << 6) 22945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_CFRE (1 << 5) 23045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_E (1 << 4) 23145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_AFE (1 << 2) 23245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_TRE (1 << 1) 23345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_M (1 << 0) 23445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) 23545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 23645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define RESUME_RETRY (0 << 0) 23745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define RESUME_TERMINATE (1 << 0) 23845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 23945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_EAE (1 << 31) 24045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 24145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_PASIZE_SHIFT 16 24245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_PASIZE_MASK 0x7 24345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 24445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_TG0_4K (0 << 14) 24545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_TG0_64K (1 << 14) 24645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 24745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SH0_SHIFT 12 24845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SH0_MASK 0x3 24945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SH_NS 0 25045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SH_OS 2 25145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SH_IS 3 25245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 25345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_ORGN0_SHIFT 10 25445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_IRGN0_SHIFT 8 25545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_RGN_MASK 0x3 25645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_RGN_NC 0 25745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_RGN_WBWA 1 25845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_RGN_WT 2 25945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_RGN_WB 3 26045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 26145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SL0_SHIFT 6 26245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SL0_MASK 0x3 26345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SL0_LVL_2 0 26445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SL0_LVL_1 1 26545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 26645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_T1SZ_SHIFT 16 26745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_T0SZ_SHIFT 0 26845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SZ_MASK 0xf 26945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 27045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_SEP_SHIFT 15 27145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_SEP_MASK 0x7 27245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 27345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_PASIZE_SHIFT 0 27445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_PASIZE_MASK 0x7 27545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 27645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Common definitions for PASize and SEP fields */ 27745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_32 0 27845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_36 1 27945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_40 2 28045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_42 3 28145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_44 4 28245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_48 5 28345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 2841463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon#define TTBRn_HI_ASID_SHIFT 16 2851463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon 28645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_SHIFT(n) ((n) << 3) 28745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_MASK 0xff 28845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_DEVICE 0x04 28945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_NC 0x44 29045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_WBRWA 0xff 29145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_IDX_NC 0 29245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_IDX_CACHE 1 29345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_IDX_DEV 2 29445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 29545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_MULTI (1 << 31) 29645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_SS (1 << 30) 29745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_UUT (1 << 8) 29845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_ASF (1 << 7) 29945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_TLBLKF (1 << 6) 30045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_TLBMCF (1 << 5) 30145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_EF (1 << 4) 30245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_PF (1 << 3) 30345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_AFF (1 << 2) 30445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_TF (1 << 1) 30545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 30645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_IGN (FSR_AFF | FSR_ASF | FSR_TLBMCF | \ 30745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon FSR_TLBLKF) 30845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ 309adaba320916d246af56821a1aab81a715091e7e5Will Deacon FSR_EF | FSR_PF | FSR_TF | FSR_IGN) 31045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 31145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSYNR0_WNR (1 << 4) 31245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 31345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstruct arm_smmu_smr { 31445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u8 idx; 31545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u16 mask; 31645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u16 id; 31745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 31845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 31945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstruct arm_smmu_master { 32045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device_node *of_node; 32145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 32245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 32345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * The following is specific to the master's position in the 32445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * SMMU chain. 32545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 32645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_node node; 32745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int num_streamids; 32845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u16 streamids[MAX_MASTER_STREAMIDS]; 32945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 33045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 33145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We only need to allocate these on the root SMMU, as we 33245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * configure unmatched streams to bypass translation. 33345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 33445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_smr *smrs; 33545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 33645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 33745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstruct arm_smmu_device { 33845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device *dev; 33945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device_node *parent_of_node; 34045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 34145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *base; 34245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long size; 34345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long pagesize; 34445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 34545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) 34645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) 34745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) 34845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) 34945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) 35045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 features; 35145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int version; 35245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 35345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 num_context_banks; 35445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 num_s2_context_banks; 35545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); 35645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon atomic_t irptndx; 35745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 35845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 num_mapping_groups; 35945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); 36045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 36145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long input_size; 36245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long s1_output_size; 36345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long s2_output_size; 36445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 36545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 num_global_irqs; 36645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 num_context_irqs; 36745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned int *irqs; 36845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 36945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct list_head list; 37045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_root masters; 37145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 37245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 37345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstruct arm_smmu_cfg { 37445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu; 37545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u8 cbndx; 37645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u8 irptndx; 37745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 cbar; 37845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_t *pgd; 37945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 380faea13b72dbdb77e4d6ad83344596486611708b0Dan Carpenter#define INVALID_IRPTNDX 0xff 38145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 382ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon#define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) 383ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon#define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) 384ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon 38545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstruct arm_smmu_domain { 38645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 38745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * A domain can span across multiple, chained SMMUs and requires 38845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * all devices within the domain to follow the same translation 38945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * path. 39045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 39145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *leaf_smmu; 39245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg root_cfg; 39345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys_addr_t output_mask; 39445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 395a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon struct mutex lock; 39645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 39745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 39845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic DEFINE_SPINLOCK(arm_smmu_devices_lock); 39945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic LIST_HEAD(arm_smmu_devices); 40045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 40145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, 40245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device_node *dev_node) 40345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 40445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_node *node = smmu->masters.rb_node; 40545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 40645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (node) { 40745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 40845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = container_of(node, struct arm_smmu_master, node); 40945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 41045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (dev_node < master->of_node) 41145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon node = node->rb_left; 41245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else if (dev_node > master->of_node) 41345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon node = node->rb_right; 41445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else 41545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return master; 41645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 41745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 41845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return NULL; 41945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 42045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 42145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int insert_smmu_master(struct arm_smmu_device *smmu, 42245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 42345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 42445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_node **new, *parent; 42545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 42645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon new = &smmu->masters.rb_node; 42745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon parent = NULL; 42845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (*new) { 42945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *this; 43045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon this = container_of(*new, struct arm_smmu_master, node); 43145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 43245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon parent = *new; 43345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master->of_node < this->of_node) 43445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon new = &((*new)->rb_left); 43545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else if (master->of_node > this->of_node) 43645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon new = &((*new)->rb_right); 43745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else 43845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EEXIST; 43945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 44045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 44145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon rb_link_node(&master->node, parent, new); 44245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon rb_insert_color(&master->node, &smmu->masters); 44345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 44445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 44545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 44645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int register_smmu_master(struct arm_smmu_device *smmu, 44745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device *dev, 44845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct of_phandle_args *masterspec) 44945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 45045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 45145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 45245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 45345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = find_smmu_master(smmu, masterspec->np); 45445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master) { 45545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, 45645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "rejecting multiple registrations for master device %s\n", 45745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon masterspec->np->name); 45845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EBUSY; 45945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 46045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 46145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (masterspec->args_count > MAX_MASTER_STREAMIDS) { 46245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, 46345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "reached maximum number (%d) of stream IDs for master device %s\n", 46445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon MAX_MASTER_STREAMIDS, masterspec->np->name); 46545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOSPC; 46645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 46745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 46845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); 46945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!master) 47045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 47145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 47245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->of_node = masterspec->np; 47345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->num_streamids = masterspec->args_count; 47445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 47545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) 47645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->streamids[i] = masterspec->args[i]; 47745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 47845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return insert_smmu_master(smmu, master); 47945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 48045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 48145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu) 48245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 48345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *parent; 48445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 48545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu->parent_of_node) 48645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return NULL; 48745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 48845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&arm_smmu_devices_lock); 48945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_for_each_entry(parent, &arm_smmu_devices, list) 49045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (parent->dev->of_node == smmu->parent_of_node) 49145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_unlock; 49245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 49345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon parent = NULL; 49445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_warn(smmu->dev, 49545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "Failed to find SMMU parent despite parent in DT\n"); 49645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_unlock: 49745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&arm_smmu_devices_lock); 49845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return parent; 49945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 50045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 50145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) 50245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 50345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int idx; 50445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 50545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 50645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon idx = find_next_zero_bit(map, end, start); 50745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (idx == end) 50845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOSPC; 50945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (test_and_set_bit(idx, map)); 51045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 51145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return idx; 51245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 51345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 51445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void __arm_smmu_free_bitmap(unsigned long *map, int idx) 51545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 51645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon clear_bit(idx, map); 51745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 51845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 51945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Wait for any pending TLB invalidations to complete */ 52045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_tlb_sync(struct arm_smmu_device *smmu) 52145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 52245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int count = 0; 52345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 52445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 52545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); 52645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) 52745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon & sTLBGSTATUS_GSACTIVE) { 52845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon cpu_relax(); 52945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (++count == TLB_LOOP_TIMEOUT) { 53045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err_ratelimited(smmu->dev, 53145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "TLB sync timed out -- SMMU may be deadlocked\n"); 53245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return; 53345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 53445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon udelay(1); 53545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 53645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 53745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 5381463fe44fd0f87af0404e2c147ab9724081b7235Will Deaconstatic void arm_smmu_tlb_inv_context(struct arm_smmu_cfg *cfg) 5391463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon{ 5401463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon struct arm_smmu_device *smmu = cfg->smmu; 5411463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon void __iomem *base = ARM_SMMU_GR0(smmu); 5421463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; 5431463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon 5441463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon if (stage1) { 5451463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); 546ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon writel_relaxed(ARM_SMMU_CB_ASID(cfg), 547ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon base + ARM_SMMU_CB_S1_TLBIASID); 5481463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon } else { 5491463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon base = ARM_SMMU_GR0(smmu); 550ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon writel_relaxed(ARM_SMMU_CB_VMID(cfg), 551ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon base + ARM_SMMU_GR0_TLBIVMID); 5521463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon } 5531463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon 5541463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon arm_smmu_tlb_sync(smmu); 5551463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon} 5561463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon 55745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic irqreturn_t arm_smmu_context_fault(int irq, void *dev) 55845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 55945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int flags, ret; 56045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 fsr, far, fsynr, resume; 56145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long iova; 56245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct iommu_domain *domain = dev; 56345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 56445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 56545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = root_cfg->smmu; 56645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *cb_base; 56745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 56845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx); 56945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); 57045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 57145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(fsr & FSR_FAULT)) 57245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return IRQ_NONE; 57345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 57445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (fsr & FSR_IGN) 57545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err_ratelimited(smmu->dev, 57645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "Unexpected context fault (fsr 0x%u)\n", 57745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon fsr); 57845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 57945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); 58045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; 58145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 58245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); 58345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon iova = far; 58445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef CONFIG_64BIT 58545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); 58645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon iova |= ((unsigned long)far << 32); 58745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 58845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 58945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { 59045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = IRQ_HANDLED; 59145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon resume = RESUME_RETRY; 59245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 5932ef0f03120ea2ad64d0e70f032a58e6c13603cdcAndreas Herrmann dev_err_ratelimited(smmu->dev, 5942ef0f03120ea2ad64d0e70f032a58e6c13603cdcAndreas Herrmann "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", 5952ef0f03120ea2ad64d0e70f032a58e6c13603cdcAndreas Herrmann iova, fsynr, root_cfg->cbndx); 59645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = IRQ_NONE; 59745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon resume = RESUME_TERMINATE; 59845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 59945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 60045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Clear the faulting FSR */ 60145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel(fsr, cb_base + ARM_SMMU_CB_FSR); 60245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 60345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Retry or terminate any stalled transactions */ 60445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (fsr & FSR_SS) 60545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); 60645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 60745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 60845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 60945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 61045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic irqreturn_t arm_smmu_global_fault(int irq, void *dev) 61145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 61245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 gfsr, gfsynr0, gfsynr1, gfsynr2; 61345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = dev; 61445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 61545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 61645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); 617adaba320916d246af56821a1aab81a715091e7e5Will Deacon if (!gfsr) 618adaba320916d246af56821a1aab81a715091e7e5Will Deacon return IRQ_NONE; 619adaba320916d246af56821a1aab81a715091e7e5Will Deacon 62045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); 62145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); 62245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); 62345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 62445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err_ratelimited(smmu->dev, 62545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "Unexpected global fault, this could be serious\n"); 62645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err_ratelimited(smmu->dev, 62745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", 62845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gfsr, gfsynr0, gfsynr1, gfsynr2); 62945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 63045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); 631adaba320916d246af56821a1aab81a715091e7e5Will Deacon return IRQ_HANDLED; 63245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 63345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 63445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) 63545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 63645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 reg; 63745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon bool stage1; 63845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 63945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = root_cfg->smmu; 64045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *cb_base, *gr0_base, *gr1_base; 64145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 64245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gr0_base = ARM_SMMU_GR0(smmu); 64345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gr1_base = ARM_SMMU_GR1(smmu); 64445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS; 64545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx); 64645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 64745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* CBAR */ 6481463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon reg = root_cfg->cbar; 64945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version == 1) 65045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT; 65145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 65245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Use the weakest memory type, so it is overridden by the pte */ 65345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (stage1) 65445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); 6551463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon else 656ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon reg |= ARM_SMMU_CB_VMID(root_cfg) << CBAR_VMID_SHIFT; 65745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(root_cfg->cbndx)); 65845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 65945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version > 1) { 66045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* CBA2R */ 66145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef CONFIG_64BIT 66245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = CBA2R_RW64_64BIT; 66345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#else 66445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = CBA2R_RW64_32BIT; 66545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 66645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, 66745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gr1_base + ARM_SMMU_GR1_CBA2R(root_cfg->cbndx)); 66845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 66945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* TTBCR2 */ 67045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon switch (smmu->input_size) { 67145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 32: 67245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); 67345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 67445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 36: 67545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); 67645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 67745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 39: 67845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); 67945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 68045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 42: 68145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); 68245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 68345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 44: 68445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); 68545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 68645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 48: 68745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); 68845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 68945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 69045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 69145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon switch (smmu->s1_output_size) { 69245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 32: 69345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT); 69445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 69545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 36: 69645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT); 69745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 69845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 39: 69945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT); 70045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 70145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 42: 70245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT); 70345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 70445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 44: 70545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT); 70645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 70745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 48: 70845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT); 70945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 71045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 71145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 71245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (stage1) 71345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); 71445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 71545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 71645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* TTBR0 */ 71745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = __pa(root_cfg->pgd); 71845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); 71945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (phys_addr_t)__pa(root_cfg->pgd) >> 32; 7201463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon if (stage1) 721ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon reg |= ARM_SMMU_CB_ASID(root_cfg) << TTBRn_HI_ASID_SHIFT; 72245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); 72345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 72445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 72545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * TTBCR 72645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We use long descriptor, with inner-shareable WBWA tables in TTBR0. 72745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 72845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version > 1) { 72945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (PAGE_SIZE == SZ_4K) 73045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = TTBCR_TG0_4K; 73145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else 73245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = TTBCR_TG0_64K; 73345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 73445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!stage1) { 73545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon switch (smmu->s2_output_size) { 73645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 32: 73745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT); 73845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 73945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 36: 74045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT); 74145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 74245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 40: 74345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT); 74445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 74545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 42: 74645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT); 74745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 74845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 44: 74945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT); 75045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 75145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 48: 75245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); 75345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 75445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 75545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 75645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT; 75745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 75845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 75945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = 0; 76045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 76145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 76245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= TTBCR_EAE | 76345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | 76445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | 76545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) | 76645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); 76745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); 76845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 76945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* MAIR0 (stage-1 only) */ 77045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (stage1) { 77145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) | 77245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) | 77345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV)); 77445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); 77545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 77645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 77745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* SCTLR */ 77845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; 77945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (stage1) 78045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= SCTLR_S1_ASIDPNE; 78145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef __BIG_ENDIAN 78245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= SCTLR_E; 78345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 78425724841dfaed05f23a3ddaaaed5c9b61ceea7bdWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); 78545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 78645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 78745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_init_domain_context(struct iommu_domain *domain, 78845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device *dev) 78945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 79045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int irq, ret, start; 79145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 79245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 79345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu, *parent; 79445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 79545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 79645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Walk the SMMU chain to find the root device for this chain. 79745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We assume that no masters have translations which terminate 79845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * early, and therefore check that the root SMMU does indeed have 79945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * a StreamID for the master in question. 80045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 80145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon parent = dev->archdata.iommu; 80245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu_domain->output_mask = -1; 80345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 80445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = parent; 80545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu_domain->output_mask &= (1ULL << smmu->s2_output_size) - 1; 80645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while ((parent = find_parent_smmu(smmu))); 80745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 80845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!find_smmu_master(smmu, dev->of_node)) { 80945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "unable to find root SMMU for device\n"); 81045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 81145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 81245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 81345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { 81445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 81545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We will likely want to change this if/when KVM gets 81645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * involved. 81745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 81845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; 81945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon start = smmu->num_s2_context_banks; 82045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) { 82145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->cbar = CBAR_TYPE_S2_TRANS; 82245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon start = 0; 82345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 82445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; 82545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon start = smmu->num_s2_context_banks; 82645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 82745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 82845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, 82945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_banks); 83045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (IS_ERR_VALUE(ret)) 831ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon return ret; 83245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 83345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->cbndx = ret; 83445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version == 1) { 83545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->irptndx = atomic_inc_return(&smmu->irptndx); 83645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->irptndx %= smmu->num_context_irqs; 83745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 83845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->irptndx = root_cfg->cbndx; 83945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 84045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 84145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx]; 84245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, 84345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "arm-smmu-context-fault", domain); 84445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (IS_ERR_VALUE(ret)) { 84545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", 84645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->irptndx, irq); 847faea13b72dbdb77e4d6ad83344596486611708b0Dan Carpenter root_cfg->irptndx = INVALID_IRPTNDX; 84845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_free_context; 84945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 85045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 85145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->smmu = smmu; 85245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_init_context_bank(smmu_domain); 85345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 85445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 85545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_free_context: 85645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx); 85745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 85845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 85945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 86045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_destroy_domain_context(struct iommu_domain *domain) 86145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 86245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 86345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 86445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = root_cfg->smmu; 8651463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon void __iomem *cb_base; 86645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int irq; 86745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 86845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu) 86945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return; 87045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 8711463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon /* Disable the context bank and nuke the TLB before freeing it. */ 8721463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx); 8731463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); 8741463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon arm_smmu_tlb_inv_context(root_cfg); 8751463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon 876faea13b72dbdb77e4d6ad83344596486611708b0Dan Carpenter if (root_cfg->irptndx != INVALID_IRPTNDX) { 87745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx]; 87845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon free_irq(irq, domain); 87945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 88045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 88145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx); 88245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 88345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 88445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_domain_init(struct iommu_domain *domain) 88545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 88645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain; 88745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_t *pgd; 88845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 88945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 89045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Allocate the domain and initialise some of its data structures. 89145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We can't really do anything meaningful until we've added a 89245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * master. 89345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 89445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); 89545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu_domain) 89645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 89745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 89845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL); 89945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!pgd) 90045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_free_domain; 90145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu_domain->root_cfg.pgd = pgd; 90245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 903a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon mutex_init(&smmu_domain->lock); 90445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon domain->priv = smmu_domain; 90545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 90645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 90745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_free_domain: 90845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon kfree(smmu_domain); 90945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 91045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 91145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 91245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_free_ptes(pmd_t *pmd) 91345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 91445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgtable_t table = pmd_pgtable(*pmd); 91545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgtable_page_dtor(table); 91645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __free_page(table); 91745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 91845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 91945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_free_pmds(pud_t *pud) 92045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 92145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 92245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd_t *pmd, *pmd_base = pmd_offset(pud, 0); 92345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 92445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd = pmd_base; 92545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < PTRS_PER_PMD; ++i) { 92645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pmd_none(*pmd)) 92745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon continue; 92845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 92945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_free_ptes(pmd); 93045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd++; 93145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 93245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 93345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd_free(NULL, pmd_base); 93445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 93545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 93645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_free_puds(pgd_t *pgd) 93745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 93845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 93945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud_t *pud, *pud_base = pud_offset(pgd, 0); 94045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 94145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud = pud_base; 94245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < PTRS_PER_PUD; ++i) { 94345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pud_none(*pud)) 94445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon continue; 94545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 94645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_free_pmds(pud); 94745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud++; 94845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 94945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 95045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud_free(NULL, pud_base); 95145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 95245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 95345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain) 95445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 95545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 95645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 95745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_t *pgd, *pgd_base = root_cfg->pgd; 95845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 95945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 96045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Recursively free the page tables for this domain. We don't 96145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * care about speculative TLB filling, because the TLB will be 96245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * nuked next time this context bank is re-allocated and no devices 96345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * currently map to these tables. 96445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 96545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd = pgd_base; 96645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < PTRS_PER_PGD; ++i) { 96745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pgd_none(*pgd)) 96845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon continue; 96945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_free_puds(pgd); 97045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd++; 97145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 97245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 97345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon kfree(pgd_base); 97445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 97545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 97645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_domain_destroy(struct iommu_domain *domain) 97745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 97845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 9791463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon 9801463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon /* 9811463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon * Free the domain resources. We assume that all devices have 9821463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon * already been detached. 9831463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon */ 98445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_destroy_domain_context(domain); 98545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_free_pgtables(smmu_domain); 98645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon kfree(smmu_domain); 98745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 98845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 98945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, 99045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 99145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 99245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 99345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_smr *smrs; 99445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 99545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 99645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) 99745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 99845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 99945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master->smrs) 100045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EEXIST; 100145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 100245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL); 100345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smrs) { 100445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n", 100545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->num_streamids, master->of_node->name); 100645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 100745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 100845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 100945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Allocate the SMRs on the root SMMU */ 101045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) { 101145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, 101245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_mapping_groups); 101345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (IS_ERR_VALUE(idx)) { 101445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "failed to allocate free SMR\n"); 101545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_free_smrs; 101645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 101745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 101845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smrs[i] = (struct arm_smmu_smr) { 101945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .idx = idx, 102045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .mask = 0, /* We don't currently share SMRs */ 102145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .id = master->streamids[i], 102245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon }; 102345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 102445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 102545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* It worked! Now, poke the actual hardware */ 102645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) { 102745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | 102845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smrs[i].mask << SMR_MASK_SHIFT; 102945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); 103045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 103145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 103245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->smrs = smrs; 103345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 103445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 103545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconerr_free_smrs: 103645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (--i >= 0) 103745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); 103845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon kfree(smrs); 103945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOSPC; 104045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 104145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 104245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, 104345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 104445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 104545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 104645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 104745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_smr *smrs = master->smrs; 104845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 104945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Invalidate the SMRs before freeing back to the allocator */ 105045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) { 105145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u8 idx = smrs[i].idx; 105245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); 105345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __arm_smmu_free_bitmap(smmu->smr_map, idx); 105445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 105545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 105645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->smrs = NULL; 105745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon kfree(smrs); 105845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 105945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 106045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu, 106145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 106245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 106345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 106445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 106545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 106645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) { 106745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u16 sid = master->streamids[i]; 106845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(S2CR_TYPE_BYPASS, 106945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gr0_base + ARM_SMMU_GR0_S2CR(sid)); 107045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 107145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 107245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 107345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, 107445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 107545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 107645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i, ret; 107745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *parent, *smmu = smmu_domain->root_cfg.smmu; 107845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 107945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 108045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_master_configure_smrs(smmu, master); 108145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (ret) 108245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 108345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 108445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Bypass the leaves */ 108545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = smmu_domain->leaf_smmu; 108645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while ((parent = find_parent_smmu(smmu))) { 108745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 108845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We won't have a StreamID match for anything but the root 108945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * smmu, so we only need to worry about StreamID indexing, 109045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * where we must install bypass entries in the S2CRs. 109145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 109245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) 109345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon continue; 109445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 109545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_bypass_stream_mapping(smmu, master); 109645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = parent; 109745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 109845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 109945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Now we're at the root, time to point at our context bank */ 110045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) { 110145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 idx, s2cr; 110245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon idx = master->smrs ? master->smrs[i].idx : master->streamids[i]; 110345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon s2cr = (S2CR_TYPE_TRANS << S2CR_TYPE_SHIFT) | 110445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT); 110545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); 110645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 110745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 110845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 110945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 111045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 111145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, 111245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 111345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 111445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = smmu_domain->root_cfg.smmu; 111545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 111645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 111745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We *must* clear the S2CR first, because freeing the SMR means 111845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * that it can be re-allocated immediately. 111945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 112045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_bypass_stream_mapping(smmu, master); 112145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_master_free_smrs(smmu, master); 112245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 112345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 112445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) 112545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 112645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret = -EINVAL; 112745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 112845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *device_smmu = dev->archdata.iommu; 112945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 113045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 113145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!device_smmu) { 113245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); 113345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENXIO; 113445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 113545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 113645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 113745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Sanity check the domain. We don't currently support domains 113845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * that cross between different SMMU chains. 113945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 1140a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon mutex_lock(&smmu_domain->lock); 114145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu_domain->leaf_smmu) { 114245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Now that we have a master, we can finalise the domain */ 114345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_init_domain_context(domain, dev); 114445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (IS_ERR_VALUE(ret)) 114545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_unlock; 114645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 114745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu_domain->leaf_smmu = device_smmu; 114845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else if (smmu_domain->leaf_smmu != device_smmu) { 114945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, 115045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", 115145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_name(smmu_domain->leaf_smmu->dev), 115245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_name(device_smmu->dev)); 115345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_unlock; 115445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 1155a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon mutex_unlock(&smmu_domain->lock); 115645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 115745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Looks ok, so add the device to the domain */ 115845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node); 115945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!master) 116045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 116145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 116245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return arm_smmu_domain_add_master(smmu_domain, master); 116345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 116445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconerr_unlock: 1165a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon mutex_unlock(&smmu_domain->lock); 116645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 116745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 116845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 116945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) 117045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 117145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 117245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 117345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 117445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node); 117545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master) 117645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_domain_remove_master(smmu_domain, master); 117745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 117845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 117945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, 118045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size_t size) 118145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 118245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long offset = (unsigned long)addr & ~PAGE_MASK; 118345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 118445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 118545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * If the SMMU can't walk tables in the CPU caches, treat them 118645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * like non-coherent DMA since we need to flush the new entries 118745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * all the way out to memory. There's no possibility of recursion 118845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * here as the SMMU table walker will not be wired through another 118945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * SMMU. 119045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 119145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)) 119245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dma_map_page(smmu->dev, virt_to_page(addr), offset, size, 119345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon DMA_TO_DEVICE); 119445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 119545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 119645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic bool arm_smmu_pte_is_contiguous_range(unsigned long addr, 119745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long end) 119845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 119945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return !(addr & ~ARM_SMMU_PTE_CONT_MASK) && 120045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (addr + ARM_SMMU_PTE_CONT_SIZE <= end); 120145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 120245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 120345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, 120445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long addr, unsigned long end, 120545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long pfn, int flags, int stage) 120645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 120745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pte_t *pte, *start; 120845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF; 120945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 121045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pmd_none(*pmd)) { 121145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Allocate a new set of tables */ 121245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgtable_t table = alloc_page(PGALLOC_GFP); 121345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!table) 121445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 121545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 121645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, page_address(table), 121745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ARM_SMMU_PTE_HWTABLE_SIZE); 121801058e70767de7b846588ef651c4d66e862f6823Kirill A. Shutemov if (!pgtable_page_ctor(table)) { 121901058e70767de7b846588ef651c4d66e862f6823Kirill A. Shutemov __free_page(table); 122001058e70767de7b846588ef651c4d66e862f6823Kirill A. Shutemov return -ENOMEM; 122101058e70767de7b846588ef651c4d66e862f6823Kirill A. Shutemov } 122245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd_populate(NULL, pmd, table); 122345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd)); 122445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 122545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 122645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (stage == 1) { 12271463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG; 122845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ)) 122945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_AP_RDONLY; 123045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 123145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (flags & IOMMU_CACHE) 123245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= (MAIR_ATTR_IDX_CACHE << 123345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ARM_SMMU_PTE_ATTRINDX_SHIFT); 123445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 123545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_HAP_FAULT; 123645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (flags & IOMMU_READ) 123745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_HAP_READ; 123845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (flags & IOMMU_WRITE) 123945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_HAP_WRITE; 124045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (flags & IOMMU_CACHE) 124145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_MEMATTR_OIWB; 124245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else 124345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_MEMATTR_NC; 124445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 124545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 124645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* If no access, create a faulting entry to avoid TLB fills */ 124745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(flags & (IOMMU_READ | IOMMU_WRITE))) 124845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval &= ~ARM_SMMU_PTE_PAGE; 124945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 125045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_SH_IS; 125145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon start = pmd_page_vaddr(*pmd) + pte_index(addr); 125245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pte = start; 125345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 125445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 125545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Install the page table entries. This is fairly complicated 125645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * since we attempt to make use of the contiguous hint in the 125745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * ptes where possible. The contiguous hint indicates a series 125845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically 125945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * contiguous region with the following constraints: 126045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 126145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE 126245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - Each pte in the region has the contiguous hint bit set 126345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 126445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * This complicates unmapping (also handled by this code, when 126545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * neither IOMMU_READ or IOMMU_WRITE are set) because it is 126645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * possible, yet highly unlikely, that a client may unmap only 126745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * part of a contiguous range. This requires clearing of the 126845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * contiguous hint bits in the range before installing the new 126945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * faulting entries. 127045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 127145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Note that re-mapping an address range without first unmapping 127245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * it is not supported, so TLB invalidation is not required here 127345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * and is instead performed at unmap and domain-init time. 127445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 127545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 127645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i = 1; 127745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval &= ~ARM_SMMU_PTE_CONT; 127845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 127945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (arm_smmu_pte_is_contiguous_range(addr, end)) { 128045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon i = ARM_SMMU_PTE_CONT_ENTRIES; 128145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_CONT; 128245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else if (pte_val(*pte) & 128345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) { 128445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int j; 128545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pte_t *cont_start; 128645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long idx = pte_index(addr); 128745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 128845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1); 128945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon cont_start = pmd_page_vaddr(*pmd) + idx; 129045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j) 129145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT; 129245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 129345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, cont_start, 129445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon sizeof(*pte) * 129545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ARM_SMMU_PTE_CONT_ENTRIES); 129645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 129745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 129845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 129945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon *pte = pfn_pte(pfn, __pgprot(pteval)); 130045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (pte++, pfn++, addr += PAGE_SIZE, --i); 130145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (addr != end); 130245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 130345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start)); 130445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 130545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 130645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 130745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud, 130845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long addr, unsigned long end, 130945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys_addr_t phys, int flags, int stage) 131045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 131145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret; 131245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd_t *pmd; 131345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long next, pfn = __phys_to_pfn(phys); 131445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 131545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifndef __PAGETABLE_PMD_FOLDED 131645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pud_none(*pud)) { 131745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd = pmd_alloc_one(NULL, addr); 131845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!pmd) 131945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 132045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else 132145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 132245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd = pmd_offset(pud, addr); 132345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 132445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 132545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon next = pmd_addr_end(addr, end); 132645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn, 132745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon flags, stage); 132845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud_populate(NULL, pud, pmd); 132945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud)); 133045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys += next - addr; 133145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (pmd++, addr = next, addr < end); 133245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 133345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 133445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 133545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 133645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd, 133745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long addr, unsigned long end, 133845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys_addr_t phys, int flags, int stage) 133945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 134045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret = 0; 134145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud_t *pud; 134245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long next; 134345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 134445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifndef __PAGETABLE_PUD_FOLDED 134545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pgd_none(*pgd)) { 134645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud = pud_alloc_one(NULL, addr); 134745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!pud) 134845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 134945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else 135045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 135145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud = pud_offset(pgd, addr); 135245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 135345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 135445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon next = pud_addr_end(addr, end); 135545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys, 135645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon flags, stage); 135745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_populate(NULL, pud, pgd); 135845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd)); 135945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys += next - addr; 136045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (pud++, addr = next, addr < end); 136145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 136245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 136345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 136445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 136545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain, 136645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long iova, phys_addr_t paddr, 136745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size_t size, int flags) 136845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 136945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret, stage; 137045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long end; 137145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys_addr_t input_mask, output_mask; 137245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 137345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_t *pgd = root_cfg->pgd; 137445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = root_cfg->smmu; 137545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 137645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) { 137745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon stage = 2; 137845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon output_mask = (1ULL << smmu->s2_output_size) - 1; 137945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 138045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon stage = 1; 138145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon output_mask = (1ULL << smmu->s1_output_size) - 1; 138245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 138345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 138445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!pgd) 138545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EINVAL; 138645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 138745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (size & ~PAGE_MASK) 138845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EINVAL; 138945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 139045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon input_mask = (1ULL << smmu->input_size) - 1; 139145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if ((phys_addr_t)iova & ~input_mask) 139245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ERANGE; 139345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 139445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (paddr & ~output_mask) 139545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ERANGE; 139645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1397a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon mutex_lock(&smmu_domain->lock); 139845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd += pgd_index(iova); 139945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon end = iova + size; 140045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 140145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long next = pgd_addr_end(iova, end); 140245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 140345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr, 140445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon flags, stage); 140545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (ret) 140645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_unlock; 140745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 140845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon paddr += next - iova; 140945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon iova = next; 141045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (pgd++, iova != end); 141145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 141245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_unlock: 1413a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon mutex_unlock(&smmu_domain->lock); 141445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 141545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Ensure new page tables are visible to the hardware walker */ 141645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) 141745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dsb(); 141845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 141945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 142045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 142145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 142245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, 142345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys_addr_t paddr, size_t size, int flags) 142445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 142545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 142645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 14275552ecdbf9fb4f7608c1d7933a8baafcfa1bb337Will Deacon if (!smmu_domain) 142845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 142945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 143045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Check for silent address truncation up the SMMU chain. */ 143145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if ((phys_addr_t)iova & ~smmu_domain->output_mask) 143245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ERANGE; 143345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 143445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags); 143545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 143645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 143745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, 143845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size_t size) 143945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 144045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret; 144145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 144245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 144345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0); 14441463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon arm_smmu_tlb_inv_context(&smmu_domain->root_cfg); 144545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret ? ret : size; 144645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 144745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 144845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, 144945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dma_addr_t iova) 145045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 1451a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon pgd_t *pgdp, pgd; 1452a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon pud_t pud; 1453a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon pmd_t pmd; 1454a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon pte_t pte; 145545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 145645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 145745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1458a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon pgdp = root_cfg->pgd; 1459a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon if (!pgdp) 1460a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon return 0; 146145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1462a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon pgd = *(pgdp + pgd_index(iova)); 1463a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon if (pgd_none(pgd)) 1464a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon return 0; 146545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1466a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon pud = *pud_offset(&pgd, iova); 1467a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon if (pud_none(pud)) 1468a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon return 0; 146945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1470a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon pmd = *pmd_offset(&pud, iova); 1471a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon if (pmd_none(pmd)) 1472a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon return 0; 147345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1474a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon pte = *(pmd_page_vaddr(pmd) + pte_index(iova)); 147545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pte_none(pte)) 1476a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon return 0; 147745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1478a44a9791e778d9ccda50d5534028ed4057a9a45bWill Deacon return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK); 147945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 148045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 148145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_domain_has_cap(struct iommu_domain *domain, 148245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long cap) 148345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 148445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long caps = 0; 148545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 148645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 148745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) 148845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon caps |= IOMMU_CAP_CACHE_COHERENCY; 148945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 149045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return !!(cap & caps); 149145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 149245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 149345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_add_device(struct device *dev) 149445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 149545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *child, *parent, *smmu; 149645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master = NULL; 149745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 149845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&arm_smmu_devices_lock); 149945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_for_each_entry(parent, &arm_smmu_devices, list) { 150045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = parent; 150145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 150245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Try to find a child of the current SMMU. */ 150345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_for_each_entry(child, &arm_smmu_devices, list) { 150445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (child->parent_of_node == parent->dev->of_node) { 150545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Does the child sit above our master? */ 150645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = find_smmu_master(child, dev->of_node); 150745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master) { 150845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = NULL; 150945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 151045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 151145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 151245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 151345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 151445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* We found some children, so keep searching. */ 151545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu) { 151645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = NULL; 151745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon continue; 151845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 151945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 152045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = find_smmu_master(smmu, dev->of_node); 152145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master) 152245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 152345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 152445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&arm_smmu_devices_lock); 152545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 152645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!master) 152745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 152845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 152945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev->archdata.iommu = smmu; 153045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 153145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 153245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 153345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_remove_device(struct device *dev) 153445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 153545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev->archdata.iommu = NULL; 153645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 153745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 153845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic struct iommu_ops arm_smmu_ops = { 153945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .domain_init = arm_smmu_domain_init, 154045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .domain_destroy = arm_smmu_domain_destroy, 154145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .attach_dev = arm_smmu_attach_dev, 154245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .detach_dev = arm_smmu_detach_dev, 154345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .map = arm_smmu_map, 154445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .unmap = arm_smmu_unmap, 154545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .iova_to_phys = arm_smmu_iova_to_phys, 154645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .domain_has_cap = arm_smmu_domain_has_cap, 154745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .add_device = arm_smmu_add_device, 154845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .remove_device = arm_smmu_remove_device, 154945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .pgsize_bitmap = (SECTION_SIZE | 155045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ARM_SMMU_PTE_CONT_SIZE | 155145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon PAGE_SIZE), 155245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 155345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 155445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_device_reset(struct arm_smmu_device *smmu) 155545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 155645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 1557659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann void __iomem *cb_base; 155845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i = 0; 1559659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann u32 reg; 1560659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann 1561659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann /* Clear Global FSR */ 1562659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); 1563659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann writel(reg, gr0_base + ARM_SMMU_GR0_sGFSR); 156445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 156545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Mark all SMRn as invalid and all S2CRn as bypass */ 156645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < smmu->num_mapping_groups; ++i) { 156745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i)); 156845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i)); 156945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 157045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1571659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann /* Make sure all context banks are disabled and clear CB_FSR */ 1572659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann for (i = 0; i < smmu->num_context_banks; ++i) { 1573659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); 1574659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); 1575659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); 1576659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann } 15771463fe44fd0f87af0404e2c147ab9724081b7235Will Deacon 157845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Invalidate the TLB, just in case */ 157945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL); 158045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); 158145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); 158245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1583659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0); 1584659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann 158545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Enable fault reporting */ 1586659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); 158745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 158845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Disable TLB broadcasting. */ 1589659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann reg |= (sCR0_VMIDPNE | sCR0_PTM); 159045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 159145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Enable client access, but bypass when no mapping is found */ 1592659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); 159345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 159445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Disable forced broadcasting */ 1595659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann reg &= ~sCR0_FB; 159645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 159745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Don't upgrade barriers */ 1598659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); 159945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 160045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Push the button */ 160145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_tlb_sync(smmu); 1602659db6f6beacae6fe49b5566debc4e82f678ff63Andreas Herrmann writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sCR0); 160345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 160445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 160545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_id_size_to_bits(int size) 160645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 160745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon switch (size) { 160845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 0: 160945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 32; 161045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 1: 161145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 36; 161245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 2: 161345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 40; 161445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 3: 161545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 42; 161645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 4: 161745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 44; 161845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 5: 161945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon default: 162045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 48; 162145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 162245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 162345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 162445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) 162545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 162645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long size; 162745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 162845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 id; 162945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 163045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "probing hardware configuration...\n"); 163145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 163245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Primecell ID */ 163345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2); 163445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1; 163545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); 163645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 163745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* ID0 */ 163845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); 163945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifndef CONFIG_64BIT 164045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) { 164145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "\tno v7 descriptor support!\n"); 164245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 164345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 164445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 164545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (id & ID0_S1TS) { 164645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->features |= ARM_SMMU_FEAT_TRANS_S1; 164745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "\tstage 1 translation\n"); 164845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 164945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 165045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (id & ID0_S2TS) { 165145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->features |= ARM_SMMU_FEAT_TRANS_S2; 165245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "\tstage 2 translation\n"); 165345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 165445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 165545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (id & ID0_NTS) { 165645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; 165745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "\tnested translation\n"); 165845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 165945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 166045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(smmu->features & 166145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 | 166245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ARM_SMMU_FEAT_TRANS_NESTED))) { 166345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "\tno translation support!\n"); 166445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 166545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 166645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 166745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (id & ID0_CTTW) { 166845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; 166945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "\tcoherent table walk\n"); 167045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 167145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 167245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (id & ID0_SMS) { 167345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 smr, sid, mask; 167445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 167545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; 167645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & 167745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ID0_NUMSMRG_MASK; 167845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->num_mapping_groups == 0) { 167945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, 168045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "stream-matching supported, but no SMRs present!\n"); 168145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 168245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 168345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 168445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smr = SMR_MASK_MASK << SMR_MASK_SHIFT; 168545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smr |= (SMR_ID_MASK << SMR_ID_SHIFT); 168645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); 168745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); 168845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 168945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; 169045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; 169145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if ((mask & sid) != sid) { 169245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, 169345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", 169445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon mask, sid); 169545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 169645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 169745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 169845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, 169945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "\tstream matching with %u register groups, mask 0x%x", 170045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_mapping_groups, mask); 170145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 170245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 170345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* ID1 */ 170445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); 170545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K; 170645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1707c55af7f719cbb0f0b28f42b3f98f662278f063c2Andreas Herrmann /* Check for size mismatch of SMMU address space from mapped region */ 170845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); 170945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size *= (smmu->pagesize << 1); 1710c55af7f719cbb0f0b28f42b3f98f662278f063c2Andreas Herrmann if (smmu->size != size) 1711c55af7f719cbb0f0b28f42b3f98f662278f063c2Andreas Herrmann dev_warn(smmu->dev, "SMMU address space size (0x%lx) differs " 1712c55af7f719cbb0f0b28f42b3f98f662278f063c2Andreas Herrmann "from mapped region size (0x%lx)!\n", size, smmu->size); 171345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 171445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & 171545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ID1_NUMS2CB_MASK; 171645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; 171745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->num_s2_context_banks > smmu->num_context_banks) { 171845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "impossible number of S2 context banks!\n"); 171945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 172045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 172145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", 172245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_banks, smmu->num_s2_context_banks); 172345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 172445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* ID2 */ 172545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); 172645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); 172745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 172845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 172945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Stage-1 output limited by stage-2 input size due to pgd 173045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * allocation (PTRS_PER_PGD). 173145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 173245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef CONFIG_64BIT 173345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Current maximum output size of 39 bits */ 173445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->s1_output_size = min(39UL, size); 173545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#else 173645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->s1_output_size = min(32UL, size); 173745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 173845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 173945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* The stage-2 output mask is also applied for bypass */ 174045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); 174145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size); 174245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 174345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version == 1) { 174445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->input_size = 32; 174545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 174645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef CONFIG_64BIT 174745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; 174845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = min(39, arm_smmu_id_size_to_bits(size)); 174945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#else 175045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = 32; 175145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 175245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->input_size = size; 175345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 175445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) || 175545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) || 175645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) { 175745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n", 175845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon PAGE_SIZE); 175945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 176045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 176145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 176245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 176345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, 176445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n", 176545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->input_size, smmu->s1_output_size, smmu->s2_output_size); 176645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 176745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 176845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 176945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_device_dt_probe(struct platform_device *pdev) 177045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 177145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct resource *res; 177245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu; 177345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device_node *dev_node; 177445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device *dev = &pdev->dev; 177545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_node *node; 177645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct of_phandle_args masterspec; 177745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int num_irqs, i, err; 177845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 177945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); 178045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu) { 178145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "failed to allocate arm_smmu_device\n"); 178245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 178345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 178445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->dev = dev; 178545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 178645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 17878a7f431221602fcde573dfdba26de1990ec195a0Julia Lawall smmu->base = devm_ioremap_resource(dev, res); 17888a7f431221602fcde573dfdba26de1990ec195a0Julia Lawall if (IS_ERR(smmu->base)) 17898a7f431221602fcde573dfdba26de1990ec195a0Julia Lawall return PTR_ERR(smmu->base); 179045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->size = resource_size(res); 179145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 179245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (of_property_read_u32(dev->of_node, "#global-interrupts", 179345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon &smmu->num_global_irqs)) { 179445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "missing #global-interrupts property\n"); 179545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 179645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 179745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 179845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon num_irqs = 0; 179945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { 180045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon num_irqs++; 180145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (num_irqs > smmu->num_global_irqs) 180245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_irqs++; 180345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 180445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 180544a08de2aaf7f4cf86dfcf04bee32536e4a2b5b8Andreas Herrmann if (!smmu->num_context_irqs) { 180644a08de2aaf7f4cf86dfcf04bee32536e4a2b5b8Andreas Herrmann dev_err(dev, "found %d interrupts but expected at least %d\n", 180744a08de2aaf7f4cf86dfcf04bee32536e4a2b5b8Andreas Herrmann num_irqs, smmu->num_global_irqs + 1); 180844a08de2aaf7f4cf86dfcf04bee32536e4a2b5b8Andreas Herrmann return -ENODEV; 180945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 181045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 181145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, 181245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon GFP_KERNEL); 181345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu->irqs) { 181445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "failed to allocate %d irqs\n", num_irqs); 181545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 181645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 181745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 181845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < num_irqs; ++i) { 181945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int irq = platform_get_irq(pdev, i); 182045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (irq < 0) { 182145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "failed to get irq index %d\n", i); 182245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 182345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 182445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->irqs[i] = irq; 182545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 182645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 182745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon i = 0; 182845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->masters = RB_ROOT; 182945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", 183045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "#stream-id-cells", i, 183145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon &masterspec)) { 183245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon err = register_smmu_master(smmu, dev, &masterspec); 183345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (err) { 183445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "failed to add master %s\n", 183545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon masterspec.np->name); 183645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_put_masters; 183745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 183845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 183945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon i++; 184045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 184145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(dev, "registered %d master devices\n", i); 184245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 184345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0))) 184445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->parent_of_node = dev_node; 184545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 184645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon err = arm_smmu_device_cfg_probe(smmu); 184745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (err) 184845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_put_parent; 184945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 185045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version > 1 && 185145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_banks != smmu->num_context_irqs) { 185245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, 185345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "found only %d context interrupt(s) but %d required\n", 185445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_irqs, smmu->num_context_banks); 185545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_put_parent; 185645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 185745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 185845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < smmu->num_global_irqs; ++i) { 185945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon err = request_irq(smmu->irqs[i], 186045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_global_fault, 186145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon IRQF_SHARED, 186245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "arm-smmu global fault", 186345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu); 186445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (err) { 186545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "failed to request global IRQ %d (%u)\n", 186645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon i, smmu->irqs[i]); 186745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_free_irqs; 186845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 186945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 187045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 187145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon INIT_LIST_HEAD(&smmu->list); 187245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&arm_smmu_devices_lock); 187345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_add(&smmu->list, &arm_smmu_devices); 187445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&arm_smmu_devices_lock); 1875fd90cecbde065eac6ecc3ef38abace725ad27010Will Deacon 1876fd90cecbde065eac6ecc3ef38abace725ad27010Will Deacon arm_smmu_device_reset(smmu); 187745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 187845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 187945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_free_irqs: 188045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (i--) 188145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon free_irq(smmu->irqs[i], smmu); 188245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 188345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_put_parent: 188445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->parent_of_node) 188545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon of_node_put(smmu->parent_of_node); 188645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 188745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_put_masters: 188845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { 188945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 189045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = container_of(node, struct arm_smmu_master, node); 189145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon of_node_put(master->of_node); 189245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 189345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 189445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return err; 189545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 189645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 189745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_device_remove(struct platform_device *pdev) 189845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 189945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 190045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device *dev = &pdev->dev; 190145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *curr, *smmu = NULL; 190245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_node *node; 190345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 190445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&arm_smmu_devices_lock); 190545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_for_each_entry(curr, &arm_smmu_devices, list) { 190645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (curr->dev == dev) { 190745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = curr; 190845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_del(&smmu->list); 190945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 191045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 191145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 191245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&arm_smmu_devices_lock); 191345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 191445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu) 191545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 191645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 191745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->parent_of_node) 191845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon of_node_put(smmu->parent_of_node); 191945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 192045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { 192145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 192245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = container_of(node, struct arm_smmu_master, node); 192345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon of_node_put(master->of_node); 192445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 192545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1926ecfadb6e5b49a0a56df2038bf39f1fcd652788b9Will Deacon if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) 192745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "removing device with active domains!\n"); 192845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 192945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < smmu->num_global_irqs; ++i) 193045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon free_irq(smmu->irqs[i], smmu); 193145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 193245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Turn the thing off */ 193325724841dfaed05f23a3ddaaaed5c9b61ceea7bdWill Deacon writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0); 193445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 193545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 193645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 193745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef CONFIG_OF 193845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic struct of_device_id arm_smmu_of_match[] = { 193945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon { .compatible = "arm,smmu-v1", }, 194045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon { .compatible = "arm,smmu-v2", }, 194145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon { .compatible = "arm,mmu-400", }, 194245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon { .compatible = "arm,mmu-500", }, 194345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon { }, 194445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 194545ae7cff3684ab45f57fc13fc242c8546536a84eWill DeaconMODULE_DEVICE_TABLE(of, arm_smmu_of_match); 194645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 194745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 194845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic struct platform_driver arm_smmu_driver = { 194945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .driver = { 195045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .owner = THIS_MODULE, 195145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .name = "arm-smmu", 195245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .of_match_table = of_match_ptr(arm_smmu_of_match), 195345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon }, 195445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .probe = arm_smmu_device_dt_probe, 195545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .remove = arm_smmu_device_remove, 195645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 195745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 195845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int __init arm_smmu_init(void) 195945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 196045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret; 196145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 196245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = platform_driver_register(&arm_smmu_driver); 196345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (ret) 196445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 196545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 196645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Oh, for a proper bus abstraction */ 19676614ee77f49d37f9bb77eb3e81431ca8fcc4042eDan Carpenter if (!iommu_present(&platform_bus_type)) 196845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon bus_set_iommu(&platform_bus_type, &arm_smmu_ops); 196945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 19706614ee77f49d37f9bb77eb3e81431ca8fcc4042eDan Carpenter if (!iommu_present(&amba_bustype)) 197145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon bus_set_iommu(&amba_bustype, &arm_smmu_ops); 197245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 197345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 197445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 197545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 197645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void __exit arm_smmu_exit(void) 197745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 197845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return platform_driver_unregister(&arm_smmu_driver); 197945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 198045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 1981b1950b2796da80b66df02db39cc3417266b73767Andreas Herrmannsubsys_initcall(arm_smmu_init); 198245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconmodule_exit(arm_smmu_exit); 198345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 198445ae7cff3684ab45f57fc13fc242c8546536a84eWill DeaconMODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); 198545ae7cff3684ab45f57fc13fc242c8546536a84eWill DeaconMODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); 198645ae7cff3684ab45f57fc13fc242c8546536a84eWill DeaconMODULE_LICENSE("GPL v2"); 1987