arm-smmu.c revision adaba320916d246af56821a1aab81a715091e7e5
145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* 245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * IOMMU API for ARM architected SMMU implementations. 345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * This program is free software; you can redistribute it and/or modify 545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * it under the terms of the GNU General Public License version 2 as 645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * published by the Free Software Foundation. 745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * This program is distributed in the hope that it will be useful, 945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * but WITHOUT ANY WARRANTY; without even the implied warranty of 1045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * GNU General Public License for more details. 1245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 1345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * You should have received a copy of the GNU General Public License 1445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * along with this program; if not, write to the Free Software 1545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 1645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 1745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Copyright (C) 2013 ARM Limited 1845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 1945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Author: Will Deacon <will.deacon@arm.com> 2045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 2145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * This driver currently supports: 2245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - SMMUv1 and v2 implementations 2345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - Stream-matching and stream-indexing 2445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - v7/v8 long-descriptor format 2545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - Non-secure access to the SMMU 2645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - 4k and 64k pages, with contiguous pte hints. 2745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - Up to 39-bit addressing 2845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - Context fault reporting 2945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 3045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 3145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define pr_fmt(fmt) "arm-smmu: " fmt 3245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 3345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/delay.h> 3445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/dma-mapping.h> 3545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/err.h> 3645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/interrupt.h> 3745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/io.h> 3845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/iommu.h> 3945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/mm.h> 4045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/module.h> 4145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/of.h> 4245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/platform_device.h> 4345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/slab.h> 4445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/spinlock.h> 4545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 4645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <linux/amba/bus.h> 4745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 4845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#include <asm/pgalloc.h> 4945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 5045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Maximum number of stream IDs assigned to a single device */ 5145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAX_MASTER_STREAMIDS 8 5245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 5345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Maximum number of context banks per SMMU */ 5445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_MAX_CBS 128 5545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 5645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Maximum number of mapping groups per SMMU */ 5745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_MAX_SMRS 128 5845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 5945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Number of VMIDs per SMMU */ 6045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_NUM_VMIDS 256 6145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 6245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* SMMU global address space */ 6345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0(smmu) ((smmu)->base) 6445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize) 6545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 6645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Page table bits */ 6745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0) 6845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52) 6945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_AF (((pteval_t)1) << 10) 7045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8) 7145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8) 7245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8) 7345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 7445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#if PAGE_SIZE == SZ_4K 7545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT_ENTRIES 16 7645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#elif PAGE_SIZE == SZ_64K 7745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT_ENTRIES 32 7845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#else 7945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT_ENTRIES 1 8045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 8145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 8245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES) 8345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1)) 8445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(pte_t)) 8545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 8645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Stage-1 PTE */ 8745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6) 8845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6) 8945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_ATTRINDX_SHIFT 2 9045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 9145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Stage-2 PTE */ 9245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6) 9345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6) 9445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6) 9545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2) 9645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2) 9745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2) 9845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 9945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Configuration registers */ 10045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sCR0 0x0 10145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_CLIENTPD (1 << 0) 10245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_GFRE (1 << 1) 10345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_GFIE (1 << 2) 10445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_GCFGFRE (1 << 4) 10545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_GCFGFIE (1 << 5) 10645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_USFCFG (1 << 10) 10745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_VMIDPNE (1 << 11) 10845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_PTM (1 << 12) 10945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_FB (1 << 13) 11045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_BSU_SHIFT 14 11145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sCR0_BSU_MASK 0x3 11245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 11345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Identification registers */ 11445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID0 0x20 11545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID1 0x24 11645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID2 0x28 11745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID3 0x2c 11845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID4 0x30 11945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID5 0x34 12045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID6 0x38 12145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_ID7 0x3c 12245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sGFSR 0x48 12345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sGFSYNR0 0x50 12445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sGFSYNR1 0x54 12545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sGFSYNR2 0x58 12645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_PIDR0 0xfe0 12745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_PIDR1 0xfe4 12845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_PIDR2 0xfe8 12945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 13045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_S1TS (1 << 30) 13145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_S2TS (1 << 29) 13245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_NTS (1 << 28) 13345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_SMS (1 << 27) 13445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_PTFS_SHIFT 24 13545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_PTFS_MASK 0x2 13645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_PTFS_V8_ONLY 0x2 13745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_CTTW (1 << 14) 13845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_NUMIRPT_SHIFT 16 13945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_NUMIRPT_MASK 0xff 14045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_NUMSMRG_SHIFT 0 14145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID0_NUMSMRG_MASK 0xff 14245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 14345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_PAGESIZE (1 << 31) 14445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMPAGENDXB_SHIFT 28 14545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMPAGENDXB_MASK 7 14645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMS2CB_SHIFT 16 14745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMS2CB_MASK 0xff 14845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMCB_SHIFT 0 14945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID1_NUMCB_MASK 0xff 15045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 15145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_OAS_SHIFT 4 15245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_OAS_MASK 0xf 15345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_IAS_SHIFT 0 15445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_IAS_MASK 0xf 15545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_UBS_SHIFT 8 15645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_UBS_MASK 0xf 15745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_PTFS_4K (1 << 12) 15845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_PTFS_16K (1 << 13) 15945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ID2_PTFS_64K (1 << 14) 16045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 16145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define PIDR2_ARCH_SHIFT 4 16245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define PIDR2_ARCH_MASK 0xf 16345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 16445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Global TLB invalidation */ 16545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_STLBIALL 0x60 16645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_TLBIVMID 0x64 16745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_TLBIALLNSNH 0x68 16845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_TLBIALLH 0x6c 16945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sTLBGSYNC 0x70 17045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_sTLBGSTATUS 0x74 17145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define sTLBGSTATUS_GSACTIVE (1 << 0) 17245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ 17345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 17445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Stream mapping registers */ 17545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) 17645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SMR_VALID (1 << 31) 17745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SMR_MASK_SHIFT 16 17845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SMR_MASK_MASK 0x7fff 17945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SMR_ID_SHIFT 0 18045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SMR_ID_MASK 0x7fff 18145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 18245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) 18345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_CBNDX_SHIFT 0 18445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_CBNDX_MASK 0xff 18545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_TYPE_SHIFT 16 18645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_TYPE_MASK 0x3 18745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) 18845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) 18945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) 19045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 19145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Context bank attribute registers */ 19245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) 19345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_VMID_SHIFT 0 19445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_VMID_MASK 0xff 19545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_S1_MEMATTR_SHIFT 12 19645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_S1_MEMATTR_MASK 0xf 19745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_S1_MEMATTR_WB 0xf 19845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_SHIFT 16 19945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_MASK 0x3 20045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) 20145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) 20245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) 20345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) 20445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_IRPTNDX_SHIFT 24 20545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBAR_IRPTNDX_MASK 0xff 20645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 20745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) 20845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBA2R_RW64_32BIT (0 << 0) 20945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define CBA2R_RW64_64BIT (1 << 0) 21045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 21145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Translation context bank */ 21245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) 21345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize) 21445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 21545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_SCTLR 0x0 21645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_RESUME 0x8 21745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_TTBCR2 0x10 21845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_TTBR0_LO 0x20 21945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_TTBR0_HI 0x24 22045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_TTBCR 0x30 22145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_S1_MAIR0 0x38 22245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_FSR 0x58 22345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_FAR_LO 0x60 22445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_FAR_HI 0x64 22545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_CB_FSYNR0 0x68 22645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 22745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_S1_ASIDPNE (1 << 12) 22845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_CFCFG (1 << 7) 22945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_CFIE (1 << 6) 23045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_CFRE (1 << 5) 23145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_E (1 << 4) 23245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_AFE (1 << 2) 23345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_TRE (1 << 1) 23445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_M (1 << 0) 23545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) 23645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 23745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define RESUME_RETRY (0 << 0) 23845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define RESUME_TERMINATE (1 << 0) 23945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 24045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_EAE (1 << 31) 24145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 24245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_PASIZE_SHIFT 16 24345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_PASIZE_MASK 0x7 24445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 24545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_TG0_4K (0 << 14) 24645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_TG0_64K (1 << 14) 24745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 24845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SH0_SHIFT 12 24945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SH0_MASK 0x3 25045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SH_NS 0 25145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SH_OS 2 25245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SH_IS 3 25345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 25445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_ORGN0_SHIFT 10 25545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_IRGN0_SHIFT 8 25645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_RGN_MASK 0x3 25745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_RGN_NC 0 25845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_RGN_WBWA 1 25945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_RGN_WT 2 26045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_RGN_WB 3 26145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 26245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SL0_SHIFT 6 26345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SL0_MASK 0x3 26445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SL0_LVL_2 0 26545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SL0_LVL_1 1 26645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 26745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_T1SZ_SHIFT 16 26845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_T0SZ_SHIFT 0 26945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR_SZ_MASK 0xf 27045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 27145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_SEP_SHIFT 15 27245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_SEP_MASK 0x7 27345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 27445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_PASIZE_SHIFT 0 27545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_PASIZE_MASK 0x7 27645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 27745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Common definitions for PASize and SEP fields */ 27845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_32 0 27945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_36 1 28045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_40 2 28145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_42 3 28245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_44 4 28345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define TTBCR2_ADDR_48 5 28445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 28545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_SHIFT(n) ((n) << 3) 28645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_MASK 0xff 28745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_DEVICE 0x04 28845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_NC 0x44 28945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_WBRWA 0xff 29045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_IDX_NC 0 29145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_IDX_CACHE 1 29245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define MAIR_ATTR_IDX_DEV 2 29345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 29445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_MULTI (1 << 31) 29545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_SS (1 << 30) 29645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_UUT (1 << 8) 29745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_ASF (1 << 7) 29845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_TLBLKF (1 << 6) 29945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_TLBMCF (1 << 5) 30045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_EF (1 << 4) 30145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_PF (1 << 3) 30245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_AFF (1 << 2) 30345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_TF (1 << 1) 30445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 30545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_IGN (FSR_AFF | FSR_ASF | FSR_TLBMCF | \ 30645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon FSR_TLBLKF) 30745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ 308adaba320916d246af56821a1aab81a715091e7e5Will Deacon FSR_EF | FSR_PF | FSR_TF | FSR_IGN) 30945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 31045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define FSYNR0_WNR (1 << 4) 31145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 31245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstruct arm_smmu_smr { 31345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u8 idx; 31445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u16 mask; 31545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u16 id; 31645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 31745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 31845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstruct arm_smmu_master { 31945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device_node *of_node; 32045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 32145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 32245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * The following is specific to the master's position in the 32345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * SMMU chain. 32445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 32545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_node node; 32645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int num_streamids; 32745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u16 streamids[MAX_MASTER_STREAMIDS]; 32845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 32945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 33045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We only need to allocate these on the root SMMU, as we 33145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * configure unmatched streams to bypass translation. 33245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 33345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_smr *smrs; 33445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 33545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 33645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstruct arm_smmu_device { 33745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device *dev; 33845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device_node *parent_of_node; 33945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 34045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *base; 34145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long size; 34245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long pagesize; 34345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 34445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) 34545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) 34645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) 34745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) 34845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) 34945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 features; 35045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int version; 35145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 35245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 num_context_banks; 35345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 num_s2_context_banks; 35445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); 35545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon atomic_t irptndx; 35645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 35745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 num_mapping_groups; 35845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); 35945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 36045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long input_size; 36145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long s1_output_size; 36245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long s2_output_size; 36345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 36445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 num_global_irqs; 36545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 num_context_irqs; 36645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned int *irqs; 36745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 36845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon DECLARE_BITMAP(vmid_map, ARM_SMMU_NUM_VMIDS); 36945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 37045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct list_head list; 37145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_root masters; 37245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 37345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 37445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstruct arm_smmu_cfg { 37545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu; 37645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u8 vmid; 37745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u8 cbndx; 37845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u8 irptndx; 37945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 cbar; 38045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_t *pgd; 38145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 38245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 38345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstruct arm_smmu_domain { 38445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 38545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * A domain can span across multiple, chained SMMUs and requires 38645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * all devices within the domain to follow the same translation 38745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * path. 38845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 38945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *leaf_smmu; 39045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg root_cfg; 39145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys_addr_t output_mask; 39245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 39345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spinlock_t lock; 39445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 39545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 39645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic DEFINE_SPINLOCK(arm_smmu_devices_lock); 39745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic LIST_HEAD(arm_smmu_devices); 39845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 39945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, 40045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device_node *dev_node) 40145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 40245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_node *node = smmu->masters.rb_node; 40345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 40445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (node) { 40545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 40645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = container_of(node, struct arm_smmu_master, node); 40745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 40845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (dev_node < master->of_node) 40945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon node = node->rb_left; 41045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else if (dev_node > master->of_node) 41145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon node = node->rb_right; 41245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else 41345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return master; 41445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 41545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 41645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return NULL; 41745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 41845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 41945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int insert_smmu_master(struct arm_smmu_device *smmu, 42045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 42145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 42245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_node **new, *parent; 42345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 42445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon new = &smmu->masters.rb_node; 42545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon parent = NULL; 42645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (*new) { 42745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *this; 42845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon this = container_of(*new, struct arm_smmu_master, node); 42945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 43045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon parent = *new; 43145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master->of_node < this->of_node) 43245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon new = &((*new)->rb_left); 43345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else if (master->of_node > this->of_node) 43445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon new = &((*new)->rb_right); 43545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else 43645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EEXIST; 43745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 43845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 43945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon rb_link_node(&master->node, parent, new); 44045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon rb_insert_color(&master->node, &smmu->masters); 44145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 44245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 44345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 44445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int register_smmu_master(struct arm_smmu_device *smmu, 44545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device *dev, 44645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct of_phandle_args *masterspec) 44745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 44845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 44945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 45045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 45145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = find_smmu_master(smmu, masterspec->np); 45245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master) { 45345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, 45445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "rejecting multiple registrations for master device %s\n", 45545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon masterspec->np->name); 45645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EBUSY; 45745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 45845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 45945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (masterspec->args_count > MAX_MASTER_STREAMIDS) { 46045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, 46145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "reached maximum number (%d) of stream IDs for master device %s\n", 46245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon MAX_MASTER_STREAMIDS, masterspec->np->name); 46345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOSPC; 46445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 46545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 46645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); 46745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!master) 46845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 46945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 47045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->of_node = masterspec->np; 47145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->num_streamids = masterspec->args_count; 47245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 47345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) 47445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->streamids[i] = masterspec->args[i]; 47545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 47645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return insert_smmu_master(smmu, master); 47745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 47845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 47945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu) 48045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 48145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *parent; 48245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 48345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu->parent_of_node) 48445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return NULL; 48545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 48645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&arm_smmu_devices_lock); 48745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_for_each_entry(parent, &arm_smmu_devices, list) 48845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (parent->dev->of_node == smmu->parent_of_node) 48945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_unlock; 49045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 49145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon parent = NULL; 49245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_warn(smmu->dev, 49345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "Failed to find SMMU parent despite parent in DT\n"); 49445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_unlock: 49545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&arm_smmu_devices_lock); 49645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return parent; 49745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 49845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 49945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) 50045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 50145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int idx; 50245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 50345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 50445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon idx = find_next_zero_bit(map, end, start); 50545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (idx == end) 50645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOSPC; 50745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (test_and_set_bit(idx, map)); 50845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 50945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return idx; 51045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 51145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 51245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void __arm_smmu_free_bitmap(unsigned long *map, int idx) 51345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 51445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon clear_bit(idx, map); 51545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 51645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 51745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon/* Wait for any pending TLB invalidations to complete */ 51845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_tlb_sync(struct arm_smmu_device *smmu) 51945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 52045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int count = 0; 52145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 52245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 52345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); 52445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) 52545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon & sTLBGSTATUS_GSACTIVE) { 52645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon cpu_relax(); 52745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (++count == TLB_LOOP_TIMEOUT) { 52845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err_ratelimited(smmu->dev, 52945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "TLB sync timed out -- SMMU may be deadlocked\n"); 53045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return; 53145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 53245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon udelay(1); 53345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 53445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 53545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 53645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic irqreturn_t arm_smmu_context_fault(int irq, void *dev) 53745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 53845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int flags, ret; 53945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 fsr, far, fsynr, resume; 54045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long iova; 54145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct iommu_domain *domain = dev; 54245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 54345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 54445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = root_cfg->smmu; 54545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *cb_base; 54645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 54745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx); 54845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); 54945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 55045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(fsr & FSR_FAULT)) 55145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return IRQ_NONE; 55245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 55345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (fsr & FSR_IGN) 55445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err_ratelimited(smmu->dev, 55545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "Unexpected context fault (fsr 0x%u)\n", 55645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon fsr); 55745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 55845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); 55945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; 56045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 56145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); 56245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon iova = far; 56345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef CONFIG_64BIT 56445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); 56545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon iova |= ((unsigned long)far << 32); 56645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 56745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 56845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { 56945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = IRQ_HANDLED; 57045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon resume = RESUME_RETRY; 57145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 57245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = IRQ_NONE; 57345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon resume = RESUME_TERMINATE; 57445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 57545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 57645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Clear the faulting FSR */ 57745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel(fsr, cb_base + ARM_SMMU_CB_FSR); 57845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 57945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Retry or terminate any stalled transactions */ 58045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (fsr & FSR_SS) 58145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); 58245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 58345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 58445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 58545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 58645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic irqreturn_t arm_smmu_global_fault(int irq, void *dev) 58745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 58845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 gfsr, gfsynr0, gfsynr1, gfsynr2; 58945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = dev; 59045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 59145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 59245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); 593adaba320916d246af56821a1aab81a715091e7e5Will Deacon if (!gfsr) 594adaba320916d246af56821a1aab81a715091e7e5Will Deacon return IRQ_NONE; 595adaba320916d246af56821a1aab81a715091e7e5Will Deacon 59645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); 59745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); 59845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); 59945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 60045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err_ratelimited(smmu->dev, 60145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "Unexpected global fault, this could be serious\n"); 60245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err_ratelimited(smmu->dev, 60345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", 60445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gfsr, gfsynr0, gfsynr1, gfsynr2); 60545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 60645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); 607adaba320916d246af56821a1aab81a715091e7e5Will Deacon return IRQ_HANDLED; 60845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 60945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 61045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) 61145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 61245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 reg; 61345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon bool stage1; 61445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 61545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = root_cfg->smmu; 61645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *cb_base, *gr0_base, *gr1_base; 61745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 61845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gr0_base = ARM_SMMU_GR0(smmu); 61945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gr1_base = ARM_SMMU_GR1(smmu); 62045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS; 62145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx); 62245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 62345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* CBAR */ 62445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = root_cfg->cbar | 62545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (root_cfg->vmid << CBAR_VMID_SHIFT); 62645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version == 1) 62745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT; 62845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 62945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Use the weakest memory type, so it is overridden by the pte */ 63045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (stage1) 63145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); 63245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(root_cfg->cbndx)); 63345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 63445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version > 1) { 63545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* CBA2R */ 63645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef CONFIG_64BIT 63745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = CBA2R_RW64_64BIT; 63845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#else 63945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = CBA2R_RW64_32BIT; 64045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 64145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, 64245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gr1_base + ARM_SMMU_GR1_CBA2R(root_cfg->cbndx)); 64345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 64445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* TTBCR2 */ 64545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon switch (smmu->input_size) { 64645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 32: 64745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); 64845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 64945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 36: 65045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); 65145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 65245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 39: 65345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); 65445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 65545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 42: 65645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); 65745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 65845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 44: 65945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); 66045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 66145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 48: 66245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); 66345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 66445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 66545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 66645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon switch (smmu->s1_output_size) { 66745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 32: 66845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT); 66945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 67045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 36: 67145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT); 67245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 67345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 39: 67445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT); 67545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 67645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 42: 67745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT); 67845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 67945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 44: 68045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT); 68145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 68245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 48: 68345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT); 68445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 68545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 68645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 68745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (stage1) 68845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); 68945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 69045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 69145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* TTBR0 */ 69245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = __pa(root_cfg->pgd); 69345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); 69445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (phys_addr_t)__pa(root_cfg->pgd) >> 32; 69545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); 69645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 69745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 69845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * TTBCR 69945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We use long descriptor, with inner-shareable WBWA tables in TTBR0. 70045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 70145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version > 1) { 70245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (PAGE_SIZE == SZ_4K) 70345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = TTBCR_TG0_4K; 70445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else 70545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = TTBCR_TG0_64K; 70645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 70745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!stage1) { 70845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon switch (smmu->s2_output_size) { 70945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 32: 71045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT); 71145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 71245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 36: 71345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT); 71445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 71545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 40: 71645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT); 71745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 71845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 42: 71945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT); 72045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 72145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 44: 72245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT); 72345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 72445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 48: 72545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); 72645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 72745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 72845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 72945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT; 73045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 73145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 73245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = 0; 73345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 73445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 73545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= TTBCR_EAE | 73645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | 73745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | 73845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) | 73945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); 74045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); 74145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 74245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* MAIR0 (stage-1 only) */ 74345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (stage1) { 74445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) | 74545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) | 74645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV)); 74745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); 74845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 74945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 75045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Nuke the TLB */ 75145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(root_cfg->vmid, gr0_base + ARM_SMMU_GR0_TLBIVMID); 75245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_tlb_sync(smmu); 75345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 75445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* SCTLR */ 75545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; 75645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (stage1) 75745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= SCTLR_S1_ASIDPNE; 75845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef __BIG_ENDIAN 75945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon reg |= SCTLR_E; 76045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 76145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel(reg, cb_base + ARM_SMMU_CB_SCTLR); 76245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 76345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 76445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_init_domain_context(struct iommu_domain *domain, 76545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device *dev) 76645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 76745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int irq, ret, start; 76845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 76945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 77045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu, *parent; 77145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 77245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 77345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Walk the SMMU chain to find the root device for this chain. 77445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We assume that no masters have translations which terminate 77545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * early, and therefore check that the root SMMU does indeed have 77645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * a StreamID for the master in question. 77745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 77845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon parent = dev->archdata.iommu; 77945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu_domain->output_mask = -1; 78045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 78145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = parent; 78245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu_domain->output_mask &= (1ULL << smmu->s2_output_size) - 1; 78345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while ((parent = find_parent_smmu(smmu))); 78445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 78545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!find_smmu_master(smmu, dev->of_node)) { 78645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "unable to find root SMMU for device\n"); 78745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 78845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 78945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 79045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = __arm_smmu_alloc_bitmap(smmu->vmid_map, 0, ARM_SMMU_NUM_VMIDS); 79145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (IS_ERR_VALUE(ret)) 79245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 79345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 79445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->vmid = ret; 79545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { 79645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 79745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We will likely want to change this if/when KVM gets 79845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * involved. 79945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 80045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; 80145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon start = smmu->num_s2_context_banks; 80245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) { 80345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->cbar = CBAR_TYPE_S2_TRANS; 80445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon start = 0; 80545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 80645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; 80745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon start = smmu->num_s2_context_banks; 80845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 80945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 81045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, 81145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_banks); 81245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (IS_ERR_VALUE(ret)) 81345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_free_vmid; 81445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 81545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->cbndx = ret; 81645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 81745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version == 1) { 81845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->irptndx = atomic_inc_return(&smmu->irptndx); 81945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->irptndx %= smmu->num_context_irqs; 82045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 82145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->irptndx = root_cfg->cbndx; 82245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 82345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 82445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx]; 82545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, 82645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "arm-smmu-context-fault", domain); 82745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (IS_ERR_VALUE(ret)) { 82845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", 82945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->irptndx, irq); 83045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->irptndx = -1; 83145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_free_context; 83245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 83345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 83445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon root_cfg->smmu = smmu; 83545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_init_context_bank(smmu_domain); 83645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 83745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 83845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_free_context: 83945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx); 84045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_free_vmid: 84145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __arm_smmu_free_bitmap(smmu->vmid_map, root_cfg->vmid); 84245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 84345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 84445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 84545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_destroy_domain_context(struct iommu_domain *domain) 84645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 84745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 84845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 84945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = root_cfg->smmu; 85045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int irq; 85145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 85245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu) 85345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return; 85445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 85545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (root_cfg->irptndx != -1) { 85645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx]; 85745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon free_irq(irq, domain); 85845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 85945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 86045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __arm_smmu_free_bitmap(smmu->vmid_map, root_cfg->vmid); 86145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx); 86245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 86345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 86445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_domain_init(struct iommu_domain *domain) 86545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 86645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain; 86745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_t *pgd; 86845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 86945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 87045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Allocate the domain and initialise some of its data structures. 87145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We can't really do anything meaningful until we've added a 87245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * master. 87345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 87445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); 87545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu_domain) 87645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 87745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 87845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL); 87945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!pgd) 88045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_free_domain; 88145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu_domain->root_cfg.pgd = pgd; 88245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 88345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock_init(&smmu_domain->lock); 88445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon domain->priv = smmu_domain; 88545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 88645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 88745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_free_domain: 88845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon kfree(smmu_domain); 88945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 89045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 89145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 89245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_free_ptes(pmd_t *pmd) 89345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 89445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgtable_t table = pmd_pgtable(*pmd); 89545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgtable_page_dtor(table); 89645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __free_page(table); 89745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 89845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 89945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_free_pmds(pud_t *pud) 90045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 90145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 90245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd_t *pmd, *pmd_base = pmd_offset(pud, 0); 90345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 90445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd = pmd_base; 90545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < PTRS_PER_PMD; ++i) { 90645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pmd_none(*pmd)) 90745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon continue; 90845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 90945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_free_ptes(pmd); 91045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd++; 91145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 91245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 91345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd_free(NULL, pmd_base); 91445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 91545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 91645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_free_puds(pgd_t *pgd) 91745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 91845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 91945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud_t *pud, *pud_base = pud_offset(pgd, 0); 92045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 92145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud = pud_base; 92245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < PTRS_PER_PUD; ++i) { 92345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pud_none(*pud)) 92445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon continue; 92545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 92645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_free_pmds(pud); 92745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud++; 92845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 92945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 93045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud_free(NULL, pud_base); 93145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 93245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 93345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain) 93445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 93545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 93645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 93745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_t *pgd, *pgd_base = root_cfg->pgd; 93845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 93945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 94045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Recursively free the page tables for this domain. We don't 94145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * care about speculative TLB filling, because the TLB will be 94245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * nuked next time this context bank is re-allocated and no devices 94345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * currently map to these tables. 94445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 94545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd = pgd_base; 94645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < PTRS_PER_PGD; ++i) { 94745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pgd_none(*pgd)) 94845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon continue; 94945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_free_puds(pgd); 95045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd++; 95145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 95245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 95345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon kfree(pgd_base); 95445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 95545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 95645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_domain_destroy(struct iommu_domain *domain) 95745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 95845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 95945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_destroy_domain_context(domain); 96045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_free_pgtables(smmu_domain); 96145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon kfree(smmu_domain); 96245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 96345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 96445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, 96545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 96645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 96745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 96845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_smr *smrs; 96945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 97045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 97145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) 97245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 97345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 97445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master->smrs) 97545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EEXIST; 97645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 97745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL); 97845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smrs) { 97945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n", 98045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->num_streamids, master->of_node->name); 98145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 98245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 98345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 98445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Allocate the SMRs on the root SMMU */ 98545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) { 98645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, 98745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_mapping_groups); 98845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (IS_ERR_VALUE(idx)) { 98945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "failed to allocate free SMR\n"); 99045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_free_smrs; 99145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 99245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 99345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smrs[i] = (struct arm_smmu_smr) { 99445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .idx = idx, 99545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .mask = 0, /* We don't currently share SMRs */ 99645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .id = master->streamids[i], 99745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon }; 99845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 99945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 100045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* It worked! Now, poke the actual hardware */ 100145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) { 100245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | 100345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smrs[i].mask << SMR_MASK_SHIFT; 100445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); 100545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 100645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 100745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->smrs = smrs; 100845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 100945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 101045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconerr_free_smrs: 101145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (--i >= 0) 101245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); 101345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon kfree(smrs); 101445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOSPC; 101545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 101645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 101745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, 101845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 101945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 102045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 102145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 102245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_smr *smrs = master->smrs; 102345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 102445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Invalidate the SMRs before freeing back to the allocator */ 102545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) { 102645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u8 idx = smrs[i].idx; 102745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); 102845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon __arm_smmu_free_bitmap(smmu->smr_map, idx); 102945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 103045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 103145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master->smrs = NULL; 103245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon kfree(smrs); 103345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 103445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 103545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu, 103645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 103745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 103845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 103945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 104045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 104145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) { 104245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u16 sid = master->streamids[i]; 104345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(S2CR_TYPE_BYPASS, 104445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon gr0_base + ARM_SMMU_GR0_S2CR(sid)); 104545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 104645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 104745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 104845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, 104945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 105045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 105145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i, ret; 105245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *parent, *smmu = smmu_domain->root_cfg.smmu; 105345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 105445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 105545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_master_configure_smrs(smmu, master); 105645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (ret) 105745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 105845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 105945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Bypass the leaves */ 106045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = smmu_domain->leaf_smmu; 106145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while ((parent = find_parent_smmu(smmu))) { 106245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 106345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We won't have a StreamID match for anything but the root 106445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * smmu, so we only need to worry about StreamID indexing, 106545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * where we must install bypass entries in the S2CRs. 106645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 106745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) 106845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon continue; 106945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 107045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_bypass_stream_mapping(smmu, master); 107145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = parent; 107245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 107345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 107445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Now we're at the root, time to point at our context bank */ 107545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < master->num_streamids; ++i) { 107645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 idx, s2cr; 107745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon idx = master->smrs ? master->smrs[i].idx : master->streamids[i]; 107845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon s2cr = (S2CR_TYPE_TRANS << S2CR_TYPE_SHIFT) | 107945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT); 108045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); 108145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 108245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 108345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 108445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 108545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 108645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, 108745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master) 108845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 108945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = smmu_domain->root_cfg.smmu; 109045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 109145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 109245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * We *must* clear the S2CR first, because freeing the SMR means 109345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * that it can be re-allocated immediately. 109445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 109545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_bypass_stream_mapping(smmu, master); 109645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_master_free_smrs(smmu, master); 109745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 109845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 109945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) 110045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 110145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret = -EINVAL; 110245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 110345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *device_smmu = dev->archdata.iommu; 110445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 110545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 110645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!device_smmu) { 110745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); 110845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENXIO; 110945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 111045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 111145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 111245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Sanity check the domain. We don't currently support domains 111345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * that cross between different SMMU chains. 111445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 111545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&smmu_domain->lock); 111645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu_domain->leaf_smmu) { 111745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Now that we have a master, we can finalise the domain */ 111845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_init_domain_context(domain, dev); 111945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (IS_ERR_VALUE(ret)) 112045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_unlock; 112145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 112245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu_domain->leaf_smmu = device_smmu; 112345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else if (smmu_domain->leaf_smmu != device_smmu) { 112445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, 112545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", 112645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_name(smmu_domain->leaf_smmu->dev), 112745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_name(device_smmu->dev)); 112845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_unlock; 112945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 113045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&smmu_domain->lock); 113145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 113245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Looks ok, so add the device to the domain */ 113345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node); 113445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!master) 113545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 113645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 113745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return arm_smmu_domain_add_master(smmu_domain, master); 113845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 113945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconerr_unlock: 114045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&smmu_domain->lock); 114145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 114245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 114345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 114445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) 114545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 114645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 114745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 114845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 114945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node); 115045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master) 115145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_domain_remove_master(smmu_domain, master); 115245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 115345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 115445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, 115545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size_t size) 115645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 115745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long offset = (unsigned long)addr & ~PAGE_MASK; 115845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 115945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 116045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * If the SMMU can't walk tables in the CPU caches, treat them 116145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * like non-coherent DMA since we need to flush the new entries 116245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * all the way out to memory. There's no possibility of recursion 116345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * here as the SMMU table walker will not be wired through another 116445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * SMMU. 116545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 116645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)) 116745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dma_map_page(smmu->dev, virt_to_page(addr), offset, size, 116845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon DMA_TO_DEVICE); 116945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 117045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 117145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic bool arm_smmu_pte_is_contiguous_range(unsigned long addr, 117245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long end) 117345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 117445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return !(addr & ~ARM_SMMU_PTE_CONT_MASK) && 117545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (addr + ARM_SMMU_PTE_CONT_SIZE <= end); 117645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 117745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 117845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, 117945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long addr, unsigned long end, 118045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long pfn, int flags, int stage) 118145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 118245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pte_t *pte, *start; 118345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF; 118445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 118545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pmd_none(*pmd)) { 118645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Allocate a new set of tables */ 118745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgtable_t table = alloc_page(PGALLOC_GFP); 118845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!table) 118945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 119045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 119145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, page_address(table), 119245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ARM_SMMU_PTE_HWTABLE_SIZE); 119345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgtable_page_ctor(table); 119445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd_populate(NULL, pmd, table); 119545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd)); 119645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 119745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 119845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (stage == 1) { 119945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_AP_UNPRIV; 120045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ)) 120145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_AP_RDONLY; 120245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 120345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (flags & IOMMU_CACHE) 120445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= (MAIR_ATTR_IDX_CACHE << 120545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ARM_SMMU_PTE_ATTRINDX_SHIFT); 120645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 120745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_HAP_FAULT; 120845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (flags & IOMMU_READ) 120945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_HAP_READ; 121045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (flags & IOMMU_WRITE) 121145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_HAP_WRITE; 121245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (flags & IOMMU_CACHE) 121345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_MEMATTR_OIWB; 121445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon else 121545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_MEMATTR_NC; 121645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 121745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 121845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* If no access, create a faulting entry to avoid TLB fills */ 121945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(flags & (IOMMU_READ | IOMMU_WRITE))) 122045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval &= ~ARM_SMMU_PTE_PAGE; 122145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 122245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_SH_IS; 122345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon start = pmd_page_vaddr(*pmd) + pte_index(addr); 122445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pte = start; 122545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 122645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 122745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Install the page table entries. This is fairly complicated 122845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * since we attempt to make use of the contiguous hint in the 122945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * ptes where possible. The contiguous hint indicates a series 123045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically 123145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * contiguous region with the following constraints: 123245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 123345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE 123445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * - Each pte in the region has the contiguous hint bit set 123545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 123645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * This complicates unmapping (also handled by this code, when 123745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * neither IOMMU_READ or IOMMU_WRITE are set) because it is 123845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * possible, yet highly unlikely, that a client may unmap only 123945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * part of a contiguous range. This requires clearing of the 124045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * contiguous hint bits in the range before installing the new 124145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * faulting entries. 124245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * 124345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Note that re-mapping an address range without first unmapping 124445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * it is not supported, so TLB invalidation is not required here 124545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * and is instead performed at unmap and domain-init time. 124645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 124745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 124845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i = 1; 124945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval &= ~ARM_SMMU_PTE_CONT; 125045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 125145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (arm_smmu_pte_is_contiguous_range(addr, end)) { 125245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon i = ARM_SMMU_PTE_CONT_ENTRIES; 125345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pteval |= ARM_SMMU_PTE_CONT; 125445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else if (pte_val(*pte) & 125545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) { 125645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int j; 125745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pte_t *cont_start; 125845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long idx = pte_index(addr); 125945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 126045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1); 126145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon cont_start = pmd_page_vaddr(*pmd) + idx; 126245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j) 126345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT; 126445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 126545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, cont_start, 126645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon sizeof(*pte) * 126745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ARM_SMMU_PTE_CONT_ENTRIES); 126845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 126945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 127045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 127145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon *pte = pfn_pte(pfn, __pgprot(pteval)); 127245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (pte++, pfn++, addr += PAGE_SIZE, --i); 127345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (addr != end); 127445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 127545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start)); 127645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 127745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 127845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 127945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud, 128045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long addr, unsigned long end, 128145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys_addr_t phys, int flags, int stage) 128245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 128345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret; 128445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd_t *pmd; 128545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long next, pfn = __phys_to_pfn(phys); 128645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 128745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifndef __PAGETABLE_PMD_FOLDED 128845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pud_none(*pud)) { 128945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd = pmd_alloc_one(NULL, addr); 129045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!pmd) 129145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 129245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else 129345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 129445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd = pmd_offset(pud, addr); 129545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 129645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 129745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon next = pmd_addr_end(addr, end); 129845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn, 129945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon flags, stage); 130045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud_populate(NULL, pud, pmd); 130145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud)); 130245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys += next - addr; 130345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (pmd++, addr = next, addr < end); 130445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 130545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 130645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 130745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 130845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd, 130945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long addr, unsigned long end, 131045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys_addr_t phys, int flags, int stage) 131145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 131245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret = 0; 131345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud_t *pud; 131445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long next; 131545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 131645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifndef __PAGETABLE_PUD_FOLDED 131745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pgd_none(*pgd)) { 131845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud = pud_alloc_one(NULL, addr); 131945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!pud) 132045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 132145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else 132245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 132345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud = pud_offset(pgd, addr); 132445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 132545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 132645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon next = pud_addr_end(addr, end); 132745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys, 132845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon flags, stage); 132945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_populate(NULL, pud, pgd); 133045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd)); 133145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys += next - addr; 133245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (pud++, addr = next, addr < end); 133345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 133445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 133545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 133645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 133745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain, 133845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long iova, phys_addr_t paddr, 133945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size_t size, int flags) 134045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 134145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret, stage; 134245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long end; 134345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys_addr_t input_mask, output_mask; 134445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 134545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_t *pgd = root_cfg->pgd; 134645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = root_cfg->smmu; 134745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 134845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) { 134945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon stage = 2; 135045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon output_mask = (1ULL << smmu->s2_output_size) - 1; 135145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 135245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon stage = 1; 135345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon output_mask = (1ULL << smmu->s1_output_size) - 1; 135445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 135545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 135645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!pgd) 135745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EINVAL; 135845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 135945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (size & ~PAGE_MASK) 136045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EINVAL; 136145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 136245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon input_mask = (1ULL << smmu->input_size) - 1; 136345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if ((phys_addr_t)iova & ~input_mask) 136445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ERANGE; 136545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 136645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (paddr & ~output_mask) 136745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ERANGE; 136845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 136945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&smmu_domain->lock); 137045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd += pgd_index(iova); 137145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon end = iova + size; 137245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon do { 137345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long next = pgd_addr_end(iova, end); 137445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 137545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr, 137645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon flags, stage); 137745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (ret) 137845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_unlock; 137945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 138045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon paddr += next - iova; 138145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon iova = next; 138245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } while (pgd++, iova != end); 138345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 138445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_unlock: 138545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&smmu_domain->lock); 138645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 138745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Ensure new page tables are visible to the hardware walker */ 138845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) 138945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dsb(); 139045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 139145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 139245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 139345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 139445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, 139545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon phys_addr_t paddr, size_t size, int flags) 139645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 139745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 139845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = smmu_domain->leaf_smmu; 139945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 140045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu_domain || !smmu) 140145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 140245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 140345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Check for silent address truncation up the SMMU chain. */ 140445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if ((phys_addr_t)iova & ~smmu_domain->output_mask) 140545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ERANGE; 140645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 140745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags); 140845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 140945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 141045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, 141145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size_t size) 141245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 141345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret; 141445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 141545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 141645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = root_cfg->smmu; 141745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 141845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 141945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0); 142045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(root_cfg->vmid, gr0_base + ARM_SMMU_GR0_TLBIVMID); 142145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_tlb_sync(smmu); 142245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret ? ret : size; 142345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 142445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 142545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, 142645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dma_addr_t iova) 142745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 142845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd_t *pgd; 142945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud_t *pud; 143045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd_t *pmd; 143145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pte_t *pte; 143245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 143345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 143445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu = root_cfg->smmu; 143545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 143645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&smmu_domain->lock); 143745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd = root_cfg->pgd; 143845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!pgd) 143945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_unlock; 144045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 144145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pgd += pgd_index(iova); 144245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pgd_none_or_clear_bad(pgd)) 144345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_unlock; 144445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 144545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pud = pud_offset(pgd, iova); 144645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pud_none_or_clear_bad(pud)) 144745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_unlock; 144845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 144945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pmd = pmd_offset(pud, iova); 145045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pmd_none_or_clear_bad(pmd)) 145145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_unlock; 145245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 145345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon pte = pmd_page_vaddr(*pmd) + pte_index(iova); 145445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (pte_none(pte)) 145545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto err_unlock; 145645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 145745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&smmu_domain->lock); 145845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return __pfn_to_phys(pte_pfn(*pte)) | (iova & ~PAGE_MASK); 145945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 146045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconerr_unlock: 146145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&smmu_domain->lock); 146245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_warn(smmu->dev, 146345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "invalid (corrupt?) page tables detected for iova 0x%llx\n", 146445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (unsigned long long)iova); 146545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EINVAL; 146645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 146745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 146845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_domain_has_cap(struct iommu_domain *domain, 146945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long cap) 147045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 147145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long caps = 0; 147245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_domain *smmu_domain = domain->priv; 147345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 147445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) 147545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon caps |= IOMMU_CAP_CACHE_COHERENCY; 147645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 147745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return !!(cap & caps); 147845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 147945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 148045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_add_device(struct device *dev) 148145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 148245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *child, *parent, *smmu; 148345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master = NULL; 148445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 148545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&arm_smmu_devices_lock); 148645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_for_each_entry(parent, &arm_smmu_devices, list) { 148745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = parent; 148845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 148945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Try to find a child of the current SMMU. */ 149045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_for_each_entry(child, &arm_smmu_devices, list) { 149145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (child->parent_of_node == parent->dev->of_node) { 149245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Does the child sit above our master? */ 149345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = find_smmu_master(child, dev->of_node); 149445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master) { 149545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = NULL; 149645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 149745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 149845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 149945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 150045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 150145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* We found some children, so keep searching. */ 150245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu) { 150345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = NULL; 150445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon continue; 150545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 150645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 150745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = find_smmu_master(smmu, dev->of_node); 150845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (master) 150945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 151045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 151145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&arm_smmu_devices_lock); 151245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 151345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!master) 151445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 151545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 151645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev->archdata.iommu = smmu; 151745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 151845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 151945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 152045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_remove_device(struct device *dev) 152145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 152245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev->archdata.iommu = NULL; 152345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 152445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 152545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic struct iommu_ops arm_smmu_ops = { 152645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .domain_init = arm_smmu_domain_init, 152745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .domain_destroy = arm_smmu_domain_destroy, 152845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .attach_dev = arm_smmu_attach_dev, 152945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .detach_dev = arm_smmu_detach_dev, 153045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .map = arm_smmu_map, 153145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .unmap = arm_smmu_unmap, 153245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .iova_to_phys = arm_smmu_iova_to_phys, 153345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .domain_has_cap = arm_smmu_domain_has_cap, 153445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .add_device = arm_smmu_add_device, 153545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .remove_device = arm_smmu_remove_device, 153645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .pgsize_bitmap = (SECTION_SIZE | 153745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ARM_SMMU_PTE_CONT_SIZE | 153845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon PAGE_SIZE), 153945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 154045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 154145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void arm_smmu_device_reset(struct arm_smmu_device *smmu) 154245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 154345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 154445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i = 0; 154545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 scr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0); 154645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 154745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Mark all SMRn as invalid and all S2CRn as bypass */ 154845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < smmu->num_mapping_groups; ++i) { 154945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i)); 155045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i)); 155145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 155245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 155345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Invalidate the TLB, just in case */ 155445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL); 155545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); 155645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); 155745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 155845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Enable fault reporting */ 155945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon scr0 |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); 156045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 156145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Disable TLB broadcasting. */ 156245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon scr0 |= (sCR0_VMIDPNE | sCR0_PTM); 156345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 156445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Enable client access, but bypass when no mapping is found */ 156545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon scr0 &= ~(sCR0_CLIENTPD | sCR0_USFCFG); 156645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 156745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Disable forced broadcasting */ 156845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon scr0 &= ~sCR0_FB; 156945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 157045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Don't upgrade barriers */ 157145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon scr0 &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); 157245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 157345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Push the button */ 157445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_tlb_sync(smmu); 157545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel(scr0, gr0_base + ARM_SMMU_GR0_sCR0); 157645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 157745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 157845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_id_size_to_bits(int size) 157945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 158045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon switch (size) { 158145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 0: 158245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 32; 158345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 1: 158445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 36; 158545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 2: 158645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 40; 158745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 3: 158845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 42; 158945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 4: 159045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 44; 159145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon case 5: 159245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon default: 159345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 48; 159445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 159545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 159645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 159745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) 159845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 159945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon unsigned long size; 160045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon void __iomem *gr0_base = ARM_SMMU_GR0(smmu); 160145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 id; 160245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 160345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "probing hardware configuration...\n"); 160445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 160545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Primecell ID */ 160645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2); 160745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1; 160845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); 160945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 161045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* ID0 */ 161145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); 161245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifndef CONFIG_64BIT 161345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) { 161445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "\tno v7 descriptor support!\n"); 161545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 161645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 161745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 161845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (id & ID0_S1TS) { 161945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->features |= ARM_SMMU_FEAT_TRANS_S1; 162045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "\tstage 1 translation\n"); 162145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 162245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 162345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (id & ID0_S2TS) { 162445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->features |= ARM_SMMU_FEAT_TRANS_S2; 162545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "\tstage 2 translation\n"); 162645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 162745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 162845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (id & ID0_NTS) { 162945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; 163045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "\tnested translation\n"); 163145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 163245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 163345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!(smmu->features & 163445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 | 163545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ARM_SMMU_FEAT_TRANS_NESTED))) { 163645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "\tno translation support!\n"); 163745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 163845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 163945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 164045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (id & ID0_CTTW) { 164145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; 164245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "\tcoherent table walk\n"); 164345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 164445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 164545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (id & ID0_SMS) { 164645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon u32 smr, sid, mask; 164745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 164845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; 164945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & 165045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ID0_NUMSMRG_MASK; 165145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->num_mapping_groups == 0) { 165245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, 165345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "stream-matching supported, but no SMRs present!\n"); 165445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 165545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 165645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 165745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smr = SMR_MASK_MASK << SMR_MASK_SHIFT; 165845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smr |= (SMR_ID_MASK << SMR_ID_SHIFT); 165945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); 166045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); 166145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 166245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; 166345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; 166445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if ((mask & sid) != sid) { 166545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, 166645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", 166745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon mask, sid); 166845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 166945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 167045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 167145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, 167245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "\tstream matching with %u register groups, mask 0x%x", 167345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_mapping_groups, mask); 167445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 167545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 167645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* ID1 */ 167745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); 167845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K; 167945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 168045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Check that we ioremapped enough */ 168145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); 168245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size *= (smmu->pagesize << 1); 168345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->size < size) 168445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_warn(smmu->dev, 168545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "device is 0x%lx bytes but only mapped 0x%lx!\n", 168645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size, smmu->size); 168745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 168845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & 168945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ID1_NUMS2CB_MASK; 169045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; 169145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->num_s2_context_banks > smmu->num_context_banks) { 169245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "impossible number of S2 context banks!\n"); 169345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 169445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 169545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", 169645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_banks, smmu->num_s2_context_banks); 169745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 169845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* ID2 */ 169945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); 170045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); 170145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 170245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* 170345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * Stage-1 output limited by stage-2 input size due to pgd 170445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon * allocation (PTRS_PER_PGD). 170545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon */ 170645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef CONFIG_64BIT 170745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Current maximum output size of 39 bits */ 170845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->s1_output_size = min(39UL, size); 170945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#else 171045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->s1_output_size = min(32UL, size); 171145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 171245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 171345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* The stage-2 output mask is also applied for bypass */ 171445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); 171545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size); 171645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 171745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version == 1) { 171845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->input_size = 32; 171945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } else { 172045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef CONFIG_64BIT 172145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; 172245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = min(39, arm_smmu_id_size_to_bits(size)); 172345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#else 172445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon size = 32; 172545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 172645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->input_size = size; 172745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 172845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) || 172945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) || 173045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) { 173145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n", 173245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon PAGE_SIZE); 173345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 173445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 173545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 173645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 173745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(smmu->dev, 173845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n", 173945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->input_size, smmu->s1_output_size, smmu->s2_output_size); 174045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 174145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 174245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 174345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_device_dt_probe(struct platform_device *pdev) 174445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 174545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct resource *res; 174645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *smmu; 174745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device_node *dev_node; 174845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device *dev = &pdev->dev; 174945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_node *node; 175045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct of_phandle_args masterspec; 175145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int num_irqs, i, err; 175245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 175345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); 175445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu) { 175545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "failed to allocate arm_smmu_device\n"); 175645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 175745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 175845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->dev = dev; 175945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 176045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 176145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!res) { 176245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "missing base address/size\n"); 176345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 176445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 176545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 176645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->size = resource_size(res); 176745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->base = devm_request_and_ioremap(dev, res); 176845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu->base) 176945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -EADDRNOTAVAIL; 177045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 177145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (of_property_read_u32(dev->of_node, "#global-interrupts", 177245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon &smmu->num_global_irqs)) { 177345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "missing #global-interrupts property\n"); 177445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 177545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 177645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 177745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon num_irqs = 0; 177845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { 177945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon num_irqs++; 178045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (num_irqs > smmu->num_global_irqs) 178145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_irqs++; 178245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 178345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 178445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (num_irqs < smmu->num_global_irqs) { 178545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_warn(dev, "found %d interrupts but expected at least %d\n", 178645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon num_irqs, smmu->num_global_irqs); 178745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_global_irqs = num_irqs; 178845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 178945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_irqs = num_irqs - smmu->num_global_irqs; 179045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 179145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, 179245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon GFP_KERNEL); 179345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu->irqs) { 179445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "failed to allocate %d irqs\n", num_irqs); 179545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENOMEM; 179645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 179745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 179845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < num_irqs; ++i) { 179945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int irq = platform_get_irq(pdev, i); 180045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (irq < 0) { 180145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "failed to get irq index %d\n", i); 180245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 180345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 180445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->irqs[i] = irq; 180545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 180645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 180745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon i = 0; 180845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->masters = RB_ROOT; 180945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", 181045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "#stream-id-cells", i, 181145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon &masterspec)) { 181245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon err = register_smmu_master(smmu, dev, &masterspec); 181345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (err) { 181445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "failed to add master %s\n", 181545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon masterspec.np->name); 181645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_put_masters; 181745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 181845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 181945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon i++; 182045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 182145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_notice(dev, "registered %d master devices\n", i); 182245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 182345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0))) 182445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->parent_of_node = dev_node; 182545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 182645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon err = arm_smmu_device_cfg_probe(smmu); 182745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (err) 182845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_put_parent; 182945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 183045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->version > 1 && 183145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_banks != smmu->num_context_irqs) { 183245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, 183345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "found only %d context interrupt(s) but %d required\n", 183445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu->num_context_irqs, smmu->num_context_banks); 183545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_put_parent; 183645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 183745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 183845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_device_reset(smmu); 183945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 184045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < smmu->num_global_irqs; ++i) { 184145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon err = request_irq(smmu->irqs[i], 184245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon arm_smmu_global_fault, 184345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon IRQF_SHARED, 184445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon "arm-smmu global fault", 184545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu); 184645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (err) { 184745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "failed to request global IRQ %d (%u)\n", 184845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon i, smmu->irqs[i]); 184945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon goto out_free_irqs; 185045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 185145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 185245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 185345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon INIT_LIST_HEAD(&smmu->list); 185445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&arm_smmu_devices_lock); 185545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_add(&smmu->list, &arm_smmu_devices); 185645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&arm_smmu_devices_lock); 185745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 185845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 185945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_free_irqs: 186045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon while (i--) 186145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon free_irq(smmu->irqs[i], smmu); 186245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 186345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_put_parent: 186445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->parent_of_node) 186545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon of_node_put(smmu->parent_of_node); 186645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 186745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconout_put_masters: 186845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { 186945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 187045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = container_of(node, struct arm_smmu_master, node); 187145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon of_node_put(master->of_node); 187245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 187345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 187445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return err; 187545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 187645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 187745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int arm_smmu_device_remove(struct platform_device *pdev) 187845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 187945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int i; 188045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct device *dev = &pdev->dev; 188145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_device *curr, *smmu = NULL; 188245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct rb_node *node; 188345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 188445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_lock(&arm_smmu_devices_lock); 188545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_for_each_entry(curr, &arm_smmu_devices, list) { 188645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (curr->dev == dev) { 188745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon smmu = curr; 188845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon list_del(&smmu->list); 188945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon break; 189045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 189145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 189245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon spin_unlock(&arm_smmu_devices_lock); 189345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 189445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!smmu) 189545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return -ENODEV; 189645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 189745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (smmu->parent_of_node) 189845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon of_node_put(smmu->parent_of_node); 189945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 190045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { 190145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon struct arm_smmu_master *master; 190245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon master = container_of(node, struct arm_smmu_master, node); 190345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon of_node_put(master->of_node); 190445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon } 190545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 190645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!bitmap_empty(smmu->vmid_map, ARM_SMMU_NUM_VMIDS)) 190745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon dev_err(dev, "removing device with active domains!\n"); 190845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 190945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon for (i = 0; i < smmu->num_global_irqs; ++i) 191045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon free_irq(smmu->irqs[i], smmu); 191145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 191245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Turn the thing off */ 191345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon writel(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0); 191445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 191545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 191645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 191745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#ifdef CONFIG_OF 191845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic struct of_device_id arm_smmu_of_match[] = { 191945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon { .compatible = "arm,smmu-v1", }, 192045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon { .compatible = "arm,smmu-v2", }, 192145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon { .compatible = "arm,mmu-400", }, 192245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon { .compatible = "arm,mmu-500", }, 192345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon { }, 192445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 192545ae7cff3684ab45f57fc13fc242c8546536a84eWill DeaconMODULE_DEVICE_TABLE(of, arm_smmu_of_match); 192645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon#endif 192745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 192845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic struct platform_driver arm_smmu_driver = { 192945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .driver = { 193045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .owner = THIS_MODULE, 193145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .name = "arm-smmu", 193245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .of_match_table = of_match_ptr(arm_smmu_of_match), 193345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon }, 193445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .probe = arm_smmu_device_dt_probe, 193545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon .remove = arm_smmu_device_remove, 193645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon}; 193745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 193845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic int __init arm_smmu_init(void) 193945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 194045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon int ret; 194145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 194245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon ret = platform_driver_register(&arm_smmu_driver); 194345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (ret) 194445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return ret; 194545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 194645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon /* Oh, for a proper bus abstraction */ 194745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!iommu_present(&platform_bus_type)); 194845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon bus_set_iommu(&platform_bus_type, &arm_smmu_ops); 194945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 195045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon if (!iommu_present(&amba_bustype)); 195145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon bus_set_iommu(&amba_bustype, &arm_smmu_ops); 195245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 195345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return 0; 195445ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 195545ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 195645ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconstatic void __exit arm_smmu_exit(void) 195745ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon{ 195845ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon return platform_driver_unregister(&arm_smmu_driver); 195945ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon} 196045ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 196145ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconmodule_init(arm_smmu_init); 196245ae7cff3684ab45f57fc13fc242c8546536a84eWill Deaconmodule_exit(arm_smmu_exit); 196345ae7cff3684ab45f57fc13fc242c8546536a84eWill Deacon 196445ae7cff3684ab45f57fc13fc242c8546536a84eWill DeaconMODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); 196545ae7cff3684ab45f57fc13fc242c8546536a84eWill DeaconMODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); 196645ae7cff3684ab45f57fc13fc242c8546536a84eWill DeaconMODULE_LICENSE("GPL v2"); 1967