1/* 2 Driver for M88RS2000 demodulator and tuner 3 4 Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com) 5 Beta Driver 6 7 Include various calculation code from DS3000 driver. 8 Copyright (C) 2009 Konstantin Dimitrov. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 24*/ 25#include <linux/init.h> 26#include <linux/module.h> 27#include <linux/device.h> 28#include <linux/jiffies.h> 29#include <linux/string.h> 30#include <linux/slab.h> 31#include <linux/types.h> 32 33 34#include "dvb_frontend.h" 35#include "m88rs2000.h" 36 37struct m88rs2000_state { 38 struct i2c_adapter *i2c; 39 const struct m88rs2000_config *config; 40 struct dvb_frontend frontend; 41 u8 no_lock_count; 42 u32 tuner_frequency; 43 u32 symbol_rate; 44 fe_code_rate_t fec_inner; 45 u8 tuner_level; 46 int errmode; 47}; 48 49static int m88rs2000_debug; 50 51module_param_named(debug, m88rs2000_debug, int, 0644); 52MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able))."); 53 54#define dprintk(level, args...) do { \ 55 if (level & m88rs2000_debug) \ 56 printk(KERN_DEBUG "m88rs2000-fe: " args); \ 57} while (0) 58 59#define deb_info(args...) dprintk(0x01, args) 60#define info(format, arg...) \ 61 printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg) 62 63static int m88rs2000_writereg(struct m88rs2000_state *state, 64 u8 reg, u8 data) 65{ 66 int ret; 67 u8 buf[] = { reg, data }; 68 struct i2c_msg msg = { 69 .addr = state->config->demod_addr, 70 .flags = 0, 71 .buf = buf, 72 .len = 2 73 }; 74 75 ret = i2c_transfer(state->i2c, &msg, 1); 76 77 if (ret != 1) 78 deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, " 79 "ret == %i)\n", __func__, reg, data, ret); 80 81 return (ret != 1) ? -EREMOTEIO : 0; 82} 83 84static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg) 85{ 86 int ret; 87 u8 b0[] = { reg }; 88 u8 b1[] = { 0 }; 89 90 struct i2c_msg msg[] = { 91 { 92 .addr = state->config->demod_addr, 93 .flags = 0, 94 .buf = b0, 95 .len = 1 96 }, { 97 .addr = state->config->demod_addr, 98 .flags = I2C_M_RD, 99 .buf = b1, 100 .len = 1 101 } 102 }; 103 104 ret = i2c_transfer(state->i2c, msg, 2); 105 106 if (ret != 2) 107 deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n", 108 __func__, reg, ret); 109 110 return b1[0]; 111} 112 113static u32 m88rs2000_get_mclk(struct dvb_frontend *fe) 114{ 115 struct m88rs2000_state *state = fe->demodulator_priv; 116 u32 mclk; 117 u8 reg; 118 /* Must not be 0x00 or 0xff */ 119 reg = m88rs2000_readreg(state, 0x86); 120 if (!reg || reg == 0xff) 121 return 0; 122 123 reg /= 2; 124 reg += 1; 125 126 mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28; 127 128 return mclk; 129} 130 131static int m88rs2000_set_carrieroffset(struct dvb_frontend *fe, s16 offset) 132{ 133 struct m88rs2000_state *state = fe->demodulator_priv; 134 u32 mclk; 135 s32 tmp; 136 u8 reg; 137 int ret; 138 139 mclk = m88rs2000_get_mclk(fe); 140 if (!mclk) 141 return -EINVAL; 142 143 tmp = (offset * 4096 + (s32)mclk / 2) / (s32)mclk; 144 if (tmp < 0) 145 tmp += 4096; 146 147 /* Carrier Offset */ 148 ret = m88rs2000_writereg(state, 0x9c, (u8)(tmp >> 4)); 149 150 reg = m88rs2000_readreg(state, 0x9d); 151 reg &= 0xf; 152 reg |= (u8)(tmp & 0xf) << 4; 153 154 ret |= m88rs2000_writereg(state, 0x9d, reg); 155 156 return ret; 157} 158 159static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate) 160{ 161 struct m88rs2000_state *state = fe->demodulator_priv; 162 int ret; 163 u64 temp; 164 u32 mclk; 165 u8 b[3]; 166 167 if ((srate < 1000000) || (srate > 45000000)) 168 return -EINVAL; 169 170 mclk = m88rs2000_get_mclk(fe); 171 if (!mclk) 172 return -EINVAL; 173 174 temp = srate / 1000; 175 temp *= 1 << 24; 176 177 do_div(temp, mclk); 178 179 b[0] = (u8) (temp >> 16) & 0xff; 180 b[1] = (u8) (temp >> 8) & 0xff; 181 b[2] = (u8) temp & 0xff; 182 183 ret = m88rs2000_writereg(state, 0x93, b[2]); 184 ret |= m88rs2000_writereg(state, 0x94, b[1]); 185 ret |= m88rs2000_writereg(state, 0x95, b[0]); 186 187 if (srate > 10000000) 188 ret |= m88rs2000_writereg(state, 0xa0, 0x20); 189 else 190 ret |= m88rs2000_writereg(state, 0xa0, 0x60); 191 192 ret |= m88rs2000_writereg(state, 0xa1, 0xe0); 193 194 if (srate > 12000000) 195 ret |= m88rs2000_writereg(state, 0xa3, 0x20); 196 else if (srate > 2800000) 197 ret |= m88rs2000_writereg(state, 0xa3, 0x98); 198 else 199 ret |= m88rs2000_writereg(state, 0xa3, 0x90); 200 201 deb_info("m88rs2000: m88rs2000_set_symbolrate\n"); 202 return ret; 203} 204 205static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe, 206 struct dvb_diseqc_master_cmd *m) 207{ 208 struct m88rs2000_state *state = fe->demodulator_priv; 209 210 int i; 211 u8 reg; 212 deb_info("%s\n", __func__); 213 m88rs2000_writereg(state, 0x9a, 0x30); 214 reg = m88rs2000_readreg(state, 0xb2); 215 reg &= 0x3f; 216 m88rs2000_writereg(state, 0xb2, reg); 217 for (i = 0; i < m->msg_len; i++) 218 m88rs2000_writereg(state, 0xb3 + i, m->msg[i]); 219 220 reg = m88rs2000_readreg(state, 0xb1); 221 reg &= 0x87; 222 reg |= ((m->msg_len - 1) << 3) | 0x07; 223 reg &= 0x7f; 224 m88rs2000_writereg(state, 0xb1, reg); 225 226 for (i = 0; i < 15; i++) { 227 if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0) 228 break; 229 msleep(20); 230 } 231 232 reg = m88rs2000_readreg(state, 0xb1); 233 if ((reg & 0x40) > 0x0) { 234 reg &= 0x7f; 235 reg |= 0x40; 236 m88rs2000_writereg(state, 0xb1, reg); 237 } 238 239 reg = m88rs2000_readreg(state, 0xb2); 240 reg &= 0x3f; 241 reg |= 0x80; 242 m88rs2000_writereg(state, 0xb2, reg); 243 m88rs2000_writereg(state, 0x9a, 0xb0); 244 245 246 return 0; 247} 248 249static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe, 250 fe_sec_mini_cmd_t burst) 251{ 252 struct m88rs2000_state *state = fe->demodulator_priv; 253 u8 reg0, reg1; 254 deb_info("%s\n", __func__); 255 m88rs2000_writereg(state, 0x9a, 0x30); 256 msleep(50); 257 reg0 = m88rs2000_readreg(state, 0xb1); 258 reg1 = m88rs2000_readreg(state, 0xb2); 259 /* TODO complete this section */ 260 m88rs2000_writereg(state, 0xb2, reg1); 261 m88rs2000_writereg(state, 0xb1, reg0); 262 m88rs2000_writereg(state, 0x9a, 0xb0); 263 264 return 0; 265} 266 267static int m88rs2000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 268{ 269 struct m88rs2000_state *state = fe->demodulator_priv; 270 u8 reg0, reg1; 271 m88rs2000_writereg(state, 0x9a, 0x30); 272 reg0 = m88rs2000_readreg(state, 0xb1); 273 reg1 = m88rs2000_readreg(state, 0xb2); 274 275 reg1 &= 0x3f; 276 277 switch (tone) { 278 case SEC_TONE_ON: 279 reg0 |= 0x4; 280 reg0 &= 0xbc; 281 break; 282 case SEC_TONE_OFF: 283 reg1 |= 0x80; 284 break; 285 default: 286 break; 287 } 288 m88rs2000_writereg(state, 0xb2, reg1); 289 m88rs2000_writereg(state, 0xb1, reg0); 290 m88rs2000_writereg(state, 0x9a, 0xb0); 291 return 0; 292} 293 294struct inittab { 295 u8 cmd; 296 u8 reg; 297 u8 val; 298}; 299 300static struct inittab m88rs2000_setup[] = { 301 {DEMOD_WRITE, 0x9a, 0x30}, 302 {DEMOD_WRITE, 0x00, 0x01}, 303 {WRITE_DELAY, 0x19, 0x00}, 304 {DEMOD_WRITE, 0x00, 0x00}, 305 {DEMOD_WRITE, 0x9a, 0xb0}, 306 {DEMOD_WRITE, 0x81, 0xc1}, 307 {DEMOD_WRITE, 0x81, 0x81}, 308 {DEMOD_WRITE, 0x86, 0xc6}, 309 {DEMOD_WRITE, 0x9a, 0x30}, 310 {DEMOD_WRITE, 0xf0, 0x22}, 311 {DEMOD_WRITE, 0xf1, 0xbf}, 312 {DEMOD_WRITE, 0xb0, 0x45}, 313 {DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/ 314 {DEMOD_WRITE, 0x9a, 0xb0}, 315 {0xff, 0xaa, 0xff} 316}; 317 318static struct inittab m88rs2000_shutdown[] = { 319 {DEMOD_WRITE, 0x9a, 0x30}, 320 {DEMOD_WRITE, 0xb0, 0x00}, 321 {DEMOD_WRITE, 0xf1, 0x89}, 322 {DEMOD_WRITE, 0x00, 0x01}, 323 {DEMOD_WRITE, 0x9a, 0xb0}, 324 {DEMOD_WRITE, 0x81, 0x81}, 325 {0xff, 0xaa, 0xff} 326}; 327 328static struct inittab fe_reset[] = { 329 {DEMOD_WRITE, 0x00, 0x01}, 330 {DEMOD_WRITE, 0x20, 0x81}, 331 {DEMOD_WRITE, 0x21, 0x80}, 332 {DEMOD_WRITE, 0x10, 0x33}, 333 {DEMOD_WRITE, 0x11, 0x44}, 334 {DEMOD_WRITE, 0x12, 0x07}, 335 {DEMOD_WRITE, 0x18, 0x20}, 336 {DEMOD_WRITE, 0x28, 0x04}, 337 {DEMOD_WRITE, 0x29, 0x8e}, 338 {DEMOD_WRITE, 0x3b, 0xff}, 339 {DEMOD_WRITE, 0x32, 0x10}, 340 {DEMOD_WRITE, 0x33, 0x02}, 341 {DEMOD_WRITE, 0x34, 0x30}, 342 {DEMOD_WRITE, 0x35, 0xff}, 343 {DEMOD_WRITE, 0x38, 0x50}, 344 {DEMOD_WRITE, 0x39, 0x68}, 345 {DEMOD_WRITE, 0x3c, 0x7f}, 346 {DEMOD_WRITE, 0x3d, 0x0f}, 347 {DEMOD_WRITE, 0x45, 0x20}, 348 {DEMOD_WRITE, 0x46, 0x24}, 349 {DEMOD_WRITE, 0x47, 0x7c}, 350 {DEMOD_WRITE, 0x48, 0x16}, 351 {DEMOD_WRITE, 0x49, 0x04}, 352 {DEMOD_WRITE, 0x4a, 0x01}, 353 {DEMOD_WRITE, 0x4b, 0x78}, 354 {DEMOD_WRITE, 0X4d, 0xd2}, 355 {DEMOD_WRITE, 0x4e, 0x6d}, 356 {DEMOD_WRITE, 0x50, 0x30}, 357 {DEMOD_WRITE, 0x51, 0x30}, 358 {DEMOD_WRITE, 0x54, 0x7b}, 359 {DEMOD_WRITE, 0x56, 0x09}, 360 {DEMOD_WRITE, 0x58, 0x59}, 361 {DEMOD_WRITE, 0x59, 0x37}, 362 {DEMOD_WRITE, 0x63, 0xfa}, 363 {0xff, 0xaa, 0xff} 364}; 365 366static struct inittab fe_trigger[] = { 367 {DEMOD_WRITE, 0x97, 0x04}, 368 {DEMOD_WRITE, 0x99, 0x77}, 369 {DEMOD_WRITE, 0x9b, 0x64}, 370 {DEMOD_WRITE, 0x9e, 0x00}, 371 {DEMOD_WRITE, 0x9f, 0xf8}, 372 {DEMOD_WRITE, 0x98, 0xff}, 373 {DEMOD_WRITE, 0xc0, 0x0f}, 374 {DEMOD_WRITE, 0x89, 0x01}, 375 {DEMOD_WRITE, 0x00, 0x00}, 376 {WRITE_DELAY, 0x0a, 0x00}, 377 {DEMOD_WRITE, 0x00, 0x01}, 378 {DEMOD_WRITE, 0x00, 0x00}, 379 {DEMOD_WRITE, 0x9a, 0xb0}, 380 {0xff, 0xaa, 0xff} 381}; 382 383static int m88rs2000_tab_set(struct m88rs2000_state *state, 384 struct inittab *tab) 385{ 386 int ret = 0; 387 u8 i; 388 if (tab == NULL) 389 return -EINVAL; 390 391 for (i = 0; i < 255; i++) { 392 switch (tab[i].cmd) { 393 case 0x01: 394 ret = m88rs2000_writereg(state, tab[i].reg, 395 tab[i].val); 396 break; 397 case 0x10: 398 if (tab[i].reg > 0) 399 mdelay(tab[i].reg); 400 break; 401 case 0xff: 402 if (tab[i].reg == 0xaa && tab[i].val == 0xff) 403 return 0; 404 case 0x00: 405 break; 406 default: 407 return -EINVAL; 408 } 409 if (ret < 0) 410 return -ENODEV; 411 } 412 return 0; 413} 414 415static int m88rs2000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt) 416{ 417 struct m88rs2000_state *state = fe->demodulator_priv; 418 u8 data; 419 420 data = m88rs2000_readreg(state, 0xb2); 421 data |= 0x03; /* bit0 V/H, bit1 off/on */ 422 423 switch (volt) { 424 case SEC_VOLTAGE_18: 425 data &= ~0x03; 426 break; 427 case SEC_VOLTAGE_13: 428 data &= ~0x03; 429 data |= 0x01; 430 break; 431 case SEC_VOLTAGE_OFF: 432 break; 433 } 434 435 m88rs2000_writereg(state, 0xb2, data); 436 437 return 0; 438} 439 440static int m88rs2000_init(struct dvb_frontend *fe) 441{ 442 struct m88rs2000_state *state = fe->demodulator_priv; 443 int ret; 444 445 deb_info("m88rs2000: init chip\n"); 446 /* Setup frontend from shutdown/cold */ 447 if (state->config->inittab) 448 ret = m88rs2000_tab_set(state, 449 (struct inittab *)state->config->inittab); 450 else 451 ret = m88rs2000_tab_set(state, m88rs2000_setup); 452 453 return ret; 454} 455 456static int m88rs2000_sleep(struct dvb_frontend *fe) 457{ 458 struct m88rs2000_state *state = fe->demodulator_priv; 459 int ret; 460 /* Shutdown the frondend */ 461 ret = m88rs2000_tab_set(state, m88rs2000_shutdown); 462 return ret; 463} 464 465static int m88rs2000_read_status(struct dvb_frontend *fe, fe_status_t *status) 466{ 467 struct m88rs2000_state *state = fe->demodulator_priv; 468 u8 reg = m88rs2000_readreg(state, 0x8c); 469 470 *status = 0; 471 472 if ((reg & 0xee) == 0xee) { 473 *status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI 474 | FE_HAS_SYNC | FE_HAS_LOCK; 475 if (state->config->set_ts_params) 476 state->config->set_ts_params(fe, CALL_IS_READ); 477 } 478 return 0; 479} 480 481static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber) 482{ 483 struct m88rs2000_state *state = fe->demodulator_priv; 484 u8 tmp0, tmp1; 485 486 m88rs2000_writereg(state, 0x9a, 0x30); 487 tmp0 = m88rs2000_readreg(state, 0xd8); 488 if ((tmp0 & 0x10) != 0) { 489 m88rs2000_writereg(state, 0x9a, 0xb0); 490 *ber = 0xffffffff; 491 return 0; 492 } 493 494 *ber = (m88rs2000_readreg(state, 0xd7) << 8) | 495 m88rs2000_readreg(state, 0xd6); 496 497 tmp1 = m88rs2000_readreg(state, 0xd9); 498 m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4); 499 /* needs twice */ 500 m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30); 501 m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30); 502 m88rs2000_writereg(state, 0x9a, 0xb0); 503 504 return 0; 505} 506 507static int m88rs2000_read_signal_strength(struct dvb_frontend *fe, 508 u16 *strength) 509{ 510 if (fe->ops.tuner_ops.get_rf_strength) 511 fe->ops.tuner_ops.get_rf_strength(fe, strength); 512 513 return 0; 514} 515 516static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr) 517{ 518 struct m88rs2000_state *state = fe->demodulator_priv; 519 520 *snr = 512 * m88rs2000_readreg(state, 0x65); 521 522 return 0; 523} 524 525static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 526{ 527 struct m88rs2000_state *state = fe->demodulator_priv; 528 u8 tmp; 529 530 *ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) | 531 m88rs2000_readreg(state, 0xd4); 532 tmp = m88rs2000_readreg(state, 0xd8); 533 m88rs2000_writereg(state, 0xd8, tmp & ~0x20); 534 /* needs two times */ 535 m88rs2000_writereg(state, 0xd8, tmp | 0x20); 536 m88rs2000_writereg(state, 0xd8, tmp | 0x20); 537 538 return 0; 539} 540 541static int m88rs2000_set_fec(struct m88rs2000_state *state, 542 fe_code_rate_t fec) 543{ 544 u8 fec_set, reg; 545 int ret; 546 547 switch (fec) { 548 case FEC_1_2: 549 fec_set = 0x8; 550 break; 551 case FEC_2_3: 552 fec_set = 0x10; 553 break; 554 case FEC_3_4: 555 fec_set = 0x20; 556 break; 557 case FEC_5_6: 558 fec_set = 0x40; 559 break; 560 case FEC_7_8: 561 fec_set = 0x80; 562 break; 563 case FEC_AUTO: 564 default: 565 fec_set = 0x0; 566 } 567 568 reg = m88rs2000_readreg(state, 0x70); 569 reg &= 0x7; 570 ret = m88rs2000_writereg(state, 0x70, reg | fec_set); 571 572 ret |= m88rs2000_writereg(state, 0x76, 0x8); 573 574 return ret; 575} 576 577static fe_code_rate_t m88rs2000_get_fec(struct m88rs2000_state *state) 578{ 579 u8 reg; 580 m88rs2000_writereg(state, 0x9a, 0x30); 581 reg = m88rs2000_readreg(state, 0x76); 582 m88rs2000_writereg(state, 0x9a, 0xb0); 583 584 reg &= 0xf0; 585 reg >>= 5; 586 587 switch (reg) { 588 case 0x4: 589 return FEC_1_2; 590 case 0x3: 591 return FEC_2_3; 592 case 0x2: 593 return FEC_3_4; 594 case 0x1: 595 return FEC_5_6; 596 case 0x0: 597 return FEC_7_8; 598 default: 599 break; 600 } 601 602 return FEC_AUTO; 603} 604 605static int m88rs2000_set_frontend(struct dvb_frontend *fe) 606{ 607 struct m88rs2000_state *state = fe->demodulator_priv; 608 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 609 fe_status_t status; 610 int i, ret = 0; 611 u32 tuner_freq; 612 s16 offset = 0; 613 u8 reg; 614 615 state->no_lock_count = 0; 616 617 if (c->delivery_system != SYS_DVBS) { 618 deb_info("%s: unsupported delivery " 619 "system selected (%d)\n", 620 __func__, c->delivery_system); 621 return -EOPNOTSUPP; 622 } 623 624 /* Set Tuner */ 625 if (fe->ops.tuner_ops.set_params) 626 ret = fe->ops.tuner_ops.set_params(fe); 627 628 if (ret < 0) 629 return -ENODEV; 630 631 if (fe->ops.tuner_ops.get_frequency) 632 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq); 633 634 if (ret < 0) 635 return -ENODEV; 636 637 offset = (s16)((s32)tuner_freq - c->frequency); 638 639 /* default mclk value 96.4285 * 2 * 1000 = 192857 */ 640 if (((c->frequency % 192857) >= (192857 - 3000)) || 641 (c->frequency % 192857) <= 3000) 642 ret = m88rs2000_writereg(state, 0x86, 0xc2); 643 else 644 ret = m88rs2000_writereg(state, 0x86, 0xc6); 645 646 ret |= m88rs2000_set_carrieroffset(fe, offset); 647 if (ret < 0) 648 return -ENODEV; 649 650 /* Reset demod by symbol rate */ 651 if (c->symbol_rate > 27500000) 652 ret = m88rs2000_writereg(state, 0xf1, 0xa4); 653 else 654 ret = m88rs2000_writereg(state, 0xf1, 0xbf); 655 656 ret |= m88rs2000_tab_set(state, fe_reset); 657 if (ret < 0) 658 return -ENODEV; 659 660 /* Set FEC */ 661 ret = m88rs2000_set_fec(state, c->fec_inner); 662 ret |= m88rs2000_writereg(state, 0x85, 0x1); 663 ret |= m88rs2000_writereg(state, 0x8a, 0xbf); 664 ret |= m88rs2000_writereg(state, 0x8d, 0x1e); 665 ret |= m88rs2000_writereg(state, 0x90, 0xf1); 666 ret |= m88rs2000_writereg(state, 0x91, 0x08); 667 668 if (ret < 0) 669 return -ENODEV; 670 671 /* Set Symbol Rate */ 672 ret = m88rs2000_set_symbolrate(fe, c->symbol_rate); 673 if (ret < 0) 674 return -ENODEV; 675 676 /* Set up Demod */ 677 ret = m88rs2000_tab_set(state, fe_trigger); 678 if (ret < 0) 679 return -ENODEV; 680 681 for (i = 0; i < 25; i++) { 682 reg = m88rs2000_readreg(state, 0x8c); 683 if ((reg & 0xee) == 0xee) { 684 status = FE_HAS_LOCK; 685 break; 686 } 687 state->no_lock_count++; 688 if (state->no_lock_count == 15) { 689 reg = m88rs2000_readreg(state, 0x70); 690 reg ^= 0x4; 691 m88rs2000_writereg(state, 0x70, reg); 692 state->no_lock_count = 0; 693 } 694 msleep(20); 695 } 696 697 if (status & FE_HAS_LOCK) { 698 state->fec_inner = m88rs2000_get_fec(state); 699 /* Uknown suspect SNR level */ 700 reg = m88rs2000_readreg(state, 0x65); 701 } 702 703 state->tuner_frequency = c->frequency; 704 state->symbol_rate = c->symbol_rate; 705 return 0; 706} 707 708static int m88rs2000_get_frontend(struct dvb_frontend *fe) 709{ 710 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 711 struct m88rs2000_state *state = fe->demodulator_priv; 712 c->fec_inner = state->fec_inner; 713 c->frequency = state->tuner_frequency; 714 c->symbol_rate = state->symbol_rate; 715 return 0; 716} 717 718static int m88rs2000_get_tune_settings(struct dvb_frontend *fe, 719 struct dvb_frontend_tune_settings *tune) 720{ 721 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 722 723 if (c->symbol_rate > 3000000) 724 tune->min_delay_ms = 2000; 725 else 726 tune->min_delay_ms = 3000; 727 728 tune->step_size = c->symbol_rate / 16000; 729 tune->max_drift = c->symbol_rate / 2000; 730 731 return 0; 732} 733 734static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 735{ 736 struct m88rs2000_state *state = fe->demodulator_priv; 737 738 if (enable) 739 m88rs2000_writereg(state, 0x81, 0x84); 740 else 741 m88rs2000_writereg(state, 0x81, 0x81); 742 udelay(10); 743 return 0; 744} 745 746static void m88rs2000_release(struct dvb_frontend *fe) 747{ 748 struct m88rs2000_state *state = fe->demodulator_priv; 749 kfree(state); 750} 751 752static struct dvb_frontend_ops m88rs2000_ops = { 753 .delsys = { SYS_DVBS }, 754 .info = { 755 .name = "M88RS2000 DVB-S", 756 .frequency_min = 950000, 757 .frequency_max = 2150000, 758 .frequency_stepsize = 1000, /* kHz for QPSK frontends */ 759 .frequency_tolerance = 5000, 760 .symbol_rate_min = 1000000, 761 .symbol_rate_max = 45000000, 762 .symbol_rate_tolerance = 500, /* ppm */ 763 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 764 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 765 FE_CAN_QPSK | FE_CAN_INVERSION_AUTO | 766 FE_CAN_FEC_AUTO 767 }, 768 769 .release = m88rs2000_release, 770 .init = m88rs2000_init, 771 .sleep = m88rs2000_sleep, 772 .i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl, 773 .read_status = m88rs2000_read_status, 774 .read_ber = m88rs2000_read_ber, 775 .read_signal_strength = m88rs2000_read_signal_strength, 776 .read_snr = m88rs2000_read_snr, 777 .read_ucblocks = m88rs2000_read_ucblocks, 778 .diseqc_send_master_cmd = m88rs2000_send_diseqc_msg, 779 .diseqc_send_burst = m88rs2000_send_diseqc_burst, 780 .set_tone = m88rs2000_set_tone, 781 .set_voltage = m88rs2000_set_voltage, 782 783 .set_frontend = m88rs2000_set_frontend, 784 .get_frontend = m88rs2000_get_frontend, 785 .get_tune_settings = m88rs2000_get_tune_settings, 786}; 787 788struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config, 789 struct i2c_adapter *i2c) 790{ 791 struct m88rs2000_state *state = NULL; 792 793 /* allocate memory for the internal state */ 794 state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL); 795 if (state == NULL) 796 goto error; 797 798 /* setup the state */ 799 state->config = config; 800 state->i2c = i2c; 801 state->tuner_frequency = 0; 802 state->symbol_rate = 0; 803 state->fec_inner = 0; 804 805 /* create dvb_frontend */ 806 memcpy(&state->frontend.ops, &m88rs2000_ops, 807 sizeof(struct dvb_frontend_ops)); 808 state->frontend.demodulator_priv = state; 809 return &state->frontend; 810 811error: 812 kfree(state); 813 814 return NULL; 815} 816EXPORT_SYMBOL(m88rs2000_attach); 817 818MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver"); 819MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com"); 820MODULE_LICENSE("GPL"); 821MODULE_VERSION("1.13"); 822 823