1/* 2 Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder 3 4 Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org> 5 Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org> 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22 References: 23 http://products.zarlink.com/product_profiles/MT312.htm 24 http://products.zarlink.com/product_profiles/SL1935.htm 25*/ 26 27#include <linux/delay.h> 28#include <linux/errno.h> 29#include <linux/init.h> 30#include <linux/kernel.h> 31#include <linux/module.h> 32#include <linux/string.h> 33#include <linux/slab.h> 34 35#include "dvb_frontend.h" 36#include "mt312_priv.h" 37#include "mt312.h" 38 39/* Max transfer size done by I2C transfer functions */ 40#define MAX_XFER_SIZE 64 41 42struct mt312_state { 43 struct i2c_adapter *i2c; 44 /* configuration settings */ 45 const struct mt312_config *config; 46 struct dvb_frontend frontend; 47 48 u8 id; 49 unsigned long xtal; 50 u8 freq_mult; 51}; 52 53static int debug; 54#define dprintk(args...) \ 55 do { \ 56 if (debug) \ 57 printk(KERN_DEBUG "mt312: " args); \ 58 } while (0) 59 60#define MT312_PLL_CLK 10000000UL /* 10 MHz */ 61#define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */ 62 63static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg, 64 u8 *buf, const size_t count) 65{ 66 int ret; 67 struct i2c_msg msg[2]; 68 u8 regbuf[1] = { reg }; 69 70 msg[0].addr = state->config->demod_address; 71 msg[0].flags = 0; 72 msg[0].buf = regbuf; 73 msg[0].len = 1; 74 msg[1].addr = state->config->demod_address; 75 msg[1].flags = I2C_M_RD; 76 msg[1].buf = buf; 77 msg[1].len = count; 78 79 ret = i2c_transfer(state->i2c, msg, 2); 80 81 if (ret != 2) { 82 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret); 83 return -EREMOTEIO; 84 } 85 86 if (debug) { 87 int i; 88 dprintk("R(%d):", reg & 0x7f); 89 for (i = 0; i < count; i++) 90 printk(KERN_CONT " %02x", buf[i]); 91 printk("\n"); 92 } 93 94 return 0; 95} 96 97static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg, 98 const u8 *src, const size_t count) 99{ 100 int ret; 101 u8 buf[MAX_XFER_SIZE]; 102 struct i2c_msg msg; 103 104 if (1 + count > sizeof(buf)) { 105 printk(KERN_WARNING 106 "mt312: write: len=%zu is too big!\n", count); 107 return -EINVAL; 108 } 109 110 if (debug) { 111 int i; 112 dprintk("W(%d):", reg & 0x7f); 113 for (i = 0; i < count; i++) 114 printk(KERN_CONT " %02x", src[i]); 115 printk("\n"); 116 } 117 118 buf[0] = reg; 119 memcpy(&buf[1], src, count); 120 121 msg.addr = state->config->demod_address; 122 msg.flags = 0; 123 msg.buf = buf; 124 msg.len = count + 1; 125 126 ret = i2c_transfer(state->i2c, &msg, 1); 127 128 if (ret != 1) { 129 dprintk("%s: ret == %d\n", __func__, ret); 130 return -EREMOTEIO; 131 } 132 133 return 0; 134} 135 136static inline int mt312_readreg(struct mt312_state *state, 137 const enum mt312_reg_addr reg, u8 *val) 138{ 139 return mt312_read(state, reg, val, 1); 140} 141 142static inline int mt312_writereg(struct mt312_state *state, 143 const enum mt312_reg_addr reg, const u8 val) 144{ 145 return mt312_write(state, reg, &val, 1); 146} 147 148static inline u32 mt312_div(u32 a, u32 b) 149{ 150 return (a + (b / 2)) / b; 151} 152 153static int mt312_reset(struct mt312_state *state, const u8 full) 154{ 155 return mt312_writereg(state, RESET, full ? 0x80 : 0x40); 156} 157 158static int mt312_get_inversion(struct mt312_state *state, 159 fe_spectral_inversion_t *i) 160{ 161 int ret; 162 u8 vit_mode; 163 164 ret = mt312_readreg(state, VIT_MODE, &vit_mode); 165 if (ret < 0) 166 return ret; 167 168 if (vit_mode & 0x80) /* auto inversion was used */ 169 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF; 170 171 return 0; 172} 173 174static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr) 175{ 176 int ret; 177 u8 sym_rate_h; 178 u8 dec_ratio; 179 u16 sym_rat_op; 180 u16 monitor; 181 u8 buf[2]; 182 183 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h); 184 if (ret < 0) 185 return ret; 186 187 if (sym_rate_h & 0x80) { 188 /* symbol rate search was used */ 189 ret = mt312_writereg(state, MON_CTRL, 0x03); 190 if (ret < 0) 191 return ret; 192 193 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); 194 if (ret < 0) 195 return ret; 196 197 monitor = (buf[0] << 8) | buf[1]; 198 199 dprintk("sr(auto) = %u\n", 200 mt312_div(monitor * 15625, 4)); 201 } else { 202 ret = mt312_writereg(state, MON_CTRL, 0x05); 203 if (ret < 0) 204 return ret; 205 206 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); 207 if (ret < 0) 208 return ret; 209 210 dec_ratio = ((buf[0] >> 5) & 0x07) * 32; 211 212 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf)); 213 if (ret < 0) 214 return ret; 215 216 sym_rat_op = (buf[0] << 8) | buf[1]; 217 218 dprintk("sym_rat_op=%d dec_ratio=%d\n", 219 sym_rat_op, dec_ratio); 220 dprintk("*sr(manual) = %lu\n", 221 (((state->xtal * 8192) / (sym_rat_op + 8192)) * 222 2) - dec_ratio); 223 } 224 225 return 0; 226} 227 228static int mt312_get_code_rate(struct mt312_state *state, fe_code_rate_t *cr) 229{ 230 const fe_code_rate_t fec_tab[8] = 231 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8, 232 FEC_AUTO, FEC_AUTO }; 233 234 int ret; 235 u8 fec_status; 236 237 ret = mt312_readreg(state, FEC_STATUS, &fec_status); 238 if (ret < 0) 239 return ret; 240 241 *cr = fec_tab[(fec_status >> 4) & 0x07]; 242 243 return 0; 244} 245 246static int mt312_initfe(struct dvb_frontend *fe) 247{ 248 struct mt312_state *state = fe->demodulator_priv; 249 int ret; 250 u8 buf[2]; 251 252 /* wake up */ 253 ret = mt312_writereg(state, CONFIG, 254 (state->freq_mult == 6 ? 0x88 : 0x8c)); 255 if (ret < 0) 256 return ret; 257 258 /* wait at least 150 usec */ 259 udelay(150); 260 261 /* full reset */ 262 ret = mt312_reset(state, 1); 263 if (ret < 0) 264 return ret; 265 266/* Per datasheet, write correct values. 09/28/03 ACCJr. 267 * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */ 268 { 269 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02, 270 0x01, 0x00, 0x00, 0x00 }; 271 272 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def)); 273 if (ret < 0) 274 return ret; 275 } 276 277 switch (state->id) { 278 case ID_ZL10313: 279 /* enable ADC */ 280 ret = mt312_writereg(state, GPP_CTRL, 0x80); 281 if (ret < 0) 282 return ret; 283 284 /* configure ZL10313 for optimal ADC performance */ 285 buf[0] = 0x80; 286 buf[1] = 0xB0; 287 ret = mt312_write(state, HW_CTRL, buf, 2); 288 if (ret < 0) 289 return ret; 290 291 /* enable MPEG output and ADCs */ 292 ret = mt312_writereg(state, HW_CTRL, 0x00); 293 if (ret < 0) 294 return ret; 295 296 ret = mt312_writereg(state, MPEG_CTRL, 0x00); 297 if (ret < 0) 298 return ret; 299 300 break; 301 } 302 303 /* SYS_CLK */ 304 buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000); 305 306 /* DISEQC_RATIO */ 307 buf[1] = mt312_div(state->xtal, 22000 * 4); 308 309 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf)); 310 if (ret < 0) 311 return ret; 312 313 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); 314 if (ret < 0) 315 return ret; 316 317 /* different MOCLK polarity */ 318 switch (state->id) { 319 case ID_ZL10313: 320 buf[0] = 0x33; 321 break; 322 default: 323 buf[0] = 0x53; 324 break; 325 } 326 327 ret = mt312_writereg(state, OP_CTRL, buf[0]); 328 if (ret < 0) 329 return ret; 330 331 /* TS_SW_LIM */ 332 buf[0] = 0x8c; 333 buf[1] = 0x98; 334 335 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf)); 336 if (ret < 0) 337 return ret; 338 339 ret = mt312_writereg(state, CS_SW_LIM, 0x69); 340 if (ret < 0) 341 return ret; 342 343 return 0; 344} 345 346static int mt312_send_master_cmd(struct dvb_frontend *fe, 347 struct dvb_diseqc_master_cmd *c) 348{ 349 struct mt312_state *state = fe->demodulator_priv; 350 int ret; 351 u8 diseqc_mode; 352 353 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg))) 354 return -EINVAL; 355 356 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); 357 if (ret < 0) 358 return ret; 359 360 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len); 361 if (ret < 0) 362 return ret; 363 364 ret = mt312_writereg(state, DISEQC_MODE, 365 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3) 366 | 0x04); 367 if (ret < 0) 368 return ret; 369 370 /* is there a better way to wait for message to be transmitted */ 371 msleep(100); 372 373 /* set DISEQC_MODE[2:0] to zero if a return message is expected */ 374 if (c->msg[0] & 0x02) { 375 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); 376 if (ret < 0) 377 return ret; 378 } 379 380 return 0; 381} 382 383static int mt312_send_burst(struct dvb_frontend *fe, const fe_sec_mini_cmd_t c) 384{ 385 struct mt312_state *state = fe->demodulator_priv; 386 const u8 mini_tab[2] = { 0x02, 0x03 }; 387 388 int ret; 389 u8 diseqc_mode; 390 391 if (c > SEC_MINI_B) 392 return -EINVAL; 393 394 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); 395 if (ret < 0) 396 return ret; 397 398 ret = mt312_writereg(state, DISEQC_MODE, 399 (diseqc_mode & 0x40) | mini_tab[c]); 400 if (ret < 0) 401 return ret; 402 403 return 0; 404} 405 406static int mt312_set_tone(struct dvb_frontend *fe, const fe_sec_tone_mode_t t) 407{ 408 struct mt312_state *state = fe->demodulator_priv; 409 const u8 tone_tab[2] = { 0x01, 0x00 }; 410 411 int ret; 412 u8 diseqc_mode; 413 414 if (t > SEC_TONE_OFF) 415 return -EINVAL; 416 417 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); 418 if (ret < 0) 419 return ret; 420 421 ret = mt312_writereg(state, DISEQC_MODE, 422 (diseqc_mode & 0x40) | tone_tab[t]); 423 if (ret < 0) 424 return ret; 425 426 return 0; 427} 428 429static int mt312_set_voltage(struct dvb_frontend *fe, const fe_sec_voltage_t v) 430{ 431 struct mt312_state *state = fe->demodulator_priv; 432 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 }; 433 u8 val; 434 435 if (v > SEC_VOLTAGE_OFF) 436 return -EINVAL; 437 438 val = volt_tab[v]; 439 if (state->config->voltage_inverted) 440 val ^= 0x40; 441 442 return mt312_writereg(state, DISEQC_MODE, val); 443} 444 445static int mt312_read_status(struct dvb_frontend *fe, fe_status_t *s) 446{ 447 struct mt312_state *state = fe->demodulator_priv; 448 int ret; 449 u8 status[3]; 450 451 *s = 0; 452 453 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status)); 454 if (ret < 0) 455 return ret; 456 457 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x," 458 " FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]); 459 460 if (status[0] & 0xc0) 461 *s |= FE_HAS_SIGNAL; /* signal noise ratio */ 462 if (status[0] & 0x04) 463 *s |= FE_HAS_CARRIER; /* qpsk carrier lock */ 464 if (status[2] & 0x02) 465 *s |= FE_HAS_VITERBI; /* viterbi lock */ 466 if (status[2] & 0x04) 467 *s |= FE_HAS_SYNC; /* byte align lock */ 468 if (status[0] & 0x01) 469 *s |= FE_HAS_LOCK; /* qpsk lock */ 470 471 return 0; 472} 473 474static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber) 475{ 476 struct mt312_state *state = fe->demodulator_priv; 477 int ret; 478 u8 buf[3]; 479 480 ret = mt312_read(state, RS_BERCNT_H, buf, 3); 481 if (ret < 0) 482 return ret; 483 484 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64; 485 486 return 0; 487} 488 489static int mt312_read_signal_strength(struct dvb_frontend *fe, 490 u16 *signal_strength) 491{ 492 struct mt312_state *state = fe->demodulator_priv; 493 int ret; 494 u8 buf[3]; 495 u16 agc; 496 s16 err_db; 497 498 ret = mt312_read(state, AGC_H, buf, sizeof(buf)); 499 if (ret < 0) 500 return ret; 501 502 agc = (buf[0] << 6) | (buf[1] >> 2); 503 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6; 504 505 *signal_strength = agc; 506 507 dprintk("agc=%08x err_db=%hd\n", agc, err_db); 508 509 return 0; 510} 511 512static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr) 513{ 514 struct mt312_state *state = fe->demodulator_priv; 515 int ret; 516 u8 buf[2]; 517 518 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf)); 519 if (ret < 0) 520 return ret; 521 522 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1); 523 524 return 0; 525} 526 527static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc) 528{ 529 struct mt312_state *state = fe->demodulator_priv; 530 int ret; 531 u8 buf[2]; 532 533 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf)); 534 if (ret < 0) 535 return ret; 536 537 *ubc = (buf[0] << 8) | buf[1]; 538 539 return 0; 540} 541 542static int mt312_set_frontend(struct dvb_frontend *fe) 543{ 544 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 545 struct mt312_state *state = fe->demodulator_priv; 546 int ret; 547 u8 buf[5], config_val; 548 u16 sr; 549 550 const u8 fec_tab[10] = 551 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f }; 552 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 }; 553 554 dprintk("%s: Freq %d\n", __func__, p->frequency); 555 556 if ((p->frequency < fe->ops.info.frequency_min) 557 || (p->frequency > fe->ops.info.frequency_max)) 558 return -EINVAL; 559 560 if (((int)p->inversion < INVERSION_OFF) 561 || (p->inversion > INVERSION_ON)) 562 return -EINVAL; 563 564 if ((p->symbol_rate < fe->ops.info.symbol_rate_min) 565 || (p->symbol_rate > fe->ops.info.symbol_rate_max)) 566 return -EINVAL; 567 568 if (((int)p->fec_inner < FEC_NONE) 569 || (p->fec_inner > FEC_AUTO)) 570 return -EINVAL; 571 572 if ((p->fec_inner == FEC_4_5) 573 || (p->fec_inner == FEC_8_9)) 574 return -EINVAL; 575 576 switch (state->id) { 577 case ID_VP310: 578 /* For now we will do this only for the VP310. 579 * It should be better for the mt312 as well, 580 * but tuning will be slower. ACCJr 09/29/03 581 */ 582 ret = mt312_readreg(state, CONFIG, &config_val); 583 if (ret < 0) 584 return ret; 585 if (p->symbol_rate >= 30000000) { 586 /* Note that 30MS/s should use 90MHz */ 587 if (state->freq_mult == 6) { 588 /* We are running 60MHz */ 589 state->freq_mult = 9; 590 ret = mt312_initfe(fe); 591 if (ret < 0) 592 return ret; 593 } 594 } else { 595 if (state->freq_mult == 9) { 596 /* We are running 90MHz */ 597 state->freq_mult = 6; 598 ret = mt312_initfe(fe); 599 if (ret < 0) 600 return ret; 601 } 602 } 603 break; 604 605 case ID_MT312: 606 case ID_ZL10313: 607 break; 608 609 default: 610 return -EINVAL; 611 } 612 613 if (fe->ops.tuner_ops.set_params) { 614 fe->ops.tuner_ops.set_params(fe); 615 if (fe->ops.i2c_gate_ctrl) 616 fe->ops.i2c_gate_ctrl(fe, 0); 617 } 618 619 /* sr = (u16)(sr * 256.0 / 1000000.0) */ 620 sr = mt312_div(p->symbol_rate * 4, 15625); 621 622 /* SYM_RATE */ 623 buf[0] = (sr >> 8) & 0x3f; 624 buf[1] = (sr >> 0) & 0xff; 625 626 /* VIT_MODE */ 627 buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner]; 628 629 /* QPSK_CTRL */ 630 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */ 631 632 if (p->symbol_rate < 10000000) 633 buf[3] |= 0x04; /* use afc mode */ 634 635 /* GO */ 636 buf[4] = 0x01; 637 638 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf)); 639 if (ret < 0) 640 return ret; 641 642 mt312_reset(state, 0); 643 644 return 0; 645} 646 647static int mt312_get_frontend(struct dvb_frontend *fe) 648{ 649 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 650 struct mt312_state *state = fe->demodulator_priv; 651 int ret; 652 653 ret = mt312_get_inversion(state, &p->inversion); 654 if (ret < 0) 655 return ret; 656 657 ret = mt312_get_symbol_rate(state, &p->symbol_rate); 658 if (ret < 0) 659 return ret; 660 661 ret = mt312_get_code_rate(state, &p->fec_inner); 662 if (ret < 0) 663 return ret; 664 665 return 0; 666} 667 668static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 669{ 670 struct mt312_state *state = fe->demodulator_priv; 671 672 u8 val = 0x00; 673 int ret; 674 675 switch (state->id) { 676 case ID_ZL10313: 677 ret = mt312_readreg(state, GPP_CTRL, &val); 678 if (ret < 0) 679 goto error; 680 681 /* preserve this bit to not accidentally shutdown ADC */ 682 val &= 0x80; 683 break; 684 } 685 686 if (enable) 687 val |= 0x40; 688 else 689 val &= ~0x40; 690 691 ret = mt312_writereg(state, GPP_CTRL, val); 692 693error: 694 return ret; 695} 696 697static int mt312_sleep(struct dvb_frontend *fe) 698{ 699 struct mt312_state *state = fe->demodulator_priv; 700 int ret; 701 u8 config; 702 703 /* reset all registers to defaults */ 704 ret = mt312_reset(state, 1); 705 if (ret < 0) 706 return ret; 707 708 if (state->id == ID_ZL10313) { 709 /* reset ADC */ 710 ret = mt312_writereg(state, GPP_CTRL, 0x00); 711 if (ret < 0) 712 return ret; 713 714 /* full shutdown of ADCs, mpeg bus tristated */ 715 ret = mt312_writereg(state, HW_CTRL, 0x0d); 716 if (ret < 0) 717 return ret; 718 } 719 720 ret = mt312_readreg(state, CONFIG, &config); 721 if (ret < 0) 722 return ret; 723 724 /* enter standby */ 725 ret = mt312_writereg(state, CONFIG, config & 0x7f); 726 if (ret < 0) 727 return ret; 728 729 return 0; 730} 731 732static int mt312_get_tune_settings(struct dvb_frontend *fe, 733 struct dvb_frontend_tune_settings *fesettings) 734{ 735 fesettings->min_delay_ms = 50; 736 fesettings->step_size = 0; 737 fesettings->max_drift = 0; 738 return 0; 739} 740 741static void mt312_release(struct dvb_frontend *fe) 742{ 743 struct mt312_state *state = fe->demodulator_priv; 744 kfree(state); 745} 746 747#define MT312_SYS_CLK 90000000UL /* 90 MHz */ 748static struct dvb_frontend_ops mt312_ops = { 749 .delsys = { SYS_DVBS }, 750 .info = { 751 .name = "Zarlink ???? DVB-S", 752 .frequency_min = 950000, 753 .frequency_max = 2150000, 754 /* FIXME: adjust freq to real used xtal */ 755 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128, 756 .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */ 757 .symbol_rate_max = MT312_SYS_CLK / 2, 758 .caps = 759 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 760 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 761 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS | 762 FE_CAN_RECOVER 763 }, 764 765 .release = mt312_release, 766 767 .init = mt312_initfe, 768 .sleep = mt312_sleep, 769 .i2c_gate_ctrl = mt312_i2c_gate_ctrl, 770 771 .set_frontend = mt312_set_frontend, 772 .get_frontend = mt312_get_frontend, 773 .get_tune_settings = mt312_get_tune_settings, 774 775 .read_status = mt312_read_status, 776 .read_ber = mt312_read_ber, 777 .read_signal_strength = mt312_read_signal_strength, 778 .read_snr = mt312_read_snr, 779 .read_ucblocks = mt312_read_ucblocks, 780 781 .diseqc_send_master_cmd = mt312_send_master_cmd, 782 .diseqc_send_burst = mt312_send_burst, 783 .set_tone = mt312_set_tone, 784 .set_voltage = mt312_set_voltage, 785}; 786 787struct dvb_frontend *mt312_attach(const struct mt312_config *config, 788 struct i2c_adapter *i2c) 789{ 790 struct mt312_state *state = NULL; 791 792 /* allocate memory for the internal state */ 793 state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL); 794 if (state == NULL) 795 goto error; 796 797 /* setup the state */ 798 state->config = config; 799 state->i2c = i2c; 800 801 /* check if the demod is there */ 802 if (mt312_readreg(state, ID, &state->id) < 0) 803 goto error; 804 805 /* create dvb_frontend */ 806 memcpy(&state->frontend.ops, &mt312_ops, 807 sizeof(struct dvb_frontend_ops)); 808 state->frontend.demodulator_priv = state; 809 810 switch (state->id) { 811 case ID_VP310: 812 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S"); 813 state->xtal = MT312_PLL_CLK; 814 state->freq_mult = 9; 815 break; 816 case ID_MT312: 817 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S"); 818 state->xtal = MT312_PLL_CLK; 819 state->freq_mult = 6; 820 break; 821 case ID_ZL10313: 822 strcpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S"); 823 state->xtal = MT312_PLL_CLK_10_111; 824 state->freq_mult = 9; 825 break; 826 default: 827 printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313" 828 " are supported chips.\n"); 829 goto error; 830 } 831 832 return &state->frontend; 833 834error: 835 kfree(state); 836 return NULL; 837} 838EXPORT_SYMBOL(mt312_attach); 839 840module_param(debug, int, 0644); 841MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 842 843MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver"); 844MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>"); 845MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>"); 846MODULE_LICENSE("GPL"); 847 848