1/* 2 * Support for NXT2002 and NXT2004 - VSB/QAM 3 * 4 * Copyright (C) 2005 Kirk Lapray <kirk.lapray@gmail.com> 5 * Copyright (C) 2006-2014 Michael Krufky <mkrufky@linuxtv.org> 6 * based on nxt2002 by Taylor Jacob <rtjacob@earthlink.net> 7 * and nxt2004 by Jean-Francois Thibert <jeanfrancois@sagetv.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 * 23*/ 24 25/* 26 * NOTES ABOUT THIS DRIVER 27 * 28 * This Linux driver supports: 29 * B2C2/BBTI Technisat Air2PC - ATSC (NXT2002) 30 * AverTVHD MCE A180 (NXT2004) 31 * ATI HDTV Wonder (NXT2004) 32 * 33 * This driver needs external firmware. Please use the command 34 * "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2002" or 35 * "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2004" to 36 * download/extract the appropriate firmware, and then copy it to 37 * /usr/lib/hotplug/firmware/ or /lib/firmware/ 38 * (depending on configuration of firmware hotplug). 39 */ 40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42/* Max transfer size done by I2C transfer functions */ 43#define MAX_XFER_SIZE 256 44 45#define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw" 46#define NXT2004_DEFAULT_FIRMWARE "dvb-fe-nxt2004.fw" 47#define CRC_CCIT_MASK 0x1021 48 49#include <linux/kernel.h> 50#include <linux/init.h> 51#include <linux/module.h> 52#include <linux/slab.h> 53#include <linux/string.h> 54 55#include "dvb_frontend.h" 56#include "nxt200x.h" 57 58struct nxt200x_state { 59 60 struct i2c_adapter* i2c; 61 const struct nxt200x_config* config; 62 struct dvb_frontend frontend; 63 64 /* demodulator private data */ 65 nxt_chip_type demod_chip; 66 u8 initialised:1; 67}; 68 69static int debug; 70#define dprintk(args...) do { if (debug) pr_debug(args); } while (0) 71 72static int i2c_writebytes (struct nxt200x_state* state, u8 addr, u8 *buf, u8 len) 73{ 74 int err; 75 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len }; 76 77 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 78 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n", 79 __func__, addr, err); 80 return -EREMOTEIO; 81 } 82 return 0; 83} 84 85static int i2c_readbytes(struct nxt200x_state *state, u8 addr, u8 *buf, u8 len) 86{ 87 int err; 88 struct i2c_msg msg = { .addr = addr, .flags = I2C_M_RD, .buf = buf, .len = len }; 89 90 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 91 pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n", 92 __func__, addr, err); 93 return -EREMOTEIO; 94 } 95 return 0; 96} 97 98static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg, 99 const u8 *buf, u8 len) 100{ 101 u8 buf2[MAX_XFER_SIZE]; 102 int err; 103 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 }; 104 105 if (1 + len > sizeof(buf2)) { 106 pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n", 107 __func__, reg, len); 108 return -EINVAL; 109 } 110 111 buf2[0] = reg; 112 memcpy(&buf2[1], buf, len); 113 114 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 115 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n", 116 __func__, state->config->demod_address, err); 117 return -EREMOTEIO; 118 } 119 return 0; 120} 121 122static int nxt200x_readbytes(struct nxt200x_state *state, u8 reg, u8 *buf, u8 len) 123{ 124 u8 reg2 [] = { reg }; 125 126 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 }, 127 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } }; 128 129 int err; 130 131 if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) { 132 pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n", 133 __func__, state->config->demod_address, err); 134 return -EREMOTEIO; 135 } 136 return 0; 137} 138 139static u16 nxt200x_crc(u16 crc, u8 c) 140{ 141 u8 i; 142 u16 input = (u16) c & 0xFF; 143 144 input<<=8; 145 for(i=0; i<8; i++) { 146 if((crc^input) & 0x8000) 147 crc=(crc<<1)^CRC_CCIT_MASK; 148 else 149 crc<<=1; 150 input<<=1; 151 } 152 return crc; 153} 154 155static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) 156{ 157 u8 attr, len2, buf; 158 dprintk("%s\n", __func__); 159 160 /* set mutli register register */ 161 nxt200x_writebytes(state, 0x35, ®, 1); 162 163 /* send the actual data */ 164 nxt200x_writebytes(state, 0x36, data, len); 165 166 switch (state->demod_chip) { 167 case NXT2002: 168 len2 = len; 169 buf = 0x02; 170 break; 171 case NXT2004: 172 /* probably not right, but gives correct values */ 173 attr = 0x02; 174 if (reg & 0x80) { 175 attr = attr << 1; 176 if (reg & 0x04) 177 attr = attr >> 1; 178 } 179 /* set write bit */ 180 len2 = ((attr << 4) | 0x10) | len; 181 buf = 0x80; 182 break; 183 default: 184 return -EINVAL; 185 break; 186 } 187 188 /* set multi register length */ 189 nxt200x_writebytes(state, 0x34, &len2, 1); 190 191 /* toggle the multireg write bit */ 192 nxt200x_writebytes(state, 0x21, &buf, 1); 193 194 nxt200x_readbytes(state, 0x21, &buf, 1); 195 196 switch (state->demod_chip) { 197 case NXT2002: 198 if ((buf & 0x02) == 0) 199 return 0; 200 break; 201 case NXT2004: 202 if (buf == 0) 203 return 0; 204 break; 205 default: 206 return -EINVAL; 207 break; 208 } 209 210 pr_warn("Error writing multireg register 0x%02X\n", reg); 211 212 return 0; 213} 214 215static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) 216{ 217 int i; 218 u8 buf, len2, attr; 219 dprintk("%s\n", __func__); 220 221 /* set mutli register register */ 222 nxt200x_writebytes(state, 0x35, ®, 1); 223 224 switch (state->demod_chip) { 225 case NXT2002: 226 /* set multi register length */ 227 len2 = len & 0x80; 228 nxt200x_writebytes(state, 0x34, &len2, 1); 229 230 /* read the actual data */ 231 nxt200x_readbytes(state, reg, data, len); 232 return 0; 233 break; 234 case NXT2004: 235 /* probably not right, but gives correct values */ 236 attr = 0x02; 237 if (reg & 0x80) { 238 attr = attr << 1; 239 if (reg & 0x04) 240 attr = attr >> 1; 241 } 242 243 /* set multi register length */ 244 len2 = (attr << 4) | len; 245 nxt200x_writebytes(state, 0x34, &len2, 1); 246 247 /* toggle the multireg bit*/ 248 buf = 0x80; 249 nxt200x_writebytes(state, 0x21, &buf, 1); 250 251 /* read the actual data */ 252 for(i = 0; i < len; i++) { 253 nxt200x_readbytes(state, 0x36 + i, &data[i], 1); 254 } 255 return 0; 256 break; 257 default: 258 return -EINVAL; 259 break; 260 } 261} 262 263static void nxt200x_microcontroller_stop (struct nxt200x_state* state) 264{ 265 u8 buf, stopval, counter = 0; 266 dprintk("%s\n", __func__); 267 268 /* set correct stop value */ 269 switch (state->demod_chip) { 270 case NXT2002: 271 stopval = 0x40; 272 break; 273 case NXT2004: 274 stopval = 0x10; 275 break; 276 default: 277 stopval = 0; 278 break; 279 } 280 281 buf = 0x80; 282 nxt200x_writebytes(state, 0x22, &buf, 1); 283 284 while (counter < 20) { 285 nxt200x_readbytes(state, 0x31, &buf, 1); 286 if (buf & stopval) 287 return; 288 msleep(10); 289 counter++; 290 } 291 292 pr_warn("Timeout waiting for nxt200x to stop. This is ok after " 293 "firmware upload.\n"); 294 return; 295} 296 297static void nxt200x_microcontroller_start (struct nxt200x_state* state) 298{ 299 u8 buf; 300 dprintk("%s\n", __func__); 301 302 buf = 0x00; 303 nxt200x_writebytes(state, 0x22, &buf, 1); 304} 305 306static void nxt2004_microcontroller_init (struct nxt200x_state* state) 307{ 308 u8 buf[9]; 309 u8 counter = 0; 310 dprintk("%s\n", __func__); 311 312 buf[0] = 0x00; 313 nxt200x_writebytes(state, 0x2b, buf, 1); 314 buf[0] = 0x70; 315 nxt200x_writebytes(state, 0x34, buf, 1); 316 buf[0] = 0x04; 317 nxt200x_writebytes(state, 0x35, buf, 1); 318 buf[0] = 0x01; buf[1] = 0x23; buf[2] = 0x45; buf[3] = 0x67; buf[4] = 0x89; 319 buf[5] = 0xAB; buf[6] = 0xCD; buf[7] = 0xEF; buf[8] = 0xC0; 320 nxt200x_writebytes(state, 0x36, buf, 9); 321 buf[0] = 0x80; 322 nxt200x_writebytes(state, 0x21, buf, 1); 323 324 while (counter < 20) { 325 nxt200x_readbytes(state, 0x21, buf, 1); 326 if (buf[0] == 0) 327 return; 328 msleep(10); 329 counter++; 330 } 331 332 pr_warn("Timeout waiting for nxt2004 to init.\n"); 333 334 return; 335} 336 337static int nxt200x_writetuner (struct nxt200x_state* state, u8* data) 338{ 339 u8 buf, count = 0; 340 341 dprintk("%s\n", __func__); 342 343 dprintk("Tuner Bytes: %*ph\n", 4, data + 1); 344 345 /* if NXT2004, write directly to tuner. if NXT2002, write through NXT chip. 346 * direct write is required for Philips TUV1236D and ALPS TDHU2 */ 347 switch (state->demod_chip) { 348 case NXT2004: 349 if (i2c_writebytes(state, data[0], data+1, 4)) 350 pr_warn("error writing to tuner\n"); 351 /* wait until we have a lock */ 352 while (count < 20) { 353 i2c_readbytes(state, data[0], &buf, 1); 354 if (buf & 0x40) 355 return 0; 356 msleep(100); 357 count++; 358 } 359 pr_warn("timeout waiting for tuner lock\n"); 360 break; 361 case NXT2002: 362 /* set the i2c transfer speed to the tuner */ 363 buf = 0x03; 364 nxt200x_writebytes(state, 0x20, &buf, 1); 365 366 /* setup to transfer 4 bytes via i2c */ 367 buf = 0x04; 368 nxt200x_writebytes(state, 0x34, &buf, 1); 369 370 /* write actual tuner bytes */ 371 nxt200x_writebytes(state, 0x36, data+1, 4); 372 373 /* set tuner i2c address */ 374 buf = data[0] << 1; 375 nxt200x_writebytes(state, 0x35, &buf, 1); 376 377 /* write UC Opmode to begin transfer */ 378 buf = 0x80; 379 nxt200x_writebytes(state, 0x21, &buf, 1); 380 381 while (count < 20) { 382 nxt200x_readbytes(state, 0x21, &buf, 1); 383 if ((buf & 0x80)== 0x00) 384 return 0; 385 msleep(100); 386 count++; 387 } 388 pr_warn("timeout error writing to tuner\n"); 389 break; 390 default: 391 return -EINVAL; 392 break; 393 } 394 return 0; 395} 396 397static void nxt200x_agc_reset(struct nxt200x_state* state) 398{ 399 u8 buf; 400 dprintk("%s\n", __func__); 401 402 switch (state->demod_chip) { 403 case NXT2002: 404 buf = 0x08; 405 nxt200x_writebytes(state, 0x08, &buf, 1); 406 buf = 0x00; 407 nxt200x_writebytes(state, 0x08, &buf, 1); 408 break; 409 case NXT2004: 410 nxt200x_readreg_multibyte(state, 0x08, &buf, 1); 411 buf = 0x08; 412 nxt200x_writereg_multibyte(state, 0x08, &buf, 1); 413 buf = 0x00; 414 nxt200x_writereg_multibyte(state, 0x08, &buf, 1); 415 break; 416 default: 417 break; 418 } 419 return; 420} 421 422static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw) 423{ 424 425 struct nxt200x_state* state = fe->demodulator_priv; 426 u8 buf[3], written = 0, chunkpos = 0; 427 u16 rambase, position, crc = 0; 428 429 dprintk("%s\n", __func__); 430 dprintk("Firmware is %zu bytes\n", fw->size); 431 432 /* Get the RAM base for this nxt2002 */ 433 nxt200x_readbytes(state, 0x10, buf, 1); 434 435 if (buf[0] & 0x10) 436 rambase = 0x1000; 437 else 438 rambase = 0x0000; 439 440 dprintk("rambase on this nxt2002 is %04X\n", rambase); 441 442 /* Hold the micro in reset while loading firmware */ 443 buf[0] = 0x80; 444 nxt200x_writebytes(state, 0x2B, buf, 1); 445 446 for (position = 0; position < fw->size; position++) { 447 if (written == 0) { 448 crc = 0; 449 chunkpos = 0x28; 450 buf[0] = ((rambase + position) >> 8); 451 buf[1] = (rambase + position) & 0xFF; 452 buf[2] = 0x81; 453 /* write starting address */ 454 nxt200x_writebytes(state, 0x29, buf, 3); 455 } 456 written++; 457 chunkpos++; 458 459 if ((written % 4) == 0) 460 nxt200x_writebytes(state, chunkpos, &fw->data[position-3], 4); 461 462 crc = nxt200x_crc(crc, fw->data[position]); 463 464 if ((written == 255) || (position+1 == fw->size)) { 465 /* write remaining bytes of firmware */ 466 nxt200x_writebytes(state, chunkpos+4-(written %4), 467 &fw->data[position-(written %4) + 1], 468 written %4); 469 buf[0] = crc << 8; 470 buf[1] = crc & 0xFF; 471 472 /* write crc */ 473 nxt200x_writebytes(state, 0x2C, buf, 2); 474 475 /* do a read to stop things */ 476 nxt200x_readbytes(state, 0x2A, buf, 1); 477 478 /* set transfer mode to complete */ 479 buf[0] = 0x80; 480 nxt200x_writebytes(state, 0x2B, buf, 1); 481 482 written = 0; 483 } 484 } 485 486 return 0; 487}; 488 489static int nxt2004_load_firmware (struct dvb_frontend* fe, const struct firmware *fw) 490{ 491 492 struct nxt200x_state* state = fe->demodulator_priv; 493 u8 buf[3]; 494 u16 rambase, position, crc=0; 495 496 dprintk("%s\n", __func__); 497 dprintk("Firmware is %zu bytes\n", fw->size); 498 499 /* set rambase */ 500 rambase = 0x1000; 501 502 /* hold the micro in reset while loading firmware */ 503 buf[0] = 0x80; 504 nxt200x_writebytes(state, 0x2B, buf,1); 505 506 /* calculate firmware CRC */ 507 for (position = 0; position < fw->size; position++) { 508 crc = nxt200x_crc(crc, fw->data[position]); 509 } 510 511 buf[0] = rambase >> 8; 512 buf[1] = rambase & 0xFF; 513 buf[2] = 0x81; 514 /* write starting address */ 515 nxt200x_writebytes(state,0x29,buf,3); 516 517 for (position = 0; position < fw->size;) { 518 nxt200x_writebytes(state, 0x2C, &fw->data[position], 519 fw->size-position > 255 ? 255 : fw->size-position); 520 position += (fw->size-position > 255 ? 255 : fw->size-position); 521 } 522 buf[0] = crc >> 8; 523 buf[1] = crc & 0xFF; 524 525 dprintk("firmware crc is 0x%02X 0x%02X\n", buf[0], buf[1]); 526 527 /* write crc */ 528 nxt200x_writebytes(state, 0x2C, buf,2); 529 530 /* do a read to stop things */ 531 nxt200x_readbytes(state, 0x2C, buf, 1); 532 533 /* set transfer mode to complete */ 534 buf[0] = 0x80; 535 nxt200x_writebytes(state, 0x2B, buf,1); 536 537 return 0; 538}; 539 540static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe) 541{ 542 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 543 struct nxt200x_state* state = fe->demodulator_priv; 544 u8 buf[5]; 545 546 /* stop the micro first */ 547 nxt200x_microcontroller_stop(state); 548 549 if (state->demod_chip == NXT2004) { 550 /* make sure demod is set to digital */ 551 buf[0] = 0x04; 552 nxt200x_writebytes(state, 0x14, buf, 1); 553 buf[0] = 0x00; 554 nxt200x_writebytes(state, 0x17, buf, 1); 555 } 556 557 /* set additional params */ 558 switch (p->modulation) { 559 case QAM_64: 560 case QAM_256: 561 /* Set punctured clock for QAM */ 562 /* This is just a guess since I am unable to test it */ 563 if (state->config->set_ts_params) 564 state->config->set_ts_params(fe, 1); 565 break; 566 case VSB_8: 567 /* Set non-punctured clock for VSB */ 568 if (state->config->set_ts_params) 569 state->config->set_ts_params(fe, 0); 570 break; 571 default: 572 return -EINVAL; 573 break; 574 } 575 576 if (fe->ops.tuner_ops.calc_regs) { 577 /* get tuning information */ 578 fe->ops.tuner_ops.calc_regs(fe, buf, 5); 579 580 /* write frequency information */ 581 nxt200x_writetuner(state, buf); 582 } 583 584 /* reset the agc now that tuning has been completed */ 585 nxt200x_agc_reset(state); 586 587 /* set target power level */ 588 switch (p->modulation) { 589 case QAM_64: 590 case QAM_256: 591 buf[0] = 0x74; 592 break; 593 case VSB_8: 594 buf[0] = 0x70; 595 break; 596 default: 597 return -EINVAL; 598 break; 599 } 600 nxt200x_writebytes(state, 0x42, buf, 1); 601 602 /* configure sdm */ 603 switch (state->demod_chip) { 604 case NXT2002: 605 buf[0] = 0x87; 606 break; 607 case NXT2004: 608 buf[0] = 0x07; 609 break; 610 default: 611 return -EINVAL; 612 break; 613 } 614 nxt200x_writebytes(state, 0x57, buf, 1); 615 616 /* write sdm1 input */ 617 buf[0] = 0x10; 618 buf[1] = 0x00; 619 switch (state->demod_chip) { 620 case NXT2002: 621 nxt200x_writereg_multibyte(state, 0x58, buf, 2); 622 break; 623 case NXT2004: 624 nxt200x_writebytes(state, 0x58, buf, 2); 625 break; 626 default: 627 return -EINVAL; 628 break; 629 } 630 631 /* write sdmx input */ 632 switch (p->modulation) { 633 case QAM_64: 634 buf[0] = 0x68; 635 break; 636 case QAM_256: 637 buf[0] = 0x64; 638 break; 639 case VSB_8: 640 buf[0] = 0x60; 641 break; 642 default: 643 return -EINVAL; 644 break; 645 } 646 buf[1] = 0x00; 647 switch (state->demod_chip) { 648 case NXT2002: 649 nxt200x_writereg_multibyte(state, 0x5C, buf, 2); 650 break; 651 case NXT2004: 652 nxt200x_writebytes(state, 0x5C, buf, 2); 653 break; 654 default: 655 return -EINVAL; 656 break; 657 } 658 659 /* write adc power lpf fc */ 660 buf[0] = 0x05; 661 nxt200x_writebytes(state, 0x43, buf, 1); 662 663 if (state->demod_chip == NXT2004) { 664 /* write ??? */ 665 buf[0] = 0x00; 666 buf[1] = 0x00; 667 nxt200x_writebytes(state, 0x46, buf, 2); 668 } 669 670 /* write accumulator2 input */ 671 buf[0] = 0x80; 672 buf[1] = 0x00; 673 switch (state->demod_chip) { 674 case NXT2002: 675 nxt200x_writereg_multibyte(state, 0x4B, buf, 2); 676 break; 677 case NXT2004: 678 nxt200x_writebytes(state, 0x4B, buf, 2); 679 break; 680 default: 681 return -EINVAL; 682 break; 683 } 684 685 /* write kg1 */ 686 buf[0] = 0x00; 687 nxt200x_writebytes(state, 0x4D, buf, 1); 688 689 /* write sdm12 lpf fc */ 690 buf[0] = 0x44; 691 nxt200x_writebytes(state, 0x55, buf, 1); 692 693 /* write agc control reg */ 694 buf[0] = 0x04; 695 nxt200x_writebytes(state, 0x41, buf, 1); 696 697 if (state->demod_chip == NXT2004) { 698 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 699 buf[0] = 0x24; 700 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 701 702 /* soft reset? */ 703 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 704 buf[0] = 0x10; 705 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 706 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 707 buf[0] = 0x00; 708 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 709 710 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 711 buf[0] = 0x04; 712 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 713 buf[0] = 0x00; 714 nxt200x_writereg_multibyte(state, 0x81, buf, 1); 715 buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00; 716 nxt200x_writereg_multibyte(state, 0x82, buf, 3); 717 nxt200x_readreg_multibyte(state, 0x88, buf, 1); 718 buf[0] = 0x11; 719 nxt200x_writereg_multibyte(state, 0x88, buf, 1); 720 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 721 buf[0] = 0x44; 722 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 723 } 724 725 /* write agc ucgp0 */ 726 switch (p->modulation) { 727 case QAM_64: 728 buf[0] = 0x02; 729 break; 730 case QAM_256: 731 buf[0] = 0x03; 732 break; 733 case VSB_8: 734 buf[0] = 0x00; 735 break; 736 default: 737 return -EINVAL; 738 break; 739 } 740 nxt200x_writebytes(state, 0x30, buf, 1); 741 742 /* write agc control reg */ 743 buf[0] = 0x00; 744 nxt200x_writebytes(state, 0x41, buf, 1); 745 746 /* write accumulator2 input */ 747 buf[0] = 0x80; 748 buf[1] = 0x00; 749 switch (state->demod_chip) { 750 case NXT2002: 751 nxt200x_writereg_multibyte(state, 0x49, buf, 2); 752 nxt200x_writereg_multibyte(state, 0x4B, buf, 2); 753 break; 754 case NXT2004: 755 nxt200x_writebytes(state, 0x49, buf, 2); 756 nxt200x_writebytes(state, 0x4B, buf, 2); 757 break; 758 default: 759 return -EINVAL; 760 break; 761 } 762 763 /* write agc control reg */ 764 buf[0] = 0x04; 765 nxt200x_writebytes(state, 0x41, buf, 1); 766 767 nxt200x_microcontroller_start(state); 768 769 if (state->demod_chip == NXT2004) { 770 nxt2004_microcontroller_init(state); 771 772 /* ???? */ 773 buf[0] = 0xF0; 774 buf[1] = 0x00; 775 nxt200x_writebytes(state, 0x5C, buf, 2); 776 } 777 778 /* adjacent channel detection should be done here, but I don't 779 have any stations with this need so I cannot test it */ 780 781 return 0; 782} 783 784static int nxt200x_read_status(struct dvb_frontend* fe, fe_status_t* status) 785{ 786 struct nxt200x_state* state = fe->demodulator_priv; 787 u8 lock; 788 nxt200x_readbytes(state, 0x31, &lock, 1); 789 790 *status = 0; 791 if (lock & 0x20) { 792 *status |= FE_HAS_SIGNAL; 793 *status |= FE_HAS_CARRIER; 794 *status |= FE_HAS_VITERBI; 795 *status |= FE_HAS_SYNC; 796 *status |= FE_HAS_LOCK; 797 } 798 return 0; 799} 800 801static int nxt200x_read_ber(struct dvb_frontend* fe, u32* ber) 802{ 803 struct nxt200x_state* state = fe->demodulator_priv; 804 u8 b[3]; 805 806 nxt200x_readreg_multibyte(state, 0xE6, b, 3); 807 808 *ber = ((b[0] << 8) + b[1]) * 8; 809 810 return 0; 811} 812 813static int nxt200x_read_signal_strength(struct dvb_frontend* fe, u16* strength) 814{ 815 struct nxt200x_state* state = fe->demodulator_priv; 816 u8 b[2]; 817 u16 temp = 0; 818 819 /* setup to read cluster variance */ 820 b[0] = 0x00; 821 nxt200x_writebytes(state, 0xA1, b, 1); 822 823 /* get multreg val */ 824 nxt200x_readreg_multibyte(state, 0xA6, b, 2); 825 826 temp = (b[0] << 8) | b[1]; 827 *strength = ((0x7FFF - temp) & 0x0FFF) * 16; 828 829 return 0; 830} 831 832static int nxt200x_read_snr(struct dvb_frontend* fe, u16* snr) 833{ 834 835 struct nxt200x_state* state = fe->demodulator_priv; 836 u8 b[2]; 837 u16 temp = 0, temp2; 838 u32 snrdb = 0; 839 840 /* setup to read cluster variance */ 841 b[0] = 0x00; 842 nxt200x_writebytes(state, 0xA1, b, 1); 843 844 /* get multreg val from 0xA6 */ 845 nxt200x_readreg_multibyte(state, 0xA6, b, 2); 846 847 temp = (b[0] << 8) | b[1]; 848 temp2 = 0x7FFF - temp; 849 850 /* snr will be in db */ 851 if (temp2 > 0x7F00) 852 snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) ); 853 else if (temp2 > 0x7EC0) 854 snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) ); 855 else if (temp2 > 0x7C00) 856 snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) ); 857 else 858 snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) ); 859 860 /* the value reported back from the frontend will be FFFF=32db 0000=0db */ 861 *snr = snrdb * (0xFFFF/32000); 862 863 return 0; 864} 865 866static int nxt200x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) 867{ 868 struct nxt200x_state* state = fe->demodulator_priv; 869 u8 b[3]; 870 871 nxt200x_readreg_multibyte(state, 0xE6, b, 3); 872 *ucblocks = b[2]; 873 874 return 0; 875} 876 877static int nxt200x_sleep(struct dvb_frontend* fe) 878{ 879 return 0; 880} 881 882static int nxt2002_init(struct dvb_frontend* fe) 883{ 884 struct nxt200x_state* state = fe->demodulator_priv; 885 const struct firmware *fw; 886 int ret; 887 u8 buf[2]; 888 889 /* request the firmware, this will block until someone uploads it */ 890 pr_debug("%s: Waiting for firmware upload (%s)...\n", 891 __func__, NXT2002_DEFAULT_FIRMWARE); 892 ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE, 893 state->i2c->dev.parent); 894 pr_debug("%s: Waiting for firmware upload(2)...\n", __func__); 895 if (ret) { 896 pr_err("%s: No firmware uploaded (timeout or file not found?)" 897 "\n", __func__); 898 return ret; 899 } 900 901 ret = nxt2002_load_firmware(fe, fw); 902 release_firmware(fw); 903 if (ret) { 904 pr_err("%s: Writing firmware to device failed\n", __func__); 905 return ret; 906 } 907 pr_info("%s: Firmware upload complete\n", __func__); 908 909 /* Put the micro into reset */ 910 nxt200x_microcontroller_stop(state); 911 912 /* ensure transfer is complete */ 913 buf[0]=0x00; 914 nxt200x_writebytes(state, 0x2B, buf, 1); 915 916 /* Put the micro into reset for real this time */ 917 nxt200x_microcontroller_stop(state); 918 919 /* soft reset everything (agc,frontend,eq,fec)*/ 920 buf[0] = 0x0F; 921 nxt200x_writebytes(state, 0x08, buf, 1); 922 buf[0] = 0x00; 923 nxt200x_writebytes(state, 0x08, buf, 1); 924 925 /* write agc sdm configure */ 926 buf[0] = 0xF1; 927 nxt200x_writebytes(state, 0x57, buf, 1); 928 929 /* write mod output format */ 930 buf[0] = 0x20; 931 nxt200x_writebytes(state, 0x09, buf, 1); 932 933 /* write fec mpeg mode */ 934 buf[0] = 0x7E; 935 buf[1] = 0x00; 936 nxt200x_writebytes(state, 0xE9, buf, 2); 937 938 /* write mux selection */ 939 buf[0] = 0x00; 940 nxt200x_writebytes(state, 0xCC, buf, 1); 941 942 return 0; 943} 944 945static int nxt2004_init(struct dvb_frontend* fe) 946{ 947 struct nxt200x_state* state = fe->demodulator_priv; 948 const struct firmware *fw; 949 int ret; 950 u8 buf[3]; 951 952 /* ??? */ 953 buf[0]=0x00; 954 nxt200x_writebytes(state, 0x1E, buf, 1); 955 956 /* request the firmware, this will block until someone uploads it */ 957 pr_debug("%s: Waiting for firmware upload (%s)...\n", 958 __func__, NXT2004_DEFAULT_FIRMWARE); 959 ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE, 960 state->i2c->dev.parent); 961 pr_debug("%s: Waiting for firmware upload(2)...\n", __func__); 962 if (ret) { 963 pr_err("%s: No firmware uploaded (timeout or file not found?)" 964 "\n", __func__); 965 return ret; 966 } 967 968 ret = nxt2004_load_firmware(fe, fw); 969 release_firmware(fw); 970 if (ret) { 971 pr_err("%s: Writing firmware to device failed\n", __func__); 972 return ret; 973 } 974 pr_info("%s: Firmware upload complete\n", __func__); 975 976 /* ensure transfer is complete */ 977 buf[0] = 0x01; 978 nxt200x_writebytes(state, 0x19, buf, 1); 979 980 nxt2004_microcontroller_init(state); 981 nxt200x_microcontroller_stop(state); 982 nxt200x_microcontroller_stop(state); 983 nxt2004_microcontroller_init(state); 984 nxt200x_microcontroller_stop(state); 985 986 /* soft reset everything (agc,frontend,eq,fec)*/ 987 buf[0] = 0xFF; 988 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 989 buf[0] = 0x00; 990 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 991 992 /* write agc sdm configure */ 993 buf[0] = 0xD7; 994 nxt200x_writebytes(state, 0x57, buf, 1); 995 996 /* ???*/ 997 buf[0] = 0x07; 998 buf[1] = 0xfe; 999 nxt200x_writebytes(state, 0x35, buf, 2); 1000 buf[0] = 0x12; 1001 nxt200x_writebytes(state, 0x34, buf, 1); 1002 buf[0] = 0x80; 1003 nxt200x_writebytes(state, 0x21, buf, 1); 1004 1005 /* ???*/ 1006 buf[0] = 0x21; 1007 nxt200x_writebytes(state, 0x0A, buf, 1); 1008 1009 /* ???*/ 1010 buf[0] = 0x01; 1011 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1012 1013 /* write fec mpeg mode */ 1014 buf[0] = 0x7E; 1015 buf[1] = 0x00; 1016 nxt200x_writebytes(state, 0xE9, buf, 2); 1017 1018 /* write mux selection */ 1019 buf[0] = 0x00; 1020 nxt200x_writebytes(state, 0xCC, buf, 1); 1021 1022 /* ???*/ 1023 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1024 buf[0] = 0x00; 1025 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1026 1027 /* soft reset? */ 1028 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1029 buf[0] = 0x10; 1030 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1031 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1032 buf[0] = 0x00; 1033 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1034 1035 /* ???*/ 1036 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1037 buf[0] = 0x01; 1038 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1039 buf[0] = 0x70; 1040 nxt200x_writereg_multibyte(state, 0x81, buf, 1); 1041 buf[0] = 0x31; buf[1] = 0x5E; buf[2] = 0x66; 1042 nxt200x_writereg_multibyte(state, 0x82, buf, 3); 1043 1044 nxt200x_readreg_multibyte(state, 0x88, buf, 1); 1045 buf[0] = 0x11; 1046 nxt200x_writereg_multibyte(state, 0x88, buf, 1); 1047 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1048 buf[0] = 0x40; 1049 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1050 1051 nxt200x_readbytes(state, 0x10, buf, 1); 1052 buf[0] = 0x10; 1053 nxt200x_writebytes(state, 0x10, buf, 1); 1054 nxt200x_readbytes(state, 0x0A, buf, 1); 1055 buf[0] = 0x21; 1056 nxt200x_writebytes(state, 0x0A, buf, 1); 1057 1058 nxt2004_microcontroller_init(state); 1059 1060 buf[0] = 0x21; 1061 nxt200x_writebytes(state, 0x0A, buf, 1); 1062 buf[0] = 0x7E; 1063 nxt200x_writebytes(state, 0xE9, buf, 1); 1064 buf[0] = 0x00; 1065 nxt200x_writebytes(state, 0xEA, buf, 1); 1066 1067 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1068 buf[0] = 0x00; 1069 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1070 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1071 buf[0] = 0x00; 1072 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1073 1074 /* soft reset? */ 1075 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1076 buf[0] = 0x10; 1077 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1078 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1079 buf[0] = 0x00; 1080 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1081 1082 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1083 buf[0] = 0x04; 1084 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1085 buf[0] = 0x00; 1086 nxt200x_writereg_multibyte(state, 0x81, buf, 1); 1087 buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00; 1088 nxt200x_writereg_multibyte(state, 0x82, buf, 3); 1089 1090 nxt200x_readreg_multibyte(state, 0x88, buf, 1); 1091 buf[0] = 0x11; 1092 nxt200x_writereg_multibyte(state, 0x88, buf, 1); 1093 1094 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1095 buf[0] = 0x44; 1096 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1097 1098 /* initialize tuner */ 1099 nxt200x_readbytes(state, 0x10, buf, 1); 1100 buf[0] = 0x12; 1101 nxt200x_writebytes(state, 0x10, buf, 1); 1102 buf[0] = 0x04; 1103 nxt200x_writebytes(state, 0x13, buf, 1); 1104 buf[0] = 0x00; 1105 nxt200x_writebytes(state, 0x16, buf, 1); 1106 buf[0] = 0x04; 1107 nxt200x_writebytes(state, 0x14, buf, 1); 1108 buf[0] = 0x00; 1109 nxt200x_writebytes(state, 0x14, buf, 1); 1110 nxt200x_writebytes(state, 0x17, buf, 1); 1111 nxt200x_writebytes(state, 0x14, buf, 1); 1112 nxt200x_writebytes(state, 0x17, buf, 1); 1113 1114 return 0; 1115} 1116 1117static int nxt200x_init(struct dvb_frontend* fe) 1118{ 1119 struct nxt200x_state* state = fe->demodulator_priv; 1120 int ret = 0; 1121 1122 if (!state->initialised) { 1123 switch (state->demod_chip) { 1124 case NXT2002: 1125 ret = nxt2002_init(fe); 1126 break; 1127 case NXT2004: 1128 ret = nxt2004_init(fe); 1129 break; 1130 default: 1131 return -EINVAL; 1132 break; 1133 } 1134 state->initialised = 1; 1135 } 1136 return ret; 1137} 1138 1139static int nxt200x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) 1140{ 1141 fesettings->min_delay_ms = 500; 1142 fesettings->step_size = 0; 1143 fesettings->max_drift = 0; 1144 return 0; 1145} 1146 1147static void nxt200x_release(struct dvb_frontend* fe) 1148{ 1149 struct nxt200x_state* state = fe->demodulator_priv; 1150 kfree(state); 1151} 1152 1153static struct dvb_frontend_ops nxt200x_ops; 1154 1155struct dvb_frontend* nxt200x_attach(const struct nxt200x_config* config, 1156 struct i2c_adapter* i2c) 1157{ 1158 struct nxt200x_state* state = NULL; 1159 u8 buf [] = {0,0,0,0,0}; 1160 1161 /* allocate memory for the internal state */ 1162 state = kzalloc(sizeof(struct nxt200x_state), GFP_KERNEL); 1163 if (state == NULL) 1164 goto error; 1165 1166 /* setup the state */ 1167 state->config = config; 1168 state->i2c = i2c; 1169 state->initialised = 0; 1170 1171 /* read card id */ 1172 nxt200x_readbytes(state, 0x00, buf, 5); 1173 dprintk("NXT info: %*ph\n", 5, buf); 1174 1175 /* set demod chip */ 1176 switch (buf[0]) { 1177 case 0x04: 1178 state->demod_chip = NXT2002; 1179 pr_info("NXT2002 Detected\n"); 1180 break; 1181 case 0x05: 1182 state->demod_chip = NXT2004; 1183 pr_info("NXT2004 Detected\n"); 1184 break; 1185 default: 1186 goto error; 1187 } 1188 1189 /* make sure demod chip is supported */ 1190 switch (state->demod_chip) { 1191 case NXT2002: 1192 if (buf[0] != 0x04) goto error; /* device id */ 1193 if (buf[1] != 0x02) goto error; /* fab id */ 1194 if (buf[2] != 0x11) goto error; /* month */ 1195 if (buf[3] != 0x20) goto error; /* year msb */ 1196 if (buf[4] != 0x00) goto error; /* year lsb */ 1197 break; 1198 case NXT2004: 1199 if (buf[0] != 0x05) goto error; /* device id */ 1200 break; 1201 default: 1202 goto error; 1203 } 1204 1205 /* create dvb_frontend */ 1206 memcpy(&state->frontend.ops, &nxt200x_ops, sizeof(struct dvb_frontend_ops)); 1207 state->frontend.demodulator_priv = state; 1208 return &state->frontend; 1209 1210error: 1211 kfree(state); 1212 pr_err("Unknown/Unsupported NXT chip: %*ph\n", 5, buf); 1213 return NULL; 1214} 1215 1216static struct dvb_frontend_ops nxt200x_ops = { 1217 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, 1218 .info = { 1219 .name = "Nextwave NXT200X VSB/QAM frontend", 1220 .frequency_min = 54000000, 1221 .frequency_max = 860000000, 1222 .frequency_stepsize = 166666, /* stepsize is just a guess */ 1223 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1224 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1225 FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256 1226 }, 1227 1228 .release = nxt200x_release, 1229 1230 .init = nxt200x_init, 1231 .sleep = nxt200x_sleep, 1232 1233 .set_frontend = nxt200x_setup_frontend_parameters, 1234 .get_tune_settings = nxt200x_get_tune_settings, 1235 1236 .read_status = nxt200x_read_status, 1237 .read_ber = nxt200x_read_ber, 1238 .read_signal_strength = nxt200x_read_signal_strength, 1239 .read_snr = nxt200x_read_snr, 1240 .read_ucblocks = nxt200x_read_ucblocks, 1241}; 1242 1243module_param(debug, int, 0644); 1244MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 1245 1246MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver"); 1247MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob"); 1248MODULE_LICENSE("GPL"); 1249 1250EXPORT_SYMBOL(nxt200x_attach); 1251 1252