1/* 2 STV0900/0903 Multistandard Broadcast Frontend driver 3 Copyright (C) Manu Abraham <abraham.manu@gmail.com> 4 5 Copyright (C) ST Microelectronics 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20*/ 21 22#include <linux/init.h> 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/string.h> 26#include <linux/slab.h> 27#include <linux/mutex.h> 28 29#include <linux/dvb/frontend.h> 30#include "dvb_frontend.h" 31 32#include "stv6110x.h" /* for demodulator internal modes */ 33 34#include "stv090x_reg.h" 35#include "stv090x.h" 36#include "stv090x_priv.h" 37 38/* Max transfer size done by I2C transfer functions */ 39#define MAX_XFER_SIZE 64 40 41static unsigned int verbose; 42module_param(verbose, int, 0644); 43 44/* internal params node */ 45struct stv090x_dev { 46 /* pointer for internal params, one for each pair of demods */ 47 struct stv090x_internal *internal; 48 struct stv090x_dev *next_dev; 49}; 50 51/* first internal params */ 52static struct stv090x_dev *stv090x_first_dev; 53 54/* find chip by i2c adapter and i2c address */ 55static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap, 56 u8 i2c_addr) 57{ 58 struct stv090x_dev *temp_dev = stv090x_first_dev; 59 60 /* 61 Search of the last stv0900 chip or 62 find it by i2c adapter and i2c address */ 63 while ((temp_dev != NULL) && 64 ((temp_dev->internal->i2c_adap != i2c_adap) || 65 (temp_dev->internal->i2c_addr != i2c_addr))) { 66 67 temp_dev = temp_dev->next_dev; 68 } 69 70 return temp_dev; 71} 72 73/* deallocating chip */ 74static void remove_dev(struct stv090x_internal *internal) 75{ 76 struct stv090x_dev *prev_dev = stv090x_first_dev; 77 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap, 78 internal->i2c_addr); 79 80 if (del_dev != NULL) { 81 if (del_dev == stv090x_first_dev) { 82 stv090x_first_dev = del_dev->next_dev; 83 } else { 84 while (prev_dev->next_dev != del_dev) 85 prev_dev = prev_dev->next_dev; 86 87 prev_dev->next_dev = del_dev->next_dev; 88 } 89 90 kfree(del_dev); 91 } 92} 93 94/* allocating new chip */ 95static struct stv090x_dev *append_internal(struct stv090x_internal *internal) 96{ 97 struct stv090x_dev *new_dev; 98 struct stv090x_dev *temp_dev; 99 100 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL); 101 if (new_dev != NULL) { 102 new_dev->internal = internal; 103 new_dev->next_dev = NULL; 104 105 /* append to list */ 106 if (stv090x_first_dev == NULL) { 107 stv090x_first_dev = new_dev; 108 } else { 109 temp_dev = stv090x_first_dev; 110 while (temp_dev->next_dev != NULL) 111 temp_dev = temp_dev->next_dev; 112 113 temp_dev->next_dev = new_dev; 114 } 115 } 116 117 return new_dev; 118} 119 120 121/* DVBS1 and DSS C/N Lookup table */ 122static const struct stv090x_tab stv090x_s1cn_tab[] = { 123 { 0, 8917 }, /* 0.0dB */ 124 { 5, 8801 }, /* 0.5dB */ 125 { 10, 8667 }, /* 1.0dB */ 126 { 15, 8522 }, /* 1.5dB */ 127 { 20, 8355 }, /* 2.0dB */ 128 { 25, 8175 }, /* 2.5dB */ 129 { 30, 7979 }, /* 3.0dB */ 130 { 35, 7763 }, /* 3.5dB */ 131 { 40, 7530 }, /* 4.0dB */ 132 { 45, 7282 }, /* 4.5dB */ 133 { 50, 7026 }, /* 5.0dB */ 134 { 55, 6781 }, /* 5.5dB */ 135 { 60, 6514 }, /* 6.0dB */ 136 { 65, 6241 }, /* 6.5dB */ 137 { 70, 5965 }, /* 7.0dB */ 138 { 75, 5690 }, /* 7.5dB */ 139 { 80, 5424 }, /* 8.0dB */ 140 { 85, 5161 }, /* 8.5dB */ 141 { 90, 4902 }, /* 9.0dB */ 142 { 95, 4654 }, /* 9.5dB */ 143 { 100, 4417 }, /* 10.0dB */ 144 { 105, 4186 }, /* 10.5dB */ 145 { 110, 3968 }, /* 11.0dB */ 146 { 115, 3757 }, /* 11.5dB */ 147 { 120, 3558 }, /* 12.0dB */ 148 { 125, 3366 }, /* 12.5dB */ 149 { 130, 3185 }, /* 13.0dB */ 150 { 135, 3012 }, /* 13.5dB */ 151 { 140, 2850 }, /* 14.0dB */ 152 { 145, 2698 }, /* 14.5dB */ 153 { 150, 2550 }, /* 15.0dB */ 154 { 160, 2283 }, /* 16.0dB */ 155 { 170, 2042 }, /* 17.0dB */ 156 { 180, 1827 }, /* 18.0dB */ 157 { 190, 1636 }, /* 19.0dB */ 158 { 200, 1466 }, /* 20.0dB */ 159 { 210, 1315 }, /* 21.0dB */ 160 { 220, 1181 }, /* 22.0dB */ 161 { 230, 1064 }, /* 23.0dB */ 162 { 240, 960 }, /* 24.0dB */ 163 { 250, 869 }, /* 25.0dB */ 164 { 260, 792 }, /* 26.0dB */ 165 { 270, 724 }, /* 27.0dB */ 166 { 280, 665 }, /* 28.0dB */ 167 { 290, 616 }, /* 29.0dB */ 168 { 300, 573 }, /* 30.0dB */ 169 { 310, 537 }, /* 31.0dB */ 170 { 320, 507 }, /* 32.0dB */ 171 { 330, 483 }, /* 33.0dB */ 172 { 400, 398 }, /* 40.0dB */ 173 { 450, 381 }, /* 45.0dB */ 174 { 500, 377 } /* 50.0dB */ 175}; 176 177/* DVBS2 C/N Lookup table */ 178static const struct stv090x_tab stv090x_s2cn_tab[] = { 179 { -30, 13348 }, /* -3.0dB */ 180 { -20, 12640 }, /* -2d.0B */ 181 { -10, 11883 }, /* -1.0dB */ 182 { 0, 11101 }, /* -0.0dB */ 183 { 5, 10718 }, /* 0.5dB */ 184 { 10, 10339 }, /* 1.0dB */ 185 { 15, 9947 }, /* 1.5dB */ 186 { 20, 9552 }, /* 2.0dB */ 187 { 25, 9183 }, /* 2.5dB */ 188 { 30, 8799 }, /* 3.0dB */ 189 { 35, 8422 }, /* 3.5dB */ 190 { 40, 8062 }, /* 4.0dB */ 191 { 45, 7707 }, /* 4.5dB */ 192 { 50, 7353 }, /* 5.0dB */ 193 { 55, 7025 }, /* 5.5dB */ 194 { 60, 6684 }, /* 6.0dB */ 195 { 65, 6331 }, /* 6.5dB */ 196 { 70, 6036 }, /* 7.0dB */ 197 { 75, 5727 }, /* 7.5dB */ 198 { 80, 5437 }, /* 8.0dB */ 199 { 85, 5164 }, /* 8.5dB */ 200 { 90, 4902 }, /* 9.0dB */ 201 { 95, 4653 }, /* 9.5dB */ 202 { 100, 4408 }, /* 10.0dB */ 203 { 105, 4187 }, /* 10.5dB */ 204 { 110, 3961 }, /* 11.0dB */ 205 { 115, 3751 }, /* 11.5dB */ 206 { 120, 3558 }, /* 12.0dB */ 207 { 125, 3368 }, /* 12.5dB */ 208 { 130, 3191 }, /* 13.0dB */ 209 { 135, 3017 }, /* 13.5dB */ 210 { 140, 2862 }, /* 14.0dB */ 211 { 145, 2710 }, /* 14.5dB */ 212 { 150, 2565 }, /* 15.0dB */ 213 { 160, 2300 }, /* 16.0dB */ 214 { 170, 2058 }, /* 17.0dB */ 215 { 180, 1849 }, /* 18.0dB */ 216 { 190, 1663 }, /* 19.0dB */ 217 { 200, 1495 }, /* 20.0dB */ 218 { 210, 1349 }, /* 21.0dB */ 219 { 220, 1222 }, /* 22.0dB */ 220 { 230, 1110 }, /* 23.0dB */ 221 { 240, 1011 }, /* 24.0dB */ 222 { 250, 925 }, /* 25.0dB */ 223 { 260, 853 }, /* 26.0dB */ 224 { 270, 789 }, /* 27.0dB */ 225 { 280, 734 }, /* 28.0dB */ 226 { 290, 690 }, /* 29.0dB */ 227 { 300, 650 }, /* 30.0dB */ 228 { 310, 619 }, /* 31.0dB */ 229 { 320, 593 }, /* 32.0dB */ 230 { 330, 571 }, /* 33.0dB */ 231 { 400, 498 }, /* 40.0dB */ 232 { 450, 484 }, /* 45.0dB */ 233 { 500, 481 } /* 50.0dB */ 234}; 235 236/* RF level C/N lookup table */ 237static const struct stv090x_tab stv090x_rf_tab[] = { 238 { -5, 0xcaa1 }, /* -5dBm */ 239 { -10, 0xc229 }, /* -10dBm */ 240 { -15, 0xbb08 }, /* -15dBm */ 241 { -20, 0xb4bc }, /* -20dBm */ 242 { -25, 0xad5a }, /* -25dBm */ 243 { -30, 0xa298 }, /* -30dBm */ 244 { -35, 0x98a8 }, /* -35dBm */ 245 { -40, 0x8389 }, /* -40dBm */ 246 { -45, 0x59be }, /* -45dBm */ 247 { -50, 0x3a14 }, /* -50dBm */ 248 { -55, 0x2d11 }, /* -55dBm */ 249 { -60, 0x210d }, /* -60dBm */ 250 { -65, 0xa14f }, /* -65dBm */ 251 { -70, 0x07aa } /* -70dBm */ 252}; 253 254 255static struct stv090x_reg stv0900_initval[] = { 256 257 { STV090x_OUTCFG, 0x00 }, 258 { STV090x_MODECFG, 0xff }, 259 { STV090x_AGCRF1CFG, 0x11 }, 260 { STV090x_AGCRF2CFG, 0x13 }, 261 { STV090x_TSGENERAL1X, 0x14 }, 262 { STV090x_TSTTNR2, 0x21 }, 263 { STV090x_TSTTNR4, 0x21 }, 264 { STV090x_P2_DISTXCTL, 0x22 }, 265 { STV090x_P2_F22TX, 0xc0 }, 266 { STV090x_P2_F22RX, 0xc0 }, 267 { STV090x_P2_DISRXCTL, 0x00 }, 268 { STV090x_P2_DMDCFGMD, 0xF9 }, 269 { STV090x_P2_DEMOD, 0x08 }, 270 { STV090x_P2_DMDCFG3, 0xc4 }, 271 { STV090x_P2_CARFREQ, 0xed }, 272 { STV090x_P2_LDT, 0xd0 }, 273 { STV090x_P2_LDT2, 0xb8 }, 274 { STV090x_P2_TMGCFG, 0xd2 }, 275 { STV090x_P2_TMGTHRISE, 0x20 }, 276 { STV090x_P1_TMGCFG, 0xd2 }, 277 278 { STV090x_P2_TMGTHFALL, 0x00 }, 279 { STV090x_P2_FECSPY, 0x88 }, 280 { STV090x_P2_FSPYDATA, 0x3a }, 281 { STV090x_P2_FBERCPT4, 0x00 }, 282 { STV090x_P2_FSPYBER, 0x10 }, 283 { STV090x_P2_ERRCTRL1, 0x35 }, 284 { STV090x_P2_ERRCTRL2, 0xc1 }, 285 { STV090x_P2_CFRICFG, 0xf8 }, 286 { STV090x_P2_NOSCFG, 0x1c }, 287 { STV090x_P2_DMDTOM, 0x20 }, 288 { STV090x_P2_CORRELMANT, 0x70 }, 289 { STV090x_P2_CORRELABS, 0x88 }, 290 { STV090x_P2_AGC2O, 0x5b }, 291 { STV090x_P2_AGC2REF, 0x38 }, 292 { STV090x_P2_CARCFG, 0xe4 }, 293 { STV090x_P2_ACLC, 0x1A }, 294 { STV090x_P2_BCLC, 0x09 }, 295 { STV090x_P2_CARHDR, 0x08 }, 296 { STV090x_P2_KREFTMG, 0xc1 }, 297 { STV090x_P2_SFRUPRATIO, 0xf0 }, 298 { STV090x_P2_SFRLOWRATIO, 0x70 }, 299 { STV090x_P2_SFRSTEP, 0x58 }, 300 { STV090x_P2_TMGCFG2, 0x01 }, 301 { STV090x_P2_CAR2CFG, 0x26 }, 302 { STV090x_P2_BCLC2S2Q, 0x86 }, 303 { STV090x_P2_BCLC2S28, 0x86 }, 304 { STV090x_P2_SMAPCOEF7, 0x77 }, 305 { STV090x_P2_SMAPCOEF6, 0x85 }, 306 { STV090x_P2_SMAPCOEF5, 0x77 }, 307 { STV090x_P2_TSCFGL, 0x20 }, 308 { STV090x_P2_DMDCFG2, 0x3b }, 309 { STV090x_P2_MODCODLST0, 0xff }, 310 { STV090x_P2_MODCODLST1, 0xff }, 311 { STV090x_P2_MODCODLST2, 0xff }, 312 { STV090x_P2_MODCODLST3, 0xff }, 313 { STV090x_P2_MODCODLST4, 0xff }, 314 { STV090x_P2_MODCODLST5, 0xff }, 315 { STV090x_P2_MODCODLST6, 0xff }, 316 { STV090x_P2_MODCODLST7, 0xcc }, 317 { STV090x_P2_MODCODLST8, 0xcc }, 318 { STV090x_P2_MODCODLST9, 0xcc }, 319 { STV090x_P2_MODCODLSTA, 0xcc }, 320 { STV090x_P2_MODCODLSTB, 0xcc }, 321 { STV090x_P2_MODCODLSTC, 0xcc }, 322 { STV090x_P2_MODCODLSTD, 0xcc }, 323 { STV090x_P2_MODCODLSTE, 0xcc }, 324 { STV090x_P2_MODCODLSTF, 0xcf }, 325 { STV090x_P1_DISTXCTL, 0x22 }, 326 { STV090x_P1_F22TX, 0xc0 }, 327 { STV090x_P1_F22RX, 0xc0 }, 328 { STV090x_P1_DISRXCTL, 0x00 }, 329 { STV090x_P1_DMDCFGMD, 0xf9 }, 330 { STV090x_P1_DEMOD, 0x08 }, 331 { STV090x_P1_DMDCFG3, 0xc4 }, 332 { STV090x_P1_DMDTOM, 0x20 }, 333 { STV090x_P1_CARFREQ, 0xed }, 334 { STV090x_P1_LDT, 0xd0 }, 335 { STV090x_P1_LDT2, 0xb8 }, 336 { STV090x_P1_TMGCFG, 0xd2 }, 337 { STV090x_P1_TMGTHRISE, 0x20 }, 338 { STV090x_P1_TMGTHFALL, 0x00 }, 339 { STV090x_P1_SFRUPRATIO, 0xf0 }, 340 { STV090x_P1_SFRLOWRATIO, 0x70 }, 341 { STV090x_P1_TSCFGL, 0x20 }, 342 { STV090x_P1_FECSPY, 0x88 }, 343 { STV090x_P1_FSPYDATA, 0x3a }, 344 { STV090x_P1_FBERCPT4, 0x00 }, 345 { STV090x_P1_FSPYBER, 0x10 }, 346 { STV090x_P1_ERRCTRL1, 0x35 }, 347 { STV090x_P1_ERRCTRL2, 0xc1 }, 348 { STV090x_P1_CFRICFG, 0xf8 }, 349 { STV090x_P1_NOSCFG, 0x1c }, 350 { STV090x_P1_CORRELMANT, 0x70 }, 351 { STV090x_P1_CORRELABS, 0x88 }, 352 { STV090x_P1_AGC2O, 0x5b }, 353 { STV090x_P1_AGC2REF, 0x38 }, 354 { STV090x_P1_CARCFG, 0xe4 }, 355 { STV090x_P1_ACLC, 0x1A }, 356 { STV090x_P1_BCLC, 0x09 }, 357 { STV090x_P1_CARHDR, 0x08 }, 358 { STV090x_P1_KREFTMG, 0xc1 }, 359 { STV090x_P1_SFRSTEP, 0x58 }, 360 { STV090x_P1_TMGCFG2, 0x01 }, 361 { STV090x_P1_CAR2CFG, 0x26 }, 362 { STV090x_P1_BCLC2S2Q, 0x86 }, 363 { STV090x_P1_BCLC2S28, 0x86 }, 364 { STV090x_P1_SMAPCOEF7, 0x77 }, 365 { STV090x_P1_SMAPCOEF6, 0x85 }, 366 { STV090x_P1_SMAPCOEF5, 0x77 }, 367 { STV090x_P1_DMDCFG2, 0x3b }, 368 { STV090x_P1_MODCODLST0, 0xff }, 369 { STV090x_P1_MODCODLST1, 0xff }, 370 { STV090x_P1_MODCODLST2, 0xff }, 371 { STV090x_P1_MODCODLST3, 0xff }, 372 { STV090x_P1_MODCODLST4, 0xff }, 373 { STV090x_P1_MODCODLST5, 0xff }, 374 { STV090x_P1_MODCODLST6, 0xff }, 375 { STV090x_P1_MODCODLST7, 0xcc }, 376 { STV090x_P1_MODCODLST8, 0xcc }, 377 { STV090x_P1_MODCODLST9, 0xcc }, 378 { STV090x_P1_MODCODLSTA, 0xcc }, 379 { STV090x_P1_MODCODLSTB, 0xcc }, 380 { STV090x_P1_MODCODLSTC, 0xcc }, 381 { STV090x_P1_MODCODLSTD, 0xcc }, 382 { STV090x_P1_MODCODLSTE, 0xcc }, 383 { STV090x_P1_MODCODLSTF, 0xcf }, 384 { STV090x_GENCFG, 0x1d }, 385 { STV090x_NBITER_NF4, 0x37 }, 386 { STV090x_NBITER_NF5, 0x29 }, 387 { STV090x_NBITER_NF6, 0x37 }, 388 { STV090x_NBITER_NF7, 0x33 }, 389 { STV090x_NBITER_NF8, 0x31 }, 390 { STV090x_NBITER_NF9, 0x2f }, 391 { STV090x_NBITER_NF10, 0x39 }, 392 { STV090x_NBITER_NF11, 0x3a }, 393 { STV090x_NBITER_NF12, 0x29 }, 394 { STV090x_NBITER_NF13, 0x37 }, 395 { STV090x_NBITER_NF14, 0x33 }, 396 { STV090x_NBITER_NF15, 0x2f }, 397 { STV090x_NBITER_NF16, 0x39 }, 398 { STV090x_NBITER_NF17, 0x3a }, 399 { STV090x_NBITERNOERR, 0x04 }, 400 { STV090x_GAINLLR_NF4, 0x0C }, 401 { STV090x_GAINLLR_NF5, 0x0F }, 402 { STV090x_GAINLLR_NF6, 0x11 }, 403 { STV090x_GAINLLR_NF7, 0x14 }, 404 { STV090x_GAINLLR_NF8, 0x17 }, 405 { STV090x_GAINLLR_NF9, 0x19 }, 406 { STV090x_GAINLLR_NF10, 0x20 }, 407 { STV090x_GAINLLR_NF11, 0x21 }, 408 { STV090x_GAINLLR_NF12, 0x0D }, 409 { STV090x_GAINLLR_NF13, 0x0F }, 410 { STV090x_GAINLLR_NF14, 0x13 }, 411 { STV090x_GAINLLR_NF15, 0x1A }, 412 { STV090x_GAINLLR_NF16, 0x1F }, 413 { STV090x_GAINLLR_NF17, 0x21 }, 414 { STV090x_RCCFGH, 0x20 }, 415 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */ 416 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */ 417 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */ 418 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */ 419}; 420 421static struct stv090x_reg stv0903_initval[] = { 422 { STV090x_OUTCFG, 0x00 }, 423 { STV090x_AGCRF1CFG, 0x11 }, 424 { STV090x_STOPCLK1, 0x48 }, 425 { STV090x_STOPCLK2, 0x14 }, 426 { STV090x_TSTTNR1, 0x27 }, 427 { STV090x_TSTTNR2, 0x21 }, 428 { STV090x_P1_DISTXCTL, 0x22 }, 429 { STV090x_P1_F22TX, 0xc0 }, 430 { STV090x_P1_F22RX, 0xc0 }, 431 { STV090x_P1_DISRXCTL, 0x00 }, 432 { STV090x_P1_DMDCFGMD, 0xF9 }, 433 { STV090x_P1_DEMOD, 0x08 }, 434 { STV090x_P1_DMDCFG3, 0xc4 }, 435 { STV090x_P1_CARFREQ, 0xed }, 436 { STV090x_P1_TNRCFG2, 0x82 }, 437 { STV090x_P1_LDT, 0xd0 }, 438 { STV090x_P1_LDT2, 0xb8 }, 439 { STV090x_P1_TMGCFG, 0xd2 }, 440 { STV090x_P1_TMGTHRISE, 0x20 }, 441 { STV090x_P1_TMGTHFALL, 0x00 }, 442 { STV090x_P1_SFRUPRATIO, 0xf0 }, 443 { STV090x_P1_SFRLOWRATIO, 0x70 }, 444 { STV090x_P1_TSCFGL, 0x20 }, 445 { STV090x_P1_FECSPY, 0x88 }, 446 { STV090x_P1_FSPYDATA, 0x3a }, 447 { STV090x_P1_FBERCPT4, 0x00 }, 448 { STV090x_P1_FSPYBER, 0x10 }, 449 { STV090x_P1_ERRCTRL1, 0x35 }, 450 { STV090x_P1_ERRCTRL2, 0xc1 }, 451 { STV090x_P1_CFRICFG, 0xf8 }, 452 { STV090x_P1_NOSCFG, 0x1c }, 453 { STV090x_P1_DMDTOM, 0x20 }, 454 { STV090x_P1_CORRELMANT, 0x70 }, 455 { STV090x_P1_CORRELABS, 0x88 }, 456 { STV090x_P1_AGC2O, 0x5b }, 457 { STV090x_P1_AGC2REF, 0x38 }, 458 { STV090x_P1_CARCFG, 0xe4 }, 459 { STV090x_P1_ACLC, 0x1A }, 460 { STV090x_P1_BCLC, 0x09 }, 461 { STV090x_P1_CARHDR, 0x08 }, 462 { STV090x_P1_KREFTMG, 0xc1 }, 463 { STV090x_P1_SFRSTEP, 0x58 }, 464 { STV090x_P1_TMGCFG2, 0x01 }, 465 { STV090x_P1_CAR2CFG, 0x26 }, 466 { STV090x_P1_BCLC2S2Q, 0x86 }, 467 { STV090x_P1_BCLC2S28, 0x86 }, 468 { STV090x_P1_SMAPCOEF7, 0x77 }, 469 { STV090x_P1_SMAPCOEF6, 0x85 }, 470 { STV090x_P1_SMAPCOEF5, 0x77 }, 471 { STV090x_P1_DMDCFG2, 0x3b }, 472 { STV090x_P1_MODCODLST0, 0xff }, 473 { STV090x_P1_MODCODLST1, 0xff }, 474 { STV090x_P1_MODCODLST2, 0xff }, 475 { STV090x_P1_MODCODLST3, 0xff }, 476 { STV090x_P1_MODCODLST4, 0xff }, 477 { STV090x_P1_MODCODLST5, 0xff }, 478 { STV090x_P1_MODCODLST6, 0xff }, 479 { STV090x_P1_MODCODLST7, 0xcc }, 480 { STV090x_P1_MODCODLST8, 0xcc }, 481 { STV090x_P1_MODCODLST9, 0xcc }, 482 { STV090x_P1_MODCODLSTA, 0xcc }, 483 { STV090x_P1_MODCODLSTB, 0xcc }, 484 { STV090x_P1_MODCODLSTC, 0xcc }, 485 { STV090x_P1_MODCODLSTD, 0xcc }, 486 { STV090x_P1_MODCODLSTE, 0xcc }, 487 { STV090x_P1_MODCODLSTF, 0xcf }, 488 { STV090x_GENCFG, 0x1c }, 489 { STV090x_NBITER_NF4, 0x37 }, 490 { STV090x_NBITER_NF5, 0x29 }, 491 { STV090x_NBITER_NF6, 0x37 }, 492 { STV090x_NBITER_NF7, 0x33 }, 493 { STV090x_NBITER_NF8, 0x31 }, 494 { STV090x_NBITER_NF9, 0x2f }, 495 { STV090x_NBITER_NF10, 0x39 }, 496 { STV090x_NBITER_NF11, 0x3a }, 497 { STV090x_NBITER_NF12, 0x29 }, 498 { STV090x_NBITER_NF13, 0x37 }, 499 { STV090x_NBITER_NF14, 0x33 }, 500 { STV090x_NBITER_NF15, 0x2f }, 501 { STV090x_NBITER_NF16, 0x39 }, 502 { STV090x_NBITER_NF17, 0x3a }, 503 { STV090x_NBITERNOERR, 0x04 }, 504 { STV090x_GAINLLR_NF4, 0x0C }, 505 { STV090x_GAINLLR_NF5, 0x0F }, 506 { STV090x_GAINLLR_NF6, 0x11 }, 507 { STV090x_GAINLLR_NF7, 0x14 }, 508 { STV090x_GAINLLR_NF8, 0x17 }, 509 { STV090x_GAINLLR_NF9, 0x19 }, 510 { STV090x_GAINLLR_NF10, 0x20 }, 511 { STV090x_GAINLLR_NF11, 0x21 }, 512 { STV090x_GAINLLR_NF12, 0x0D }, 513 { STV090x_GAINLLR_NF13, 0x0F }, 514 { STV090x_GAINLLR_NF14, 0x13 }, 515 { STV090x_GAINLLR_NF15, 0x1A }, 516 { STV090x_GAINLLR_NF16, 0x1F }, 517 { STV090x_GAINLLR_NF17, 0x21 }, 518 { STV090x_RCCFGH, 0x20 }, 519 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */ 520 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/ 521}; 522 523static struct stv090x_reg stv0900_cut20_val[] = { 524 525 { STV090x_P2_DMDCFG3, 0xe8 }, 526 { STV090x_P2_DMDCFG4, 0x10 }, 527 { STV090x_P2_CARFREQ, 0x38 }, 528 { STV090x_P2_CARHDR, 0x20 }, 529 { STV090x_P2_KREFTMG, 0x5a }, 530 { STV090x_P2_SMAPCOEF7, 0x06 }, 531 { STV090x_P2_SMAPCOEF6, 0x00 }, 532 { STV090x_P2_SMAPCOEF5, 0x04 }, 533 { STV090x_P2_NOSCFG, 0x0c }, 534 { STV090x_P1_DMDCFG3, 0xe8 }, 535 { STV090x_P1_DMDCFG4, 0x10 }, 536 { STV090x_P1_CARFREQ, 0x38 }, 537 { STV090x_P1_CARHDR, 0x20 }, 538 { STV090x_P1_KREFTMG, 0x5a }, 539 { STV090x_P1_SMAPCOEF7, 0x06 }, 540 { STV090x_P1_SMAPCOEF6, 0x00 }, 541 { STV090x_P1_SMAPCOEF5, 0x04 }, 542 { STV090x_P1_NOSCFG, 0x0c }, 543 { STV090x_GAINLLR_NF4, 0x21 }, 544 { STV090x_GAINLLR_NF5, 0x21 }, 545 { STV090x_GAINLLR_NF6, 0x20 }, 546 { STV090x_GAINLLR_NF7, 0x1F }, 547 { STV090x_GAINLLR_NF8, 0x1E }, 548 { STV090x_GAINLLR_NF9, 0x1E }, 549 { STV090x_GAINLLR_NF10, 0x1D }, 550 { STV090x_GAINLLR_NF11, 0x1B }, 551 { STV090x_GAINLLR_NF12, 0x20 }, 552 { STV090x_GAINLLR_NF13, 0x20 }, 553 { STV090x_GAINLLR_NF14, 0x20 }, 554 { STV090x_GAINLLR_NF15, 0x20 }, 555 { STV090x_GAINLLR_NF16, 0x20 }, 556 { STV090x_GAINLLR_NF17, 0x21 }, 557}; 558 559static struct stv090x_reg stv0903_cut20_val[] = { 560 { STV090x_P1_DMDCFG3, 0xe8 }, 561 { STV090x_P1_DMDCFG4, 0x10 }, 562 { STV090x_P1_CARFREQ, 0x38 }, 563 { STV090x_P1_CARHDR, 0x20 }, 564 { STV090x_P1_KREFTMG, 0x5a }, 565 { STV090x_P1_SMAPCOEF7, 0x06 }, 566 { STV090x_P1_SMAPCOEF6, 0x00 }, 567 { STV090x_P1_SMAPCOEF5, 0x04 }, 568 { STV090x_P1_NOSCFG, 0x0c }, 569 { STV090x_GAINLLR_NF4, 0x21 }, 570 { STV090x_GAINLLR_NF5, 0x21 }, 571 { STV090x_GAINLLR_NF6, 0x20 }, 572 { STV090x_GAINLLR_NF7, 0x1F }, 573 { STV090x_GAINLLR_NF8, 0x1E }, 574 { STV090x_GAINLLR_NF9, 0x1E }, 575 { STV090x_GAINLLR_NF10, 0x1D }, 576 { STV090x_GAINLLR_NF11, 0x1B }, 577 { STV090x_GAINLLR_NF12, 0x20 }, 578 { STV090x_GAINLLR_NF13, 0x20 }, 579 { STV090x_GAINLLR_NF14, 0x20 }, 580 { STV090x_GAINLLR_NF15, 0x20 }, 581 { STV090x_GAINLLR_NF16, 0x20 }, 582 { STV090x_GAINLLR_NF17, 0x21 } 583}; 584 585/* Cut 2.0 Long Frame Tracking CR loop */ 586static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = { 587 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 588 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e }, 589 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e }, 590 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d }, 591 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 592 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 593 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 594 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 595 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 596 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d }, 597 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d }, 598 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d }, 599 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, 600 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, 601 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d } 602}; 603 604/* Cut 3.0 Long Frame Tracking CR loop */ 605static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = { 606 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 607 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b }, 608 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 609 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 610 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 611 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 612 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 613 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 614 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 615 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 }, 616 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a }, 617 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a }, 618 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b }, 619 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b }, 620 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b } 621}; 622 623/* Cut 2.0 Long Frame Tracking CR Loop */ 624static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = { 625 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 626 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c }, 627 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c }, 628 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, 629 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, 630 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, 631 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, 632 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 633 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 634 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 635 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 636 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c } 637}; 638 639/* Cut 3.0 Long Frame Tracking CR Loop */ 640static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = { 641 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 642 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a }, 643 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a }, 644 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, 645 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, 646 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, 647 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, 648 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 649 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 650 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 651 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 652 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } 653}; 654 655static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = { 656 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 657 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e }, 658 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e }, 659 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e } 660}; 661 662static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = { 663 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 664 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b }, 665 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b }, 666 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b } 667}; 668 669/* Cut 2.0 Short Frame Tracking CR Loop */ 670static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = { 671 /* MODCOD 2M 5M 10M 20M 30M */ 672 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d }, 673 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c }, 674 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }, 675 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d } 676}; 677 678/* Cut 3.0 Short Frame Tracking CR Loop */ 679static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = { 680 /* MODCOD 2M 5M 10M 20M 30M */ 681 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A }, 682 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 }, 683 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }, 684 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A } 685}; 686 687static inline s32 comp2(s32 __x, s32 __width) 688{ 689 if (__width == 32) 690 return __x; 691 else 692 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x; 693} 694 695static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) 696{ 697 const struct stv090x_config *config = state->config; 698 int ret; 699 700 u8 b0[] = { reg >> 8, reg & 0xff }; 701 u8 buf; 702 703 struct i2c_msg msg[] = { 704 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, 705 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 } 706 }; 707 708 ret = i2c_transfer(state->i2c, msg, 2); 709 if (ret != 2) { 710 if (ret != -ERESTARTSYS) 711 dprintk(FE_ERROR, 1, 712 "Read error, Reg=[0x%02x], Status=%d", 713 reg, ret); 714 715 return ret < 0 ? ret : -EREMOTEIO; 716 } 717 if (unlikely(*state->verbose >= FE_DEBUGREG)) 718 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x", 719 reg, buf); 720 721 return (unsigned int) buf; 722} 723 724static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count) 725{ 726 const struct stv090x_config *config = state->config; 727 int ret; 728 u8 buf[MAX_XFER_SIZE]; 729 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count }; 730 731 if (2 + count > sizeof(buf)) { 732 printk(KERN_WARNING 733 "%s: i2c wr reg=%04x: len=%d is too big!\n", 734 KBUILD_MODNAME, reg, count); 735 return -EINVAL; 736 } 737 738 buf[0] = reg >> 8; 739 buf[1] = reg & 0xff; 740 memcpy(&buf[2], data, count); 741 742 if (unlikely(*state->verbose >= FE_DEBUGREG)) { 743 int i; 744 745 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg); 746 for (i = 0; i < count; i++) 747 printk(" %02x", data[i]); 748 printk("\n"); 749 } 750 751 ret = i2c_transfer(state->i2c, &i2c_msg, 1); 752 if (ret != 1) { 753 if (ret != -ERESTARTSYS) 754 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d", 755 reg, data[0], count, ret); 756 return ret < 0 ? ret : -EREMOTEIO; 757 } 758 759 return 0; 760} 761 762static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data) 763{ 764 return stv090x_write_regs(state, reg, &data, 1); 765} 766 767static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable) 768{ 769 u32 reg; 770 771 /* 772 * NOTE! A lock is used as a FSM to control the state in which 773 * access is serialized between two tuners on the same demod. 774 * This has nothing to do with a lock to protect a critical section 775 * which may in some other cases be confused with protecting I/O 776 * access to the demodulator gate. 777 * In case of any error, the lock is unlocked and exit within the 778 * relevant operations themselves. 779 */ 780 if (enable) { 781 if (state->config->tuner_i2c_lock) 782 state->config->tuner_i2c_lock(&state->frontend, 1); 783 else 784 mutex_lock(&state->internal->tuner_lock); 785 } 786 787 reg = STV090x_READ_DEMOD(state, I2CRPT); 788 if (enable) { 789 dprintk(FE_DEBUG, 1, "Enable Gate"); 790 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1); 791 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) 792 goto err; 793 794 } else { 795 dprintk(FE_DEBUG, 1, "Disable Gate"); 796 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0); 797 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0) 798 goto err; 799 } 800 801 if (!enable) { 802 if (state->config->tuner_i2c_lock) 803 state->config->tuner_i2c_lock(&state->frontend, 0); 804 else 805 mutex_unlock(&state->internal->tuner_lock); 806 } 807 808 return 0; 809err: 810 dprintk(FE_ERROR, 1, "I/O error"); 811 if (state->config->tuner_i2c_lock) 812 state->config->tuner_i2c_lock(&state->frontend, 0); 813 else 814 mutex_unlock(&state->internal->tuner_lock); 815 return -1; 816} 817 818static void stv090x_get_lock_tmg(struct stv090x_state *state) 819{ 820 switch (state->algo) { 821 case STV090x_BLIND_SEARCH: 822 dprintk(FE_DEBUG, 1, "Blind Search"); 823 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/ 824 state->DemodTimeout = 1500; 825 state->FecTimeout = 400; 826 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/ 827 state->DemodTimeout = 1000; 828 state->FecTimeout = 300; 829 } else { /*SR >20Msps*/ 830 state->DemodTimeout = 700; 831 state->FecTimeout = 100; 832 } 833 break; 834 835 case STV090x_COLD_SEARCH: 836 case STV090x_WARM_SEARCH: 837 default: 838 dprintk(FE_DEBUG, 1, "Normal Search"); 839 if (state->srate <= 1000000) { /*SR <=1Msps*/ 840 state->DemodTimeout = 4500; 841 state->FecTimeout = 1700; 842 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */ 843 state->DemodTimeout = 2500; 844 state->FecTimeout = 1100; 845 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */ 846 state->DemodTimeout = 1000; 847 state->FecTimeout = 550; 848 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */ 849 state->DemodTimeout = 700; 850 state->FecTimeout = 250; 851 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */ 852 state->DemodTimeout = 400; 853 state->FecTimeout = 130; 854 } else { /*SR >20Msps*/ 855 state->DemodTimeout = 300; 856 state->FecTimeout = 100; 857 } 858 break; 859 } 860 861 if (state->algo == STV090x_WARM_SEARCH) 862 state->DemodTimeout /= 2; 863} 864 865static int stv090x_set_srate(struct stv090x_state *state, u32 srate) 866{ 867 u32 sym; 868 869 if (srate > 60000000) { 870 sym = (srate << 4); /* SR * 2^16 / master_clk */ 871 sym /= (state->internal->mclk >> 12); 872 } else if (srate > 6000000) { 873 sym = (srate << 6); 874 sym /= (state->internal->mclk >> 10); 875 } else { 876 sym = (srate << 9); 877 sym /= (state->internal->mclk >> 7); 878 } 879 880 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */ 881 goto err; 882 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */ 883 goto err; 884 885 return 0; 886err: 887 dprintk(FE_ERROR, 1, "I/O error"); 888 return -1; 889} 890 891static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate) 892{ 893 u32 sym; 894 895 srate = 105 * (srate / 100); 896 if (srate > 60000000) { 897 sym = (srate << 4); /* SR * 2^16 / master_clk */ 898 sym /= (state->internal->mclk >> 12); 899 } else if (srate > 6000000) { 900 sym = (srate << 6); 901 sym /= (state->internal->mclk >> 10); 902 } else { 903 sym = (srate << 9); 904 sym /= (state->internal->mclk >> 7); 905 } 906 907 if (sym < 0x7fff) { 908 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */ 909 goto err; 910 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */ 911 goto err; 912 } else { 913 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */ 914 goto err; 915 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */ 916 goto err; 917 } 918 919 return 0; 920err: 921 dprintk(FE_ERROR, 1, "I/O error"); 922 return -1; 923} 924 925static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate) 926{ 927 u32 sym; 928 929 srate = 95 * (srate / 100); 930 if (srate > 60000000) { 931 sym = (srate << 4); /* SR * 2^16 / master_clk */ 932 sym /= (state->internal->mclk >> 12); 933 } else if (srate > 6000000) { 934 sym = (srate << 6); 935 sym /= (state->internal->mclk >> 10); 936 } else { 937 sym = (srate << 9); 938 sym /= (state->internal->mclk >> 7); 939 } 940 941 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */ 942 goto err; 943 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */ 944 goto err; 945 return 0; 946err: 947 dprintk(FE_ERROR, 1, "I/O error"); 948 return -1; 949} 950 951static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff) 952{ 953 u32 ro; 954 955 switch (rolloff) { 956 case STV090x_RO_20: 957 ro = 20; 958 break; 959 case STV090x_RO_25: 960 ro = 25; 961 break; 962 case STV090x_RO_35: 963 default: 964 ro = 35; 965 break; 966 } 967 968 return srate + (srate * ro) / 100; 969} 970 971static int stv090x_set_vit_thacq(struct stv090x_state *state) 972{ 973 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0) 974 goto err; 975 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0) 976 goto err; 977 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0) 978 goto err; 979 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0) 980 goto err; 981 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0) 982 goto err; 983 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0) 984 goto err; 985 return 0; 986err: 987 dprintk(FE_ERROR, 1, "I/O error"); 988 return -1; 989} 990 991static int stv090x_set_vit_thtracq(struct stv090x_state *state) 992{ 993 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0) 994 goto err; 995 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0) 996 goto err; 997 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0) 998 goto err; 999 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0) 1000 goto err; 1001 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0) 1002 goto err; 1003 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0) 1004 goto err; 1005 return 0; 1006err: 1007 dprintk(FE_ERROR, 1, "I/O error"); 1008 return -1; 1009} 1010 1011static int stv090x_set_viterbi(struct stv090x_state *state) 1012{ 1013 switch (state->search_mode) { 1014 case STV090x_SEARCH_AUTO: 1015 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */ 1016 goto err; 1017 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */ 1018 goto err; 1019 break; 1020 case STV090x_SEARCH_DVBS1: 1021 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */ 1022 goto err; 1023 switch (state->fec) { 1024 case STV090x_PR12: 1025 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) 1026 goto err; 1027 break; 1028 1029 case STV090x_PR23: 1030 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) 1031 goto err; 1032 break; 1033 1034 case STV090x_PR34: 1035 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0) 1036 goto err; 1037 break; 1038 1039 case STV090x_PR56: 1040 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0) 1041 goto err; 1042 break; 1043 1044 case STV090x_PR78: 1045 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0) 1046 goto err; 1047 break; 1048 1049 default: 1050 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */ 1051 goto err; 1052 break; 1053 } 1054 break; 1055 case STV090x_SEARCH_DSS: 1056 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0) 1057 goto err; 1058 switch (state->fec) { 1059 case STV090x_PR12: 1060 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) 1061 goto err; 1062 break; 1063 1064 case STV090x_PR23: 1065 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) 1066 goto err; 1067 break; 1068 1069 case STV090x_PR67: 1070 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0) 1071 goto err; 1072 break; 1073 1074 default: 1075 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */ 1076 goto err; 1077 break; 1078 } 1079 break; 1080 default: 1081 break; 1082 } 1083 return 0; 1084err: 1085 dprintk(FE_ERROR, 1, "I/O error"); 1086 return -1; 1087} 1088 1089static int stv090x_stop_modcod(struct stv090x_state *state) 1090{ 1091 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1092 goto err; 1093 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) 1094 goto err; 1095 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) 1096 goto err; 1097 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) 1098 goto err; 1099 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) 1100 goto err; 1101 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) 1102 goto err; 1103 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) 1104 goto err; 1105 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0) 1106 goto err; 1107 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0) 1108 goto err; 1109 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0) 1110 goto err; 1111 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0) 1112 goto err; 1113 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0) 1114 goto err; 1115 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0) 1116 goto err; 1117 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0) 1118 goto err; 1119 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) 1120 goto err; 1121 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0) 1122 goto err; 1123 return 0; 1124err: 1125 dprintk(FE_ERROR, 1, "I/O error"); 1126 return -1; 1127} 1128 1129static int stv090x_activate_modcod(struct stv090x_state *state) 1130{ 1131 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1132 goto err; 1133 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0) 1134 goto err; 1135 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0) 1136 goto err; 1137 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0) 1138 goto err; 1139 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0) 1140 goto err; 1141 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0) 1142 goto err; 1143 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0) 1144 goto err; 1145 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) 1146 goto err; 1147 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) 1148 goto err; 1149 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) 1150 goto err; 1151 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) 1152 goto err; 1153 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) 1154 goto err; 1155 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) 1156 goto err; 1157 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) 1158 goto err; 1159 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0) 1160 goto err; 1161 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) 1162 goto err; 1163 1164 return 0; 1165err: 1166 dprintk(FE_ERROR, 1, "I/O error"); 1167 return -1; 1168} 1169 1170static int stv090x_activate_modcod_single(struct stv090x_state *state) 1171{ 1172 1173 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1174 goto err; 1175 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0) 1176 goto err; 1177 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0) 1178 goto err; 1179 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0) 1180 goto err; 1181 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0) 1182 goto err; 1183 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0) 1184 goto err; 1185 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0) 1186 goto err; 1187 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0) 1188 goto err; 1189 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0) 1190 goto err; 1191 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0) 1192 goto err; 1193 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0) 1194 goto err; 1195 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0) 1196 goto err; 1197 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0) 1198 goto err; 1199 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0) 1200 goto err; 1201 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0) 1202 goto err; 1203 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0) 1204 goto err; 1205 1206 return 0; 1207 1208err: 1209 dprintk(FE_ERROR, 1, "I/O error"); 1210 return -1; 1211} 1212 1213static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable) 1214{ 1215 u32 reg; 1216 1217 switch (state->demod) { 1218 case STV090x_DEMODULATOR_0: 1219 mutex_lock(&state->internal->demod_lock); 1220 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 1221 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable); 1222 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 1223 goto err; 1224 mutex_unlock(&state->internal->demod_lock); 1225 break; 1226 1227 case STV090x_DEMODULATOR_1: 1228 mutex_lock(&state->internal->demod_lock); 1229 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 1230 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable); 1231 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 1232 goto err; 1233 mutex_unlock(&state->internal->demod_lock); 1234 break; 1235 1236 default: 1237 dprintk(FE_ERROR, 1, "Wrong demodulator!"); 1238 break; 1239 } 1240 return 0; 1241err: 1242 mutex_unlock(&state->internal->demod_lock); 1243 dprintk(FE_ERROR, 1, "I/O error"); 1244 return -1; 1245} 1246 1247static int stv090x_dvbs_track_crl(struct stv090x_state *state) 1248{ 1249 if (state->internal->dev_ver >= 0x30) { 1250 /* Set ACLC BCLC optimised value vs SR */ 1251 if (state->srate >= 15000000) { 1252 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0) 1253 goto err; 1254 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0) 1255 goto err; 1256 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) { 1257 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0) 1258 goto err; 1259 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0) 1260 goto err; 1261 } else if (state->srate < 7000000) { 1262 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0) 1263 goto err; 1264 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0) 1265 goto err; 1266 } 1267 1268 } else { 1269 /* Cut 2.0 */ 1270 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) 1271 goto err; 1272 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) 1273 goto err; 1274 } 1275 return 0; 1276err: 1277 dprintk(FE_ERROR, 1, "I/O error"); 1278 return -1; 1279} 1280 1281static int stv090x_delivery_search(struct stv090x_state *state) 1282{ 1283 u32 reg; 1284 1285 switch (state->search_mode) { 1286 case STV090x_SEARCH_DVBS1: 1287 case STV090x_SEARCH_DSS: 1288 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1289 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1290 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1291 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1292 goto err; 1293 1294 /* Activate Viterbi decoder in legacy search, 1295 * do not use FRESVIT1, might impact VITERBI2 1296 */ 1297 if (stv090x_vitclk_ctl(state, 0) < 0) 1298 goto err; 1299 1300 if (stv090x_dvbs_track_crl(state) < 0) 1301 goto err; 1302 1303 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */ 1304 goto err; 1305 1306 if (stv090x_set_vit_thacq(state) < 0) 1307 goto err; 1308 if (stv090x_set_viterbi(state) < 0) 1309 goto err; 1310 break; 1311 1312 case STV090x_SEARCH_DVBS2: 1313 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1314 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 1315 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1316 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1317 goto err; 1318 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1319 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 1320 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1321 goto err; 1322 1323 if (stv090x_vitclk_ctl(state, 1) < 0) 1324 goto err; 1325 1326 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */ 1327 goto err; 1328 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) 1329 goto err; 1330 1331 if (state->internal->dev_ver <= 0x20) { 1332 /* enable S2 carrier loop */ 1333 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) 1334 goto err; 1335 } else { 1336 /* > Cut 3: Stop carrier 3 */ 1337 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) 1338 goto err; 1339 } 1340 1341 if (state->demod_mode != STV090x_SINGLE) { 1342 /* Cut 2: enable link during search */ 1343 if (stv090x_activate_modcod(state) < 0) 1344 goto err; 1345 } else { 1346 /* Single demodulator 1347 * Authorize SHORT and LONG frames, 1348 * QPSK, 8PSK, 16APSK and 32APSK 1349 */ 1350 if (stv090x_activate_modcod_single(state) < 0) 1351 goto err; 1352 } 1353 1354 if (stv090x_set_vit_thtracq(state) < 0) 1355 goto err; 1356 break; 1357 1358 case STV090x_SEARCH_AUTO: 1359 default: 1360 /* enable DVB-S2 and DVB-S2 in Auto MODE */ 1361 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1362 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 1363 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1364 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1365 goto err; 1366 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1367 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 1368 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1369 goto err; 1370 1371 if (stv090x_vitclk_ctl(state, 0) < 0) 1372 goto err; 1373 1374 if (stv090x_dvbs_track_crl(state) < 0) 1375 goto err; 1376 1377 if (state->internal->dev_ver <= 0x20) { 1378 /* enable S2 carrier loop */ 1379 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) 1380 goto err; 1381 } else { 1382 /* > Cut 3: Stop carrier 3 */ 1383 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) 1384 goto err; 1385 } 1386 1387 if (state->demod_mode != STV090x_SINGLE) { 1388 /* Cut 2: enable link during search */ 1389 if (stv090x_activate_modcod(state) < 0) 1390 goto err; 1391 } else { 1392 /* Single demodulator 1393 * Authorize SHORT and LONG frames, 1394 * QPSK, 8PSK, 16APSK and 32APSK 1395 */ 1396 if (stv090x_activate_modcod_single(state) < 0) 1397 goto err; 1398 } 1399 1400 if (stv090x_set_vit_thacq(state) < 0) 1401 goto err; 1402 1403 if (stv090x_set_viterbi(state) < 0) 1404 goto err; 1405 break; 1406 } 1407 return 0; 1408err: 1409 dprintk(FE_ERROR, 1, "I/O error"); 1410 return -1; 1411} 1412 1413static int stv090x_start_search(struct stv090x_state *state) 1414{ 1415 u32 reg, freq_abs; 1416 s16 freq; 1417 1418 /* Reset demodulator */ 1419 reg = STV090x_READ_DEMOD(state, DMDISTATE); 1420 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); 1421 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) 1422 goto err; 1423 1424 if (state->internal->dev_ver <= 0x20) { 1425 if (state->srate <= 5000000) { 1426 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0) 1427 goto err; 1428 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0) 1429 goto err; 1430 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0) 1431 goto err; 1432 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0) 1433 goto err; 1434 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0) 1435 goto err; 1436 1437 /*enlarge the timing bandwidth for Low SR*/ 1438 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) 1439 goto err; 1440 } else { 1441 /* If the symbol rate is >5 Msps 1442 Set The carrier search up and low to auto mode */ 1443 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) 1444 goto err; 1445 /*reduce the timing bandwidth for high SR*/ 1446 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) 1447 goto err; 1448 } 1449 } else { 1450 /* >= Cut 3 */ 1451 if (state->srate <= 5000000) { 1452 /* enlarge the timing bandwidth for Low SR */ 1453 STV090x_WRITE_DEMOD(state, RTCS2, 0x68); 1454 } else { 1455 /* reduce timing bandwidth for high SR */ 1456 STV090x_WRITE_DEMOD(state, RTCS2, 0x44); 1457 } 1458 1459 /* Set CFR min and max to manual mode */ 1460 STV090x_WRITE_DEMOD(state, CARCFG, 0x46); 1461 1462 if (state->algo == STV090x_WARM_SEARCH) { 1463 /* WARM Start 1464 * CFR min = -1MHz, 1465 * CFR max = +1MHz 1466 */ 1467 freq_abs = 1000 << 16; 1468 freq_abs /= (state->internal->mclk / 1000); 1469 freq = (s16) freq_abs; 1470 } else { 1471 /* COLD Start 1472 * CFR min =- (SearchRange / 2 + 600KHz) 1473 * CFR max = +(SearchRange / 2 + 600KHz) 1474 * (600KHz for the tuner step size) 1475 */ 1476 freq_abs = (state->search_range / 2000) + 600; 1477 freq_abs = freq_abs << 16; 1478 freq_abs /= (state->internal->mclk / 1000); 1479 freq = (s16) freq_abs; 1480 } 1481 1482 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0) 1483 goto err; 1484 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0) 1485 goto err; 1486 1487 freq *= -1; 1488 1489 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0) 1490 goto err; 1491 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0) 1492 goto err; 1493 1494 } 1495 1496 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0) 1497 goto err; 1498 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0) 1499 goto err; 1500 1501 if (state->internal->dev_ver >= 0x20) { 1502 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) 1503 goto err; 1504 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) 1505 goto err; 1506 1507 if ((state->search_mode == STV090x_SEARCH_DVBS1) || 1508 (state->search_mode == STV090x_SEARCH_DSS) || 1509 (state->search_mode == STV090x_SEARCH_AUTO)) { 1510 1511 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) 1512 goto err; 1513 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) 1514 goto err; 1515 } 1516 } 1517 1518 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0) 1519 goto err; 1520 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0) 1521 goto err; 1522 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0) 1523 goto err; 1524 1525 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1526 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); 1527 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1528 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1529 goto err; 1530 reg = STV090x_READ_DEMOD(state, DMDCFG2); 1531 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0); 1532 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0) 1533 goto err; 1534 1535 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) 1536 goto err; 1537 1538 if (state->internal->dev_ver >= 0x20) { 1539 /*Frequency offset detector setting*/ 1540 if (state->srate < 2000000) { 1541 if (state->internal->dev_ver <= 0x20) { 1542 /* Cut 2 */ 1543 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0) 1544 goto err; 1545 } else { 1546 /* Cut 3 */ 1547 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0) 1548 goto err; 1549 } 1550 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0) 1551 goto err; 1552 } else if (state->srate < 10000000) { 1553 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0) 1554 goto err; 1555 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) 1556 goto err; 1557 } else { 1558 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0) 1559 goto err; 1560 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) 1561 goto err; 1562 } 1563 } else { 1564 if (state->srate < 10000000) { 1565 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0) 1566 goto err; 1567 } else { 1568 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0) 1569 goto err; 1570 } 1571 } 1572 1573 switch (state->algo) { 1574 case STV090x_WARM_SEARCH: 1575 /* The symbol rate and the exact 1576 * carrier Frequency are known 1577 */ 1578 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 1579 goto err; 1580 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 1581 goto err; 1582 break; 1583 1584 case STV090x_COLD_SEARCH: 1585 /* The symbol rate is known */ 1586 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 1587 goto err; 1588 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 1589 goto err; 1590 break; 1591 1592 default: 1593 break; 1594 } 1595 return 0; 1596err: 1597 dprintk(FE_ERROR, 1, "I/O error"); 1598 return -1; 1599} 1600 1601static int stv090x_get_agc2_min_level(struct stv090x_state *state) 1602{ 1603 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg; 1604 s32 i, j, steps, dir; 1605 1606 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 1607 goto err; 1608 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1609 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); 1610 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1611 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1612 goto err; 1613 1614 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */ 1615 goto err; 1616 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) 1617 goto err; 1618 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */ 1619 goto err; 1620 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) 1621 goto err; 1622 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */ 1623 goto err; 1624 if (stv090x_set_srate(state, 1000000) < 0) 1625 goto err; 1626 1627 steps = state->search_range / 1000000; 1628 if (steps <= 0) 1629 steps = 1; 1630 1631 dir = 1; 1632 freq_step = (1000000 * 256) / (state->internal->mclk / 256); 1633 freq_init = 0; 1634 1635 for (i = 0; i < steps; i++) { 1636 if (dir > 0) 1637 freq_init = freq_init + (freq_step * i); 1638 else 1639 freq_init = freq_init - (freq_step * i); 1640 1641 dir *= -1; 1642 1643 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */ 1644 goto err; 1645 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0) 1646 goto err; 1647 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0) 1648 goto err; 1649 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */ 1650 goto err; 1651 msleep(10); 1652 1653 agc2 = 0; 1654 for (j = 0; j < 10; j++) { 1655 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 1656 STV090x_READ_DEMOD(state, AGC2I0); 1657 } 1658 agc2 /= 10; 1659 if (agc2 < agc2_min) 1660 agc2_min = agc2; 1661 } 1662 1663 return agc2_min; 1664err: 1665 dprintk(FE_ERROR, 1, "I/O error"); 1666 return -1; 1667} 1668 1669static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk) 1670{ 1671 u8 r3, r2, r1, r0; 1672 s32 srate, int_1, int_2, tmp_1, tmp_2; 1673 1674 r3 = STV090x_READ_DEMOD(state, SFR3); 1675 r2 = STV090x_READ_DEMOD(state, SFR2); 1676 r1 = STV090x_READ_DEMOD(state, SFR1); 1677 r0 = STV090x_READ_DEMOD(state, SFR0); 1678 1679 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0); 1680 1681 int_1 = clk >> 16; 1682 int_2 = srate >> 16; 1683 1684 tmp_1 = clk % 0x10000; 1685 tmp_2 = srate % 0x10000; 1686 1687 srate = (int_1 * int_2) + 1688 ((int_1 * tmp_2) >> 16) + 1689 ((int_2 * tmp_1) >> 16); 1690 1691 return srate; 1692} 1693 1694static u32 stv090x_srate_srch_coarse(struct stv090x_state *state) 1695{ 1696 struct dvb_frontend *fe = &state->frontend; 1697 1698 int tmg_lock = 0, i; 1699 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq; 1700 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg; 1701 u32 agc2th; 1702 1703 if (state->internal->dev_ver >= 0x30) 1704 agc2th = 0x2e00; 1705 else 1706 agc2th = 0x1f00; 1707 1708 reg = STV090x_READ_DEMOD(state, DMDISTATE); 1709 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */ 1710 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) 1711 goto err; 1712 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0) 1713 goto err; 1714 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) 1715 goto err; 1716 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0) 1717 goto err; 1718 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0) 1719 goto err; 1720 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1721 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1); 1722 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1723 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1724 goto err; 1725 1726 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) 1727 goto err; 1728 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) 1729 goto err; 1730 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) 1731 goto err; 1732 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) 1733 goto err; 1734 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) 1735 goto err; 1736 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0) 1737 goto err; 1738 1739 if (state->internal->dev_ver >= 0x30) { 1740 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0) 1741 goto err; 1742 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0) 1743 goto err; 1744 1745 } else if (state->internal->dev_ver >= 0x20) { 1746 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0) 1747 goto err; 1748 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0) 1749 goto err; 1750 } 1751 1752 if (state->srate <= 2000000) 1753 car_step = 1000; 1754 else if (state->srate <= 5000000) 1755 car_step = 2000; 1756 else if (state->srate <= 12000000) 1757 car_step = 3000; 1758 else 1759 car_step = 5000; 1760 1761 steps = -1 + ((state->search_range / 1000) / car_step); 1762 steps /= 2; 1763 steps = (2 * steps) + 1; 1764 if (steps < 0) 1765 steps = 1; 1766 else if (steps > 10) { 1767 steps = 11; 1768 car_step = (state->search_range / 1000) / 10; 1769 } 1770 cur_step = 0; 1771 dir = 1; 1772 freq = state->frequency; 1773 1774 while ((!tmg_lock) && (cur_step < steps)) { 1775 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */ 1776 goto err; 1777 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) 1778 goto err; 1779 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 1780 goto err; 1781 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0) 1782 goto err; 1783 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0) 1784 goto err; 1785 /* trigger acquisition */ 1786 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0) 1787 goto err; 1788 msleep(50); 1789 for (i = 0; i < 10; i++) { 1790 reg = STV090x_READ_DEMOD(state, DSTATUS); 1791 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) 1792 tmg_cpt++; 1793 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 1794 STV090x_READ_DEMOD(state, AGC2I0); 1795 } 1796 agc2 /= 10; 1797 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1798 cur_step++; 1799 dir *= -1; 1800 if ((tmg_cpt >= 5) && (agc2 < agc2th) && 1801 (srate_coarse < 50000000) && (srate_coarse > 850000)) 1802 tmg_lock = 1; 1803 else if (cur_step < steps) { 1804 if (dir > 0) 1805 freq += cur_step * car_step; 1806 else 1807 freq -= cur_step * car_step; 1808 1809 /* Setup tuner */ 1810 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 1811 goto err; 1812 1813 if (state->config->tuner_set_frequency) { 1814 if (state->config->tuner_set_frequency(fe, freq) < 0) 1815 goto err_gateoff; 1816 } 1817 1818 if (state->config->tuner_set_bandwidth) { 1819 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 1820 goto err_gateoff; 1821 } 1822 1823 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 1824 goto err; 1825 1826 msleep(50); 1827 1828 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 1829 goto err; 1830 1831 if (state->config->tuner_get_status) { 1832 if (state->config->tuner_get_status(fe, ®) < 0) 1833 goto err_gateoff; 1834 } 1835 1836 if (reg) 1837 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 1838 else 1839 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 1840 1841 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 1842 goto err; 1843 1844 } 1845 } 1846 if (!tmg_lock) 1847 srate_coarse = 0; 1848 else 1849 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1850 1851 return srate_coarse; 1852 1853err_gateoff: 1854 stv090x_i2c_gate_ctrl(state, 0); 1855err: 1856 dprintk(FE_ERROR, 1, "I/O error"); 1857 return -1; 1858} 1859 1860static u32 stv090x_srate_srch_fine(struct stv090x_state *state) 1861{ 1862 u32 srate_coarse, freq_coarse, sym, reg; 1863 1864 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1865 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8; 1866 freq_coarse |= STV090x_READ_DEMOD(state, CFR1); 1867 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1868 1869 if (sym < state->srate) 1870 srate_coarse = 0; 1871 else { 1872 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */ 1873 goto err; 1874 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) 1875 goto err; 1876 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) 1877 goto err; 1878 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) 1879 goto err; 1880 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) 1881 goto err; 1882 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1883 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); 1884 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1885 goto err; 1886 1887 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 1888 goto err; 1889 1890 if (state->internal->dev_ver >= 0x30) { 1891 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0) 1892 goto err; 1893 } else if (state->internal->dev_ver >= 0x20) { 1894 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 1895 goto err; 1896 } 1897 1898 if (srate_coarse > 3000000) { 1899 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1900 sym = (sym / 1000) * 65536; 1901 sym /= (state->internal->mclk / 1000); 1902 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) 1903 goto err; 1904 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) 1905 goto err; 1906 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */ 1907 sym = (sym / 1000) * 65536; 1908 sym /= (state->internal->mclk / 1000); 1909 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) 1910 goto err; 1911 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) 1912 goto err; 1913 sym = (srate_coarse / 1000) * 65536; 1914 sym /= (state->internal->mclk / 1000); 1915 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) 1916 goto err; 1917 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) 1918 goto err; 1919 } else { 1920 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1921 sym = (sym / 100) * 65536; 1922 sym /= (state->internal->mclk / 100); 1923 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) 1924 goto err; 1925 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) 1926 goto err; 1927 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */ 1928 sym = (sym / 100) * 65536; 1929 sym /= (state->internal->mclk / 100); 1930 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) 1931 goto err; 1932 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) 1933 goto err; 1934 sym = (srate_coarse / 100) * 65536; 1935 sym /= (state->internal->mclk / 100); 1936 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) 1937 goto err; 1938 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) 1939 goto err; 1940 } 1941 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) 1942 goto err; 1943 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0) 1944 goto err; 1945 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0) 1946 goto err; 1947 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */ 1948 goto err; 1949 } 1950 1951 return srate_coarse; 1952 1953err: 1954 dprintk(FE_ERROR, 1, "I/O error"); 1955 return -1; 1956} 1957 1958static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout) 1959{ 1960 s32 timer = 0, lock = 0; 1961 u32 reg; 1962 u8 stat; 1963 1964 while ((timer < timeout) && (!lock)) { 1965 reg = STV090x_READ_DEMOD(state, DMDSTATE); 1966 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 1967 1968 switch (stat) { 1969 case 0: /* searching */ 1970 case 1: /* first PLH detected */ 1971 default: 1972 dprintk(FE_DEBUG, 1, "Demodulator searching .."); 1973 lock = 0; 1974 break; 1975 case 2: /* DVB-S2 mode */ 1976 case 3: /* DVB-S1/legacy mode */ 1977 reg = STV090x_READ_DEMOD(state, DSTATUS); 1978 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 1979 break; 1980 } 1981 1982 if (!lock) 1983 msleep(10); 1984 else 1985 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK"); 1986 1987 timer += 10; 1988 } 1989 return lock; 1990} 1991 1992static int stv090x_blind_search(struct stv090x_state *state) 1993{ 1994 u32 agc2, reg, srate_coarse; 1995 s32 cpt_fail, agc2_ovflw, i; 1996 u8 k_ref, k_max, k_min; 1997 int coarse_fail = 0; 1998 int lock; 1999 2000 k_max = 110; 2001 k_min = 10; 2002 2003 agc2 = stv090x_get_agc2_min_level(state); 2004 2005 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) { 2006 lock = 0; 2007 } else { 2008 2009 if (state->internal->dev_ver <= 0x20) { 2010 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) 2011 goto err; 2012 } else { 2013 /* > Cut 3 */ 2014 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0) 2015 goto err; 2016 } 2017 2018 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) 2019 goto err; 2020 2021 if (state->internal->dev_ver >= 0x20) { 2022 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) 2023 goto err; 2024 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) 2025 goto err; 2026 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) 2027 goto err; 2028 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */ 2029 goto err; 2030 } 2031 2032 k_ref = k_max; 2033 do { 2034 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0) 2035 goto err; 2036 if (stv090x_srate_srch_coarse(state) != 0) { 2037 srate_coarse = stv090x_srate_srch_fine(state); 2038 if (srate_coarse != 0) { 2039 stv090x_get_lock_tmg(state); 2040 lock = stv090x_get_dmdlock(state, 2041 state->DemodTimeout); 2042 } else { 2043 lock = 0; 2044 } 2045 } else { 2046 cpt_fail = 0; 2047 agc2_ovflw = 0; 2048 for (i = 0; i < 10; i++) { 2049 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 2050 STV090x_READ_DEMOD(state, AGC2I0); 2051 if (agc2 >= 0xff00) 2052 agc2_ovflw++; 2053 reg = STV090x_READ_DEMOD(state, DSTATUS2); 2054 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) && 2055 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01)) 2056 2057 cpt_fail++; 2058 } 2059 if ((cpt_fail > 7) || (agc2_ovflw > 7)) 2060 coarse_fail = 1; 2061 2062 lock = 0; 2063 } 2064 k_ref -= 20; 2065 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail)); 2066 } 2067 2068 return lock; 2069 2070err: 2071 dprintk(FE_ERROR, 1, "I/O error"); 2072 return -1; 2073} 2074 2075static int stv090x_chk_tmg(struct stv090x_state *state) 2076{ 2077 u32 reg; 2078 s32 tmg_cpt = 0, i; 2079 u8 freq, tmg_thh, tmg_thl; 2080 int tmg_lock = 0; 2081 2082 freq = STV090x_READ_DEMOD(state, CARFREQ); 2083 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE); 2084 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL); 2085 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) 2086 goto err; 2087 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) 2088 goto err; 2089 2090 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2091 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */ 2092 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2093 goto err; 2094 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0) 2095 goto err; 2096 2097 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0) 2098 goto err; 2099 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0) 2100 goto err; 2101 2102 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */ 2103 goto err; 2104 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 2105 goto err; 2106 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0) 2107 goto err; 2108 2109 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */ 2110 goto err; 2111 msleep(10); 2112 2113 for (i = 0; i < 10; i++) { 2114 reg = STV090x_READ_DEMOD(state, DSTATUS); 2115 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) 2116 tmg_cpt++; 2117 msleep(1); 2118 } 2119 if (tmg_cpt >= 3) 2120 tmg_lock = 1; 2121 2122 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 2123 goto err; 2124 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */ 2125 goto err; 2126 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */ 2127 goto err; 2128 2129 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0) 2130 goto err; 2131 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0) 2132 goto err; 2133 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0) 2134 goto err; 2135 2136 return tmg_lock; 2137 2138err: 2139 dprintk(FE_ERROR, 1, "I/O error"); 2140 return -1; 2141} 2142 2143static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) 2144{ 2145 struct dvb_frontend *fe = &state->frontend; 2146 2147 u32 reg; 2148 s32 car_step, steps, cur_step, dir, freq, timeout_lock; 2149 int lock = 0; 2150 2151 if (state->srate >= 10000000) 2152 timeout_lock = timeout_dmd / 3; 2153 else 2154 timeout_lock = timeout_dmd / 2; 2155 2156 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */ 2157 if (!lock) { 2158 if (state->srate >= 10000000) { 2159 if (stv090x_chk_tmg(state)) { 2160 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 2161 goto err; 2162 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 2163 goto err; 2164 lock = stv090x_get_dmdlock(state, timeout_dmd); 2165 } else { 2166 lock = 0; 2167 } 2168 } else { 2169 if (state->srate <= 4000000) 2170 car_step = 1000; 2171 else if (state->srate <= 7000000) 2172 car_step = 2000; 2173 else if (state->srate <= 10000000) 2174 car_step = 3000; 2175 else 2176 car_step = 5000; 2177 2178 steps = (state->search_range / 1000) / car_step; 2179 steps /= 2; 2180 steps = 2 * (steps + 1); 2181 if (steps < 0) 2182 steps = 2; 2183 else if (steps > 12) 2184 steps = 12; 2185 2186 cur_step = 1; 2187 dir = 1; 2188 2189 if (!lock) { 2190 freq = state->frequency; 2191 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate; 2192 while ((cur_step <= steps) && (!lock)) { 2193 if (dir > 0) 2194 freq += cur_step * car_step; 2195 else 2196 freq -= cur_step * car_step; 2197 2198 /* Setup tuner */ 2199 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2200 goto err; 2201 2202 if (state->config->tuner_set_frequency) { 2203 if (state->config->tuner_set_frequency(fe, freq) < 0) 2204 goto err_gateoff; 2205 } 2206 2207 if (state->config->tuner_set_bandwidth) { 2208 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 2209 goto err_gateoff; 2210 } 2211 2212 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2213 goto err; 2214 2215 msleep(50); 2216 2217 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2218 goto err; 2219 2220 if (state->config->tuner_get_status) { 2221 if (state->config->tuner_get_status(fe, ®) < 0) 2222 goto err_gateoff; 2223 } 2224 2225 if (reg) 2226 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 2227 else 2228 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 2229 2230 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2231 goto err; 2232 2233 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); 2234 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) 2235 goto err; 2236 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 2237 goto err; 2238 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 2239 goto err; 2240 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 2241 goto err; 2242 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3)); 2243 2244 dir *= -1; 2245 cur_step++; 2246 } 2247 } 2248 } 2249 } 2250 2251 return lock; 2252 2253err_gateoff: 2254 stv090x_i2c_gate_ctrl(state, 0); 2255err: 2256 dprintk(FE_ERROR, 1, "I/O error"); 2257 return -1; 2258} 2259 2260static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps) 2261{ 2262 s32 timeout, inc, steps_max, srate, car_max; 2263 2264 srate = state->srate; 2265 car_max = state->search_range / 1000; 2266 car_max += car_max / 10; 2267 car_max = 65536 * (car_max / 2); 2268 car_max /= (state->internal->mclk / 1000); 2269 2270 if (car_max > 0x4000) 2271 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */ 2272 2273 inc = srate; 2274 inc /= state->internal->mclk / 1000; 2275 inc *= 256; 2276 inc *= 256; 2277 inc /= 1000; 2278 2279 switch (state->search_mode) { 2280 case STV090x_SEARCH_DVBS1: 2281 case STV090x_SEARCH_DSS: 2282 inc *= 3; /* freq step = 3% of srate */ 2283 timeout = 20; 2284 break; 2285 2286 case STV090x_SEARCH_DVBS2: 2287 inc *= 4; 2288 timeout = 25; 2289 break; 2290 2291 case STV090x_SEARCH_AUTO: 2292 default: 2293 inc *= 3; 2294 timeout = 25; 2295 break; 2296 } 2297 inc /= 100; 2298 if ((inc > car_max) || (inc < 0)) 2299 inc = car_max / 2; /* increment <= 1/8 Mclk */ 2300 2301 timeout *= 27500; /* 27.5 Msps reference */ 2302 if (srate > 0) 2303 timeout /= (srate / 1000); 2304 2305 if ((timeout > 100) || (timeout < 0)) 2306 timeout = 100; 2307 2308 steps_max = (car_max / inc) + 1; /* min steps = 3 */ 2309 if ((steps_max > 100) || (steps_max < 0)) { 2310 steps_max = 100; /* max steps <= 100 */ 2311 inc = car_max / steps_max; 2312 } 2313 *freq_inc = inc; 2314 *timeout_sw = timeout; 2315 *steps = steps_max; 2316 2317 return 0; 2318} 2319 2320static int stv090x_chk_signal(struct stv090x_state *state) 2321{ 2322 s32 offst_car, agc2, car_max; 2323 int no_signal; 2324 2325 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8; 2326 offst_car |= STV090x_READ_DEMOD(state, CFR1); 2327 offst_car = comp2(offst_car, 16); 2328 2329 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8; 2330 agc2 |= STV090x_READ_DEMOD(state, AGC2I0); 2331 car_max = state->search_range / 1000; 2332 2333 car_max += (car_max / 10); /* 10% margin */ 2334 car_max = (65536 * car_max / 2); 2335 car_max /= state->internal->mclk / 1000; 2336 2337 if (car_max > 0x4000) 2338 car_max = 0x4000; 2339 2340 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) { 2341 no_signal = 1; 2342 dprintk(FE_DEBUG, 1, "No Signal"); 2343 } else { 2344 no_signal = 0; 2345 dprintk(FE_DEBUG, 1, "Found Signal"); 2346 } 2347 2348 return no_signal; 2349} 2350 2351static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max) 2352{ 2353 int no_signal, lock = 0; 2354 s32 cpt_step = 0, offst_freq, car_max; 2355 u32 reg; 2356 2357 car_max = state->search_range / 1000; 2358 car_max += (car_max / 10); 2359 car_max = (65536 * car_max / 2); 2360 car_max /= (state->internal->mclk / 1000); 2361 if (car_max > 0x4000) 2362 car_max = 0x4000; 2363 2364 if (zigzag) 2365 offst_freq = 0; 2366 else 2367 offst_freq = -car_max + inc; 2368 2369 do { 2370 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) 2371 goto err; 2372 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0) 2373 goto err; 2374 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0) 2375 goto err; 2376 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 2377 goto err; 2378 2379 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 2380 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */ 2381 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 2382 goto err; 2383 2384 if (zigzag) { 2385 if (offst_freq >= 0) 2386 offst_freq = -offst_freq - 2 * inc; 2387 else 2388 offst_freq = -offst_freq; 2389 } else { 2390 offst_freq += 2 * inc; 2391 } 2392 2393 cpt_step++; 2394 2395 lock = stv090x_get_dmdlock(state, timeout); 2396 no_signal = stv090x_chk_signal(state); 2397 2398 } while ((!lock) && 2399 (!no_signal) && 2400 ((offst_freq - inc) < car_max) && 2401 ((offst_freq + inc) > -car_max) && 2402 (cpt_step < steps_max)); 2403 2404 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 2405 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0); 2406 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 2407 goto err; 2408 2409 return lock; 2410err: 2411 dprintk(FE_ERROR, 1, "I/O error"); 2412 return -1; 2413} 2414 2415static int stv090x_sw_algo(struct stv090x_state *state) 2416{ 2417 int no_signal, zigzag, lock = 0; 2418 u32 reg; 2419 2420 s32 dvbs2_fly_wheel; 2421 s32 inc, timeout_step, trials, steps_max; 2422 2423 /* get params */ 2424 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); 2425 2426 switch (state->search_mode) { 2427 case STV090x_SEARCH_DVBS1: 2428 case STV090x_SEARCH_DSS: 2429 /* accelerate the frequency detector */ 2430 if (state->internal->dev_ver >= 0x20) { 2431 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0) 2432 goto err; 2433 } 2434 2435 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0) 2436 goto err; 2437 zigzag = 0; 2438 break; 2439 2440 case STV090x_SEARCH_DVBS2: 2441 if (state->internal->dev_ver >= 0x20) { 2442 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2443 goto err; 2444 } 2445 2446 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) 2447 goto err; 2448 zigzag = 1; 2449 break; 2450 2451 case STV090x_SEARCH_AUTO: 2452 default: 2453 /* accelerate the frequency detector */ 2454 if (state->internal->dev_ver >= 0x20) { 2455 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0) 2456 goto err; 2457 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2458 goto err; 2459 } 2460 2461 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0) 2462 goto err; 2463 zigzag = 0; 2464 break; 2465 } 2466 2467 trials = 0; 2468 do { 2469 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max); 2470 no_signal = stv090x_chk_signal(state); 2471 trials++; 2472 2473 /*run the SW search 2 times maximum*/ 2474 if (lock || no_signal || (trials == 2)) { 2475 /*Check if the demod is not losing lock in DVBS2*/ 2476 if (state->internal->dev_ver >= 0x20) { 2477 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 2478 goto err; 2479 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) 2480 goto err; 2481 } 2482 2483 reg = STV090x_READ_DEMOD(state, DMDSTATE); 2484 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) { 2485 /*Check if the demod is not losing lock in DVBS2*/ 2486 msleep(timeout_step); 2487 reg = STV090x_READ_DEMOD(state, DMDFLYW); 2488 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); 2489 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */ 2490 msleep(timeout_step); 2491 reg = STV090x_READ_DEMOD(state, DMDFLYW); 2492 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); 2493 } 2494 if (dvbs2_fly_wheel < 0xd) { 2495 /*FALSE lock, The demod is losing lock */ 2496 lock = 0; 2497 if (trials < 2) { 2498 if (state->internal->dev_ver >= 0x20) { 2499 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2500 goto err; 2501 } 2502 2503 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) 2504 goto err; 2505 } 2506 } 2507 } 2508 } 2509 } while ((!lock) && (trials < 2) && (!no_signal)); 2510 2511 return lock; 2512err: 2513 dprintk(FE_ERROR, 1, "I/O error"); 2514 return -1; 2515} 2516 2517static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state) 2518{ 2519 u32 reg; 2520 enum stv090x_delsys delsys; 2521 2522 reg = STV090x_READ_DEMOD(state, DMDSTATE); 2523 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2) 2524 delsys = STV090x_DVBS2; 2525 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { 2526 reg = STV090x_READ_DEMOD(state, FECM); 2527 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1) 2528 delsys = STV090x_DSS; 2529 else 2530 delsys = STV090x_DVBS1; 2531 } else { 2532 delsys = STV090x_ERROR; 2533 } 2534 2535 return delsys; 2536} 2537 2538/* in Hz */ 2539static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk) 2540{ 2541 s32 derot, int_1, int_2, tmp_1, tmp_2; 2542 2543 derot = STV090x_READ_DEMOD(state, CFR2) << 16; 2544 derot |= STV090x_READ_DEMOD(state, CFR1) << 8; 2545 derot |= STV090x_READ_DEMOD(state, CFR0); 2546 2547 derot = comp2(derot, 24); 2548 int_1 = mclk >> 12; 2549 int_2 = derot >> 12; 2550 2551 /* carrier_frequency = MasterClock * Reg / 2^24 */ 2552 tmp_1 = mclk % 0x1000; 2553 tmp_2 = derot % 0x1000; 2554 2555 derot = (int_1 * int_2) + 2556 ((int_1 * tmp_2) >> 12) + 2557 ((int_2 * tmp_1) >> 12); 2558 2559 return derot; 2560} 2561 2562static int stv090x_get_viterbi(struct stv090x_state *state) 2563{ 2564 u32 reg, rate; 2565 2566 reg = STV090x_READ_DEMOD(state, VITCURPUN); 2567 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD); 2568 2569 switch (rate) { 2570 case 13: 2571 state->fec = STV090x_PR12; 2572 break; 2573 2574 case 18: 2575 state->fec = STV090x_PR23; 2576 break; 2577 2578 case 21: 2579 state->fec = STV090x_PR34; 2580 break; 2581 2582 case 24: 2583 state->fec = STV090x_PR56; 2584 break; 2585 2586 case 25: 2587 state->fec = STV090x_PR67; 2588 break; 2589 2590 case 26: 2591 state->fec = STV090x_PR78; 2592 break; 2593 2594 default: 2595 state->fec = STV090x_PRERR; 2596 break; 2597 } 2598 2599 return 0; 2600} 2601 2602static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state) 2603{ 2604 struct dvb_frontend *fe = &state->frontend; 2605 2606 u8 tmg; 2607 u32 reg; 2608 s32 i = 0, offst_freq; 2609 2610 msleep(5); 2611 2612 if (state->algo == STV090x_BLIND_SEARCH) { 2613 tmg = STV090x_READ_DEMOD(state, TMGREG2); 2614 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c); 2615 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) { 2616 tmg = STV090x_READ_DEMOD(state, TMGREG2); 2617 msleep(5); 2618 i += 5; 2619 } 2620 } 2621 state->delsys = stv090x_get_std(state); 2622 2623 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2624 goto err; 2625 2626 if (state->config->tuner_get_frequency) { 2627 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) 2628 goto err_gateoff; 2629 } 2630 2631 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2632 goto err; 2633 2634 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000; 2635 state->frequency += offst_freq; 2636 2637 if (stv090x_get_viterbi(state) < 0) 2638 goto err; 2639 2640 reg = STV090x_READ_DEMOD(state, DMDMODCOD); 2641 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); 2642 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; 2643 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1; 2644 reg = STV090x_READ_DEMOD(state, TMGOBS); 2645 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); 2646 reg = STV090x_READ_DEMOD(state, FECM); 2647 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD); 2648 2649 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) { 2650 2651 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2652 goto err; 2653 2654 if (state->config->tuner_get_frequency) { 2655 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) 2656 goto err_gateoff; 2657 } 2658 2659 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2660 goto err; 2661 2662 if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) 2663 return STV090x_RANGEOK; 2664 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000)) 2665 return STV090x_RANGEOK; 2666 else 2667 return STV090x_OUTOFRANGE; /* Out of Range */ 2668 } else { 2669 if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) 2670 return STV090x_RANGEOK; 2671 else 2672 return STV090x_OUTOFRANGE; 2673 } 2674 2675 return STV090x_OUTOFRANGE; 2676 2677err_gateoff: 2678 stv090x_i2c_gate_ctrl(state, 0); 2679err: 2680 dprintk(FE_ERROR, 1, "I/O error"); 2681 return -1; 2682} 2683 2684static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate) 2685{ 2686 s32 offst_tmg; 2687 2688 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16; 2689 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8; 2690 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0); 2691 2692 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */ 2693 if (!offst_tmg) 2694 offst_tmg = 1; 2695 2696 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg); 2697 offst_tmg /= 320; 2698 2699 return offst_tmg; 2700} 2701 2702static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots) 2703{ 2704 u8 aclc = 0x29; 2705 s32 i; 2706 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low; 2707 2708 if (state->internal->dev_ver == 0x20) { 2709 car_loop = stv090x_s2_crl_cut20; 2710 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20; 2711 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20; 2712 } else { 2713 /* >= Cut 3 */ 2714 car_loop = stv090x_s2_crl_cut30; 2715 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30; 2716 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30; 2717 } 2718 2719 if (modcod < STV090x_QPSK_12) { 2720 i = 0; 2721 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod)) 2722 i++; 2723 2724 if (i >= 3) 2725 i = 2; 2726 2727 } else { 2728 i = 0; 2729 while ((i < 14) && (modcod != car_loop[i].modcod)) 2730 i++; 2731 2732 if (i >= 14) { 2733 i = 0; 2734 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod)) 2735 i++; 2736 2737 if (i >= 11) 2738 i = 10; 2739 } 2740 } 2741 2742 if (modcod <= STV090x_QPSK_25) { 2743 if (pilots) { 2744 if (state->srate <= 3000000) 2745 aclc = car_loop_qpsk_low[i].crl_pilots_on_2; 2746 else if (state->srate <= 7000000) 2747 aclc = car_loop_qpsk_low[i].crl_pilots_on_5; 2748 else if (state->srate <= 15000000) 2749 aclc = car_loop_qpsk_low[i].crl_pilots_on_10; 2750 else if (state->srate <= 25000000) 2751 aclc = car_loop_qpsk_low[i].crl_pilots_on_20; 2752 else 2753 aclc = car_loop_qpsk_low[i].crl_pilots_on_30; 2754 } else { 2755 if (state->srate <= 3000000) 2756 aclc = car_loop_qpsk_low[i].crl_pilots_off_2; 2757 else if (state->srate <= 7000000) 2758 aclc = car_loop_qpsk_low[i].crl_pilots_off_5; 2759 else if (state->srate <= 15000000) 2760 aclc = car_loop_qpsk_low[i].crl_pilots_off_10; 2761 else if (state->srate <= 25000000) 2762 aclc = car_loop_qpsk_low[i].crl_pilots_off_20; 2763 else 2764 aclc = car_loop_qpsk_low[i].crl_pilots_off_30; 2765 } 2766 2767 } else if (modcod <= STV090x_8PSK_910) { 2768 if (pilots) { 2769 if (state->srate <= 3000000) 2770 aclc = car_loop[i].crl_pilots_on_2; 2771 else if (state->srate <= 7000000) 2772 aclc = car_loop[i].crl_pilots_on_5; 2773 else if (state->srate <= 15000000) 2774 aclc = car_loop[i].crl_pilots_on_10; 2775 else if (state->srate <= 25000000) 2776 aclc = car_loop[i].crl_pilots_on_20; 2777 else 2778 aclc = car_loop[i].crl_pilots_on_30; 2779 } else { 2780 if (state->srate <= 3000000) 2781 aclc = car_loop[i].crl_pilots_off_2; 2782 else if (state->srate <= 7000000) 2783 aclc = car_loop[i].crl_pilots_off_5; 2784 else if (state->srate <= 15000000) 2785 aclc = car_loop[i].crl_pilots_off_10; 2786 else if (state->srate <= 25000000) 2787 aclc = car_loop[i].crl_pilots_off_20; 2788 else 2789 aclc = car_loop[i].crl_pilots_off_30; 2790 } 2791 } else { /* 16APSK and 32APSK */ 2792 if (state->srate <= 3000000) 2793 aclc = car_loop_apsk_low[i].crl_pilots_on_2; 2794 else if (state->srate <= 7000000) 2795 aclc = car_loop_apsk_low[i].crl_pilots_on_5; 2796 else if (state->srate <= 15000000) 2797 aclc = car_loop_apsk_low[i].crl_pilots_on_10; 2798 else if (state->srate <= 25000000) 2799 aclc = car_loop_apsk_low[i].crl_pilots_on_20; 2800 else 2801 aclc = car_loop_apsk_low[i].crl_pilots_on_30; 2802 } 2803 2804 return aclc; 2805} 2806 2807static u8 stv090x_optimize_carloop_short(struct stv090x_state *state) 2808{ 2809 struct stv090x_short_frame_crloop *short_crl = NULL; 2810 s32 index = 0; 2811 u8 aclc = 0x0b; 2812 2813 switch (state->modulation) { 2814 case STV090x_QPSK: 2815 default: 2816 index = 0; 2817 break; 2818 case STV090x_8PSK: 2819 index = 1; 2820 break; 2821 case STV090x_16APSK: 2822 index = 2; 2823 break; 2824 case STV090x_32APSK: 2825 index = 3; 2826 break; 2827 } 2828 2829 if (state->internal->dev_ver >= 0x30) { 2830 /* Cut 3.0 and up */ 2831 short_crl = stv090x_s2_short_crl_cut30; 2832 } else { 2833 /* Cut 2.0 and up: we don't support cuts older than 2.0 */ 2834 short_crl = stv090x_s2_short_crl_cut20; 2835 } 2836 2837 if (state->srate <= 3000000) 2838 aclc = short_crl[index].crl_2; 2839 else if (state->srate <= 7000000) 2840 aclc = short_crl[index].crl_5; 2841 else if (state->srate <= 15000000) 2842 aclc = short_crl[index].crl_10; 2843 else if (state->srate <= 25000000) 2844 aclc = short_crl[index].crl_20; 2845 else 2846 aclc = short_crl[index].crl_30; 2847 2848 return aclc; 2849} 2850 2851static int stv090x_optimize_track(struct stv090x_state *state) 2852{ 2853 struct dvb_frontend *fe = &state->frontend; 2854 2855 enum stv090x_modcod modcod; 2856 2857 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0; 2858 u32 reg; 2859 2860 srate = stv090x_get_srate(state, state->internal->mclk); 2861 srate += stv090x_get_tmgoffst(state, srate); 2862 2863 switch (state->delsys) { 2864 case STV090x_DVBS1: 2865 case STV090x_DSS: 2866 if (state->search_mode == STV090x_SEARCH_AUTO) { 2867 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2868 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 2869 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 2870 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2871 goto err; 2872 } 2873 reg = STV090x_READ_DEMOD(state, DEMOD); 2874 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); 2875 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01); 2876 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 2877 goto err; 2878 2879 if (state->internal->dev_ver >= 0x30) { 2880 if (stv090x_get_viterbi(state) < 0) 2881 goto err; 2882 2883 if (state->fec == STV090x_PR12) { 2884 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0) 2885 goto err; 2886 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) 2887 goto err; 2888 } else { 2889 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0) 2890 goto err; 2891 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) 2892 goto err; 2893 } 2894 } 2895 2896 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) 2897 goto err; 2898 break; 2899 2900 case STV090x_DVBS2: 2901 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2902 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 2903 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 2904 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2905 goto err; 2906 if (state->internal->dev_ver >= 0x30) { 2907 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0) 2908 goto err; 2909 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0) 2910 goto err; 2911 } 2912 if (state->frame_len == STV090x_LONG_FRAME) { 2913 reg = STV090x_READ_DEMOD(state, DMDMODCOD); 2914 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); 2915 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; 2916 aclc = stv090x_optimize_carloop(state, modcod, pilots); 2917 if (modcod <= STV090x_QPSK_910) { 2918 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc); 2919 } else if (modcod <= STV090x_8PSK_910) { 2920 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2921 goto err; 2922 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) 2923 goto err; 2924 } 2925 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) { 2926 if (modcod <= STV090x_16APSK_910) { 2927 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2928 goto err; 2929 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) 2930 goto err; 2931 } else { 2932 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2933 goto err; 2934 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) 2935 goto err; 2936 } 2937 } 2938 } else { 2939 /*Carrier loop setting for short frame*/ 2940 aclc = stv090x_optimize_carloop_short(state); 2941 if (state->modulation == STV090x_QPSK) { 2942 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0) 2943 goto err; 2944 } else if (state->modulation == STV090x_8PSK) { 2945 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2946 goto err; 2947 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) 2948 goto err; 2949 } else if (state->modulation == STV090x_16APSK) { 2950 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2951 goto err; 2952 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) 2953 goto err; 2954 } else if (state->modulation == STV090x_32APSK) { 2955 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2956 goto err; 2957 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) 2958 goto err; 2959 } 2960 } 2961 2962 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */ 2963 break; 2964 2965 case STV090x_ERROR: 2966 default: 2967 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2968 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 2969 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 2970 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2971 goto err; 2972 break; 2973 } 2974 2975 f_1 = STV090x_READ_DEMOD(state, CFR2); 2976 f_0 = STV090x_READ_DEMOD(state, CFR1); 2977 reg = STV090x_READ_DEMOD(state, TMGOBS); 2978 2979 if (state->algo == STV090x_BLIND_SEARCH) { 2980 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00); 2981 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2982 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00); 2983 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); 2984 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2985 goto err; 2986 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) 2987 goto err; 2988 2989 if (stv090x_set_srate(state, srate) < 0) 2990 goto err; 2991 blind_tune = 1; 2992 2993 if (stv090x_dvbs_track_crl(state) < 0) 2994 goto err; 2995 } 2996 2997 if (state->internal->dev_ver >= 0x20) { 2998 if ((state->search_mode == STV090x_SEARCH_DVBS1) || 2999 (state->search_mode == STV090x_SEARCH_DSS) || 3000 (state->search_mode == STV090x_SEARCH_AUTO)) { 3001 3002 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0) 3003 goto err; 3004 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0) 3005 goto err; 3006 } 3007 } 3008 3009 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 3010 goto err; 3011 3012 /* AUTO tracking MODE */ 3013 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0) 3014 goto err; 3015 /* AUTO tracking MODE */ 3016 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0) 3017 goto err; 3018 3019 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) || 3020 (state->srate < 10000000)) { 3021 /* update initial carrier freq with the found freq offset */ 3022 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3023 goto err; 3024 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3025 goto err; 3026 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000; 3027 3028 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) { 3029 3030 if (state->algo != STV090x_WARM_SEARCH) { 3031 3032 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3033 goto err; 3034 3035 if (state->config->tuner_set_bandwidth) { 3036 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 3037 goto err_gateoff; 3038 } 3039 3040 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3041 goto err; 3042 3043 } 3044 } 3045 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) 3046 msleep(50); /* blind search: wait 50ms for SR stabilization */ 3047 else 3048 msleep(5); 3049 3050 stv090x_get_lock_tmg(state); 3051 3052 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) { 3053 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 3054 goto err; 3055 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3056 goto err; 3057 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3058 goto err; 3059 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 3060 goto err; 3061 3062 i = 0; 3063 3064 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) { 3065 3066 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 3067 goto err; 3068 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3069 goto err; 3070 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3071 goto err; 3072 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 3073 goto err; 3074 i++; 3075 } 3076 } 3077 3078 } 3079 3080 if (state->internal->dev_ver >= 0x20) { 3081 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 3082 goto err; 3083 } 3084 3085 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS)) 3086 stv090x_set_vit_thtracq(state); 3087 3088 return 0; 3089 3090err_gateoff: 3091 stv090x_i2c_gate_ctrl(state, 0); 3092err: 3093 dprintk(FE_ERROR, 1, "I/O error"); 3094 return -1; 3095} 3096 3097static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout) 3098{ 3099 s32 timer = 0, lock = 0, stat; 3100 u32 reg; 3101 3102 while ((timer < timeout) && (!lock)) { 3103 reg = STV090x_READ_DEMOD(state, DMDSTATE); 3104 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 3105 3106 switch (stat) { 3107 case 0: /* searching */ 3108 case 1: /* first PLH detected */ 3109 default: 3110 lock = 0; 3111 break; 3112 3113 case 2: /* DVB-S2 mode */ 3114 reg = STV090x_READ_DEMOD(state, PDELSTATUS1); 3115 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD); 3116 break; 3117 3118 case 3: /* DVB-S1/legacy mode */ 3119 reg = STV090x_READ_DEMOD(state, VSTATUSVIT); 3120 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD); 3121 break; 3122 } 3123 if (!lock) { 3124 msleep(10); 3125 timer += 10; 3126 } 3127 } 3128 return lock; 3129} 3130 3131static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec) 3132{ 3133 u32 reg; 3134 s32 timer = 0; 3135 int lock; 3136 3137 lock = stv090x_get_dmdlock(state, timeout_dmd); 3138 if (lock) 3139 lock = stv090x_get_feclock(state, timeout_fec); 3140 3141 if (lock) { 3142 lock = 0; 3143 3144 while ((timer < timeout_fec) && (!lock)) { 3145 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3146 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD); 3147 msleep(1); 3148 timer++; 3149 } 3150 } 3151 3152 return lock; 3153} 3154 3155static int stv090x_set_s2rolloff(struct stv090x_state *state) 3156{ 3157 u32 reg; 3158 3159 if (state->internal->dev_ver <= 0x20) { 3160 /* rolloff to auto mode if DVBS2 */ 3161 reg = STV090x_READ_DEMOD(state, DEMOD); 3162 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00); 3163 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3164 goto err; 3165 } else { 3166 /* DVB-S2 rolloff to auto mode if DVBS2 */ 3167 reg = STV090x_READ_DEMOD(state, DEMOD); 3168 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00); 3169 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3170 goto err; 3171 } 3172 return 0; 3173err: 3174 dprintk(FE_ERROR, 1, "I/O error"); 3175 return -1; 3176} 3177 3178 3179static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state) 3180{ 3181 struct dvb_frontend *fe = &state->frontend; 3182 enum stv090x_signal_state signal_state = STV090x_NOCARRIER; 3183 u32 reg; 3184 s32 agc1_power, power_iq = 0, i; 3185 int lock = 0, low_sr = 0; 3186 3187 reg = STV090x_READ_DEMOD(state, TSCFGH); 3188 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */ 3189 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3190 goto err; 3191 3192 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */ 3193 goto err; 3194 3195 if (state->internal->dev_ver >= 0x20) { 3196 if (state->srate > 5000000) { 3197 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) 3198 goto err; 3199 } else { 3200 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0) 3201 goto err; 3202 } 3203 } 3204 3205 stv090x_get_lock_tmg(state); 3206 3207 if (state->algo == STV090x_BLIND_SEARCH) { 3208 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */ 3209 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */ 3210 goto err; 3211 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) 3212 goto err; 3213 if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */ 3214 goto err; 3215 } else { 3216 /* known srate */ 3217 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) 3218 goto err; 3219 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) 3220 goto err; 3221 3222 if (state->srate < 2000000) { 3223 /* SR < 2MSPS */ 3224 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0) 3225 goto err; 3226 } else { 3227 /* SR >= 2Msps */ 3228 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) 3229 goto err; 3230 } 3231 3232 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 3233 goto err; 3234 3235 if (state->internal->dev_ver >= 0x20) { 3236 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0) 3237 goto err; 3238 if (state->algo == STV090x_COLD_SEARCH) 3239 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10; 3240 else if (state->algo == STV090x_WARM_SEARCH) 3241 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000; 3242 } 3243 3244 /* if cold start or warm (Symbolrate is known) 3245 * use a Narrow symbol rate scan range 3246 */ 3247 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */ 3248 goto err; 3249 3250 if (stv090x_set_srate(state, state->srate) < 0) 3251 goto err; 3252 3253 if (stv090x_set_max_srate(state, state->internal->mclk, 3254 state->srate) < 0) 3255 goto err; 3256 if (stv090x_set_min_srate(state, state->internal->mclk, 3257 state->srate) < 0) 3258 goto err; 3259 3260 if (state->srate >= 10000000) 3261 low_sr = 0; 3262 else 3263 low_sr = 1; 3264 } 3265 3266 /* Setup tuner */ 3267 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3268 goto err; 3269 3270 if (state->config->tuner_set_bbgain) { 3271 reg = state->config->tuner_bbgain; 3272 if (reg == 0) 3273 reg = 10; /* default: 10dB */ 3274 if (state->config->tuner_set_bbgain(fe, reg) < 0) 3275 goto err_gateoff; 3276 } 3277 3278 if (state->config->tuner_set_frequency) { 3279 if (state->config->tuner_set_frequency(fe, state->frequency) < 0) 3280 goto err_gateoff; 3281 } 3282 3283 if (state->config->tuner_set_bandwidth) { 3284 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 3285 goto err_gateoff; 3286 } 3287 3288 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3289 goto err; 3290 3291 msleep(50); 3292 3293 if (state->config->tuner_get_status) { 3294 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3295 goto err; 3296 if (state->config->tuner_get_status(fe, ®) < 0) 3297 goto err_gateoff; 3298 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3299 goto err; 3300 3301 if (reg) 3302 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 3303 else { 3304 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 3305 return STV090x_NOCARRIER; 3306 } 3307 } 3308 3309 msleep(10); 3310 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1), 3311 STV090x_READ_DEMOD(state, AGCIQIN0)); 3312 3313 if (agc1_power == 0) { 3314 /* If AGC1 integrator value is 0 3315 * then read POWERI, POWERQ 3316 */ 3317 for (i = 0; i < 5; i++) { 3318 power_iq += (STV090x_READ_DEMOD(state, POWERI) + 3319 STV090x_READ_DEMOD(state, POWERQ)) >> 1; 3320 } 3321 power_iq /= 5; 3322 } 3323 3324 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) { 3325 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq); 3326 lock = 0; 3327 signal_state = STV090x_NOAGC1; 3328 } else { 3329 reg = STV090x_READ_DEMOD(state, DEMOD); 3330 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion); 3331 3332 if (state->internal->dev_ver <= 0x20) { 3333 /* rolloff to auto mode if DVBS2 */ 3334 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1); 3335 } else { 3336 /* DVB-S2 rolloff to auto mode if DVBS2 */ 3337 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1); 3338 } 3339 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3340 goto err; 3341 3342 if (stv090x_delivery_search(state) < 0) 3343 goto err; 3344 3345 if (state->algo != STV090x_BLIND_SEARCH) { 3346 if (stv090x_start_search(state) < 0) 3347 goto err; 3348 } 3349 } 3350 3351 if (signal_state == STV090x_NOAGC1) 3352 return signal_state; 3353 3354 if (state->algo == STV090x_BLIND_SEARCH) 3355 lock = stv090x_blind_search(state); 3356 3357 else if (state->algo == STV090x_COLD_SEARCH) 3358 lock = stv090x_get_coldlock(state, state->DemodTimeout); 3359 3360 else if (state->algo == STV090x_WARM_SEARCH) 3361 lock = stv090x_get_dmdlock(state, state->DemodTimeout); 3362 3363 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) { 3364 if (!low_sr) { 3365 if (stv090x_chk_tmg(state)) 3366 lock = stv090x_sw_algo(state); 3367 } 3368 } 3369 3370 if (lock) 3371 signal_state = stv090x_get_sig_params(state); 3372 3373 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */ 3374 stv090x_optimize_track(state); 3375 3376 if (state->internal->dev_ver >= 0x20) { 3377 /* >= Cut 2.0 :release TS reset after 3378 * demod lock and optimized Tracking 3379 */ 3380 reg = STV090x_READ_DEMOD(state, TSCFGH); 3381 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ 3382 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3383 goto err; 3384 3385 msleep(3); 3386 3387 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */ 3388 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3389 goto err; 3390 3391 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ 3392 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3393 goto err; 3394 } 3395 3396 lock = stv090x_get_lock(state, state->FecTimeout, 3397 state->FecTimeout); 3398 if (lock) { 3399 if (state->delsys == STV090x_DVBS2) { 3400 stv090x_set_s2rolloff(state); 3401 3402 reg = STV090x_READ_DEMOD(state, PDELCTRL2); 3403 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1); 3404 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) 3405 goto err; 3406 /* Reset DVBS2 packet delinator error counter */ 3407 reg = STV090x_READ_DEMOD(state, PDELCTRL2); 3408 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0); 3409 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) 3410 goto err; 3411 3412 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */ 3413 goto err; 3414 } else { 3415 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) 3416 goto err; 3417 } 3418 /* Reset the Total packet counter */ 3419 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0) 3420 goto err; 3421 /* Reset the packet Error counter2 */ 3422 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) 3423 goto err; 3424 } else { 3425 signal_state = STV090x_NODATA; 3426 stv090x_chk_signal(state); 3427 } 3428 } 3429 return signal_state; 3430 3431err_gateoff: 3432 stv090x_i2c_gate_ctrl(state, 0); 3433err: 3434 dprintk(FE_ERROR, 1, "I/O error"); 3435 return -1; 3436} 3437 3438static int stv090x_set_mis(struct stv090x_state *state, int mis) 3439{ 3440 u32 reg; 3441 3442 if (mis < 0 || mis > 255) { 3443 dprintk(FE_DEBUG, 1, "Disable MIS filtering"); 3444 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 3445 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00); 3446 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 3447 goto err; 3448 } else { 3449 dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis); 3450 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 3451 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01); 3452 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 3453 goto err; 3454 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0) 3455 goto err; 3456 if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0) 3457 goto err; 3458 } 3459 return 0; 3460err: 3461 dprintk(FE_ERROR, 1, "I/O error"); 3462 return -1; 3463} 3464 3465static enum dvbfe_search stv090x_search(struct dvb_frontend *fe) 3466{ 3467 struct stv090x_state *state = fe->demodulator_priv; 3468 struct dtv_frontend_properties *props = &fe->dtv_property_cache; 3469 3470 if (props->frequency == 0) 3471 return DVBFE_ALGO_SEARCH_INVALID; 3472 3473 state->delsys = props->delivery_system; 3474 state->frequency = props->frequency; 3475 state->srate = props->symbol_rate; 3476 state->search_mode = STV090x_SEARCH_AUTO; 3477 state->algo = STV090x_COLD_SEARCH; 3478 state->fec = STV090x_PRERR; 3479 if (state->srate > 10000000) { 3480 dprintk(FE_DEBUG, 1, "Search range: 10 MHz"); 3481 state->search_range = 10000000; 3482 } else { 3483 dprintk(FE_DEBUG, 1, "Search range: 5 MHz"); 3484 state->search_range = 5000000; 3485 } 3486 3487 stv090x_set_mis(state, props->stream_id); 3488 3489 if (stv090x_algo(state) == STV090x_RANGEOK) { 3490 dprintk(FE_DEBUG, 1, "Search success!"); 3491 return DVBFE_ALGO_SEARCH_SUCCESS; 3492 } else { 3493 dprintk(FE_DEBUG, 1, "Search failed!"); 3494 return DVBFE_ALGO_SEARCH_FAILED; 3495 } 3496 3497 return DVBFE_ALGO_SEARCH_ERROR; 3498} 3499 3500static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status) 3501{ 3502 struct stv090x_state *state = fe->demodulator_priv; 3503 u32 reg, dstatus; 3504 u8 search_state; 3505 3506 *status = 0; 3507 3508 dstatus = STV090x_READ_DEMOD(state, DSTATUS); 3509 if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD)) 3510 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; 3511 3512 reg = STV090x_READ_DEMOD(state, DMDSTATE); 3513 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 3514 3515 switch (search_state) { 3516 case 0: /* searching */ 3517 case 1: /* first PLH detected */ 3518 default: 3519 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)"); 3520 break; 3521 3522 case 2: /* DVB-S2 mode */ 3523 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2"); 3524 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) { 3525 reg = STV090x_READ_DEMOD(state, PDELSTATUS1); 3526 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) { 3527 *status |= FE_HAS_VITERBI; 3528 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3529 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) 3530 *status |= FE_HAS_SYNC | FE_HAS_LOCK; 3531 } 3532 } 3533 break; 3534 3535 case 3: /* DVB-S1/legacy mode */ 3536 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S"); 3537 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) { 3538 reg = STV090x_READ_DEMOD(state, VSTATUSVIT); 3539 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) { 3540 *status |= FE_HAS_VITERBI; 3541 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3542 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) 3543 *status |= FE_HAS_SYNC | FE_HAS_LOCK; 3544 } 3545 } 3546 break; 3547 } 3548 3549 return 0; 3550} 3551 3552static int stv090x_read_per(struct dvb_frontend *fe, u32 *per) 3553{ 3554 struct stv090x_state *state = fe->demodulator_priv; 3555 3556 s32 count_4, count_3, count_2, count_1, count_0, count; 3557 u32 reg, h, m, l; 3558 enum fe_status status; 3559 3560 stv090x_read_status(fe, &status); 3561 if (!(status & FE_HAS_LOCK)) { 3562 *per = 1 << 23; /* Max PER */ 3563 } else { 3564 /* Counter 2 */ 3565 reg = STV090x_READ_DEMOD(state, ERRCNT22); 3566 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD); 3567 3568 reg = STV090x_READ_DEMOD(state, ERRCNT21); 3569 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD); 3570 3571 reg = STV090x_READ_DEMOD(state, ERRCNT20); 3572 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD); 3573 3574 *per = ((h << 16) | (m << 8) | l); 3575 3576 count_4 = STV090x_READ_DEMOD(state, FBERCPT4); 3577 count_3 = STV090x_READ_DEMOD(state, FBERCPT3); 3578 count_2 = STV090x_READ_DEMOD(state, FBERCPT2); 3579 count_1 = STV090x_READ_DEMOD(state, FBERCPT1); 3580 count_0 = STV090x_READ_DEMOD(state, FBERCPT0); 3581 3582 if ((!count_4) && (!count_3)) { 3583 count = (count_2 & 0xff) << 16; 3584 count |= (count_1 & 0xff) << 8; 3585 count |= count_0 & 0xff; 3586 } else { 3587 count = 1 << 24; 3588 } 3589 if (count == 0) 3590 *per = 1; 3591 } 3592 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0) 3593 goto err; 3594 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) 3595 goto err; 3596 3597 return 0; 3598err: 3599 dprintk(FE_ERROR, 1, "I/O error"); 3600 return -1; 3601} 3602 3603static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val) 3604{ 3605 int res = 0; 3606 int min = 0, med; 3607 3608 if ((val >= tab[min].read && val < tab[max].read) || 3609 (val >= tab[max].read && val < tab[min].read)) { 3610 while ((max - min) > 1) { 3611 med = (max + min) / 2; 3612 if ((val >= tab[min].read && val < tab[med].read) || 3613 (val >= tab[med].read && val < tab[min].read)) 3614 max = med; 3615 else 3616 min = med; 3617 } 3618 res = ((val - tab[min].read) * 3619 (tab[max].real - tab[min].real) / 3620 (tab[max].read - tab[min].read)) + 3621 tab[min].real; 3622 } else { 3623 if (tab[min].read < tab[max].read) { 3624 if (val < tab[min].read) 3625 res = tab[min].real; 3626 else if (val >= tab[max].read) 3627 res = tab[max].real; 3628 } else { 3629 if (val >= tab[min].read) 3630 res = tab[min].real; 3631 else if (val < tab[max].read) 3632 res = tab[max].real; 3633 } 3634 } 3635 3636 return res; 3637} 3638 3639static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 3640{ 3641 struct stv090x_state *state = fe->demodulator_priv; 3642 u32 reg; 3643 s32 agc_0, agc_1, agc; 3644 s32 str; 3645 3646 reg = STV090x_READ_DEMOD(state, AGCIQIN1); 3647 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); 3648 reg = STV090x_READ_DEMOD(state, AGCIQIN0); 3649 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); 3650 agc = MAKEWORD16(agc_1, agc_0); 3651 3652 str = stv090x_table_lookup(stv090x_rf_tab, 3653 ARRAY_SIZE(stv090x_rf_tab) - 1, agc); 3654 if (agc > stv090x_rf_tab[0].read) 3655 str = 0; 3656 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read) 3657 str = -100; 3658 *strength = (str + 100) * 0xFFFF / 100; 3659 3660 return 0; 3661} 3662 3663static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr) 3664{ 3665 struct stv090x_state *state = fe->demodulator_priv; 3666 u32 reg_0, reg_1, reg, i; 3667 s32 val_0, val_1, val = 0; 3668 u8 lock_f; 3669 s32 div; 3670 u32 last; 3671 3672 switch (state->delsys) { 3673 case STV090x_DVBS2: 3674 reg = STV090x_READ_DEMOD(state, DSTATUS); 3675 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 3676 if (lock_f) { 3677 msleep(5); 3678 for (i = 0; i < 16; i++) { 3679 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1); 3680 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD); 3681 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0); 3682 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD); 3683 val += MAKEWORD16(val_1, val_0); 3684 msleep(1); 3685 } 3686 val /= 16; 3687 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1; 3688 div = stv090x_s2cn_tab[0].read - 3689 stv090x_s2cn_tab[last].read; 3690 *cnr = 0xFFFF - ((val * 0xFFFF) / div); 3691 } 3692 break; 3693 3694 case STV090x_DVBS1: 3695 case STV090x_DSS: 3696 reg = STV090x_READ_DEMOD(state, DSTATUS); 3697 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 3698 if (lock_f) { 3699 msleep(5); 3700 for (i = 0; i < 16; i++) { 3701 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1); 3702 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD); 3703 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0); 3704 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD); 3705 val += MAKEWORD16(val_1, val_0); 3706 msleep(1); 3707 } 3708 val /= 16; 3709 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1; 3710 div = stv090x_s1cn_tab[0].read - 3711 stv090x_s1cn_tab[last].read; 3712 *cnr = 0xFFFF - ((val * 0xFFFF) / div); 3713 } 3714 break; 3715 default: 3716 break; 3717 } 3718 3719 return 0; 3720} 3721 3722static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 3723{ 3724 struct stv090x_state *state = fe->demodulator_priv; 3725 u32 reg; 3726 3727 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3728 switch (tone) { 3729 case SEC_TONE_ON: 3730 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); 3731 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3732 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3733 goto err; 3734 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3735 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3736 goto err; 3737 break; 3738 3739 case SEC_TONE_OFF: 3740 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); 3741 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3742 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3743 goto err; 3744 break; 3745 default: 3746 return -EINVAL; 3747 } 3748 3749 return 0; 3750err: 3751 dprintk(FE_ERROR, 1, "I/O error"); 3752 return -1; 3753} 3754 3755 3756static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe) 3757{ 3758 return DVBFE_ALGO_CUSTOM; 3759} 3760 3761static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd) 3762{ 3763 struct stv090x_state *state = fe->demodulator_priv; 3764 u32 reg, idle = 0, fifo_full = 1; 3765 int i; 3766 3767 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3768 3769 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 3770 (state->config->diseqc_envelope_mode) ? 4 : 2); 3771 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3772 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3773 goto err; 3774 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3775 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3776 goto err; 3777 3778 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); 3779 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3780 goto err; 3781 3782 for (i = 0; i < cmd->msg_len; i++) { 3783 3784 while (fifo_full) { 3785 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3786 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); 3787 } 3788 3789 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0) 3790 goto err; 3791 } 3792 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3793 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); 3794 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3795 goto err; 3796 3797 i = 0; 3798 3799 while ((!idle) && (i < 10)) { 3800 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3801 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); 3802 msleep(10); 3803 i++; 3804 } 3805 3806 return 0; 3807err: 3808 dprintk(FE_ERROR, 1, "I/O error"); 3809 return -1; 3810} 3811 3812static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) 3813{ 3814 struct stv090x_state *state = fe->demodulator_priv; 3815 u32 reg, idle = 0, fifo_full = 1; 3816 u8 mode, value; 3817 int i; 3818 3819 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3820 3821 if (burst == SEC_MINI_A) { 3822 mode = (state->config->diseqc_envelope_mode) ? 5 : 3; 3823 value = 0x00; 3824 } else { 3825 mode = (state->config->diseqc_envelope_mode) ? 4 : 2; 3826 value = 0xFF; 3827 } 3828 3829 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode); 3830 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3831 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3832 goto err; 3833 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3834 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3835 goto err; 3836 3837 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); 3838 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3839 goto err; 3840 3841 while (fifo_full) { 3842 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3843 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); 3844 } 3845 3846 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0) 3847 goto err; 3848 3849 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3850 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); 3851 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3852 goto err; 3853 3854 i = 0; 3855 3856 while ((!idle) && (i < 10)) { 3857 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3858 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); 3859 msleep(10); 3860 i++; 3861 } 3862 3863 return 0; 3864err: 3865 dprintk(FE_ERROR, 1, "I/O error"); 3866 return -1; 3867} 3868 3869static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply) 3870{ 3871 struct stv090x_state *state = fe->demodulator_priv; 3872 u32 reg = 0, i = 0, rx_end = 0; 3873 3874 while ((rx_end != 1) && (i < 10)) { 3875 msleep(10); 3876 i++; 3877 reg = STV090x_READ_DEMOD(state, DISRX_ST0); 3878 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD); 3879 } 3880 3881 if (rx_end) { 3882 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD); 3883 for (i = 0; i < reply->msg_len; i++) 3884 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA); 3885 } 3886 3887 return 0; 3888} 3889 3890static int stv090x_sleep(struct dvb_frontend *fe) 3891{ 3892 struct stv090x_state *state = fe->demodulator_priv; 3893 u32 reg; 3894 u8 full_standby = 0; 3895 3896 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3897 goto err; 3898 3899 if (state->config->tuner_sleep) { 3900 if (state->config->tuner_sleep(fe) < 0) 3901 goto err_gateoff; 3902 } 3903 3904 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3905 goto err; 3906 3907 dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep", 3908 state->device == STV0900 ? "STV0900" : "STV0903", 3909 state->demod); 3910 3911 mutex_lock(&state->internal->demod_lock); 3912 3913 switch (state->demod) { 3914 case STV090x_DEMODULATOR_0: 3915 /* power off ADC 1 */ 3916 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 3917 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0); 3918 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 3919 goto err_unlock; 3920 /* power off DiSEqC 1 */ 3921 reg = stv090x_read_reg(state, STV090x_TSTTNR2); 3922 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0); 3923 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) 3924 goto err_unlock; 3925 3926 /* check whether path 2 is already sleeping, that is when 3927 ADC2 is off */ 3928 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 3929 if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0) 3930 full_standby = 1; 3931 3932 /* stop clocks */ 3933 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 3934 /* packet delineator 1 clock */ 3935 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1); 3936 /* ADC 1 clock */ 3937 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1); 3938 /* FEC clock is shared between the two paths, only stop it 3939 when full standby is possible */ 3940 if (full_standby) 3941 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); 3942 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 3943 goto err_unlock; 3944 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 3945 /* sampling 1 clock */ 3946 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1); 3947 /* viterbi 1 clock */ 3948 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1); 3949 /* TS clock is shared between the two paths, only stop it 3950 when full standby is possible */ 3951 if (full_standby) 3952 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); 3953 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 3954 goto err_unlock; 3955 break; 3956 3957 case STV090x_DEMODULATOR_1: 3958 /* power off ADC 2 */ 3959 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 3960 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0); 3961 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) 3962 goto err_unlock; 3963 /* power off DiSEqC 2 */ 3964 reg = stv090x_read_reg(state, STV090x_TSTTNR4); 3965 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0); 3966 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) 3967 goto err_unlock; 3968 3969 /* check whether path 1 is already sleeping, that is when 3970 ADC1 is off */ 3971 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 3972 if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0) 3973 full_standby = 1; 3974 3975 /* stop clocks */ 3976 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 3977 /* packet delineator 2 clock */ 3978 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1); 3979 /* ADC 2 clock */ 3980 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1); 3981 /* FEC clock is shared between the two paths, only stop it 3982 when full standby is possible */ 3983 if (full_standby) 3984 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); 3985 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 3986 goto err_unlock; 3987 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 3988 /* sampling 2 clock */ 3989 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1); 3990 /* viterbi 2 clock */ 3991 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1); 3992 /* TS clock is shared between the two paths, only stop it 3993 when full standby is possible */ 3994 if (full_standby) 3995 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); 3996 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 3997 goto err_unlock; 3998 break; 3999 4000 default: 4001 dprintk(FE_ERROR, 1, "Wrong demodulator!"); 4002 break; 4003 } 4004 4005 if (full_standby) { 4006 /* general power off */ 4007 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4008 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01); 4009 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) 4010 goto err_unlock; 4011 } 4012 4013 mutex_unlock(&state->internal->demod_lock); 4014 return 0; 4015 4016err_gateoff: 4017 stv090x_i2c_gate_ctrl(state, 0); 4018 goto err; 4019err_unlock: 4020 mutex_unlock(&state->internal->demod_lock); 4021err: 4022 dprintk(FE_ERROR, 1, "I/O error"); 4023 return -1; 4024} 4025 4026static int stv090x_wakeup(struct dvb_frontend *fe) 4027{ 4028 struct stv090x_state *state = fe->demodulator_priv; 4029 u32 reg; 4030 4031 dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby", 4032 state->device == STV0900 ? "STV0900" : "STV0903", 4033 state->demod); 4034 4035 mutex_lock(&state->internal->demod_lock); 4036 4037 /* general power on */ 4038 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4039 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00); 4040 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) 4041 goto err; 4042 4043 switch (state->demod) { 4044 case STV090x_DEMODULATOR_0: 4045 /* power on ADC 1 */ 4046 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 4047 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1); 4048 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 4049 goto err; 4050 /* power on DiSEqC 1 */ 4051 reg = stv090x_read_reg(state, STV090x_TSTTNR2); 4052 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1); 4053 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) 4054 goto err; 4055 4056 /* activate clocks */ 4057 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 4058 /* packet delineator 1 clock */ 4059 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0); 4060 /* ADC 1 clock */ 4061 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0); 4062 /* FEC clock */ 4063 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); 4064 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 4065 goto err; 4066 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 4067 /* sampling 1 clock */ 4068 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0); 4069 /* viterbi 1 clock */ 4070 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0); 4071 /* TS clock */ 4072 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); 4073 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 4074 goto err; 4075 break; 4076 4077 case STV090x_DEMODULATOR_1: 4078 /* power on ADC 2 */ 4079 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 4080 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1); 4081 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) 4082 goto err; 4083 /* power on DiSEqC 2 */ 4084 reg = stv090x_read_reg(state, STV090x_TSTTNR4); 4085 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1); 4086 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) 4087 goto err; 4088 4089 /* activate clocks */ 4090 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 4091 /* packet delineator 2 clock */ 4092 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0); 4093 /* ADC 2 clock */ 4094 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0); 4095 /* FEC clock */ 4096 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); 4097 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 4098 goto err; 4099 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 4100 /* sampling 2 clock */ 4101 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0); 4102 /* viterbi 2 clock */ 4103 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0); 4104 /* TS clock */ 4105 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); 4106 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 4107 goto err; 4108 break; 4109 4110 default: 4111 dprintk(FE_ERROR, 1, "Wrong demodulator!"); 4112 break; 4113 } 4114 4115 mutex_unlock(&state->internal->demod_lock); 4116 return 0; 4117err: 4118 mutex_unlock(&state->internal->demod_lock); 4119 dprintk(FE_ERROR, 1, "I/O error"); 4120 return -1; 4121} 4122 4123static void stv090x_release(struct dvb_frontend *fe) 4124{ 4125 struct stv090x_state *state = fe->demodulator_priv; 4126 4127 state->internal->num_used--; 4128 if (state->internal->num_used <= 0) { 4129 4130 dprintk(FE_ERROR, 1, "Actually removing"); 4131 4132 remove_dev(state->internal); 4133 kfree(state->internal); 4134 } 4135 4136 kfree(state); 4137} 4138 4139static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode) 4140{ 4141 u32 reg = 0; 4142 4143 reg = stv090x_read_reg(state, STV090x_GENCFG); 4144 4145 switch (ldpc_mode) { 4146 case STV090x_DUAL: 4147 default: 4148 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) { 4149 /* set LDPC to dual mode */ 4150 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0) 4151 goto err; 4152 4153 state->demod_mode = STV090x_DUAL; 4154 4155 reg = stv090x_read_reg(state, STV090x_TSTRES0); 4156 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); 4157 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4158 goto err; 4159 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); 4160 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4161 goto err; 4162 4163 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 4164 goto err; 4165 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) 4166 goto err; 4167 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) 4168 goto err; 4169 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) 4170 goto err; 4171 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) 4172 goto err; 4173 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) 4174 goto err; 4175 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) 4176 goto err; 4177 4178 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) 4179 goto err; 4180 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) 4181 goto err; 4182 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) 4183 goto err; 4184 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) 4185 goto err; 4186 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) 4187 goto err; 4188 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) 4189 goto err; 4190 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) 4191 goto err; 4192 4193 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) 4194 goto err; 4195 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) 4196 goto err; 4197 } 4198 break; 4199 4200 case STV090x_SINGLE: 4201 if (stv090x_stop_modcod(state) < 0) 4202 goto err; 4203 if (stv090x_activate_modcod_single(state) < 0) 4204 goto err; 4205 4206 if (state->demod == STV090x_DEMODULATOR_1) { 4207 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */ 4208 goto err; 4209 } else { 4210 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */ 4211 goto err; 4212 } 4213 4214 reg = stv090x_read_reg(state, STV090x_TSTRES0); 4215 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); 4216 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4217 goto err; 4218 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); 4219 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4220 goto err; 4221 4222 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 4223 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01); 4224 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 4225 goto err; 4226 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00); 4227 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 4228 goto err; 4229 break; 4230 } 4231 4232 return 0; 4233err: 4234 dprintk(FE_ERROR, 1, "I/O error"); 4235 return -1; 4236} 4237 4238/* return (Hz), clk in Hz*/ 4239static u32 stv090x_get_mclk(struct stv090x_state *state) 4240{ 4241 const struct stv090x_config *config = state->config; 4242 u32 div, reg; 4243 u8 ratio; 4244 4245 div = stv090x_read_reg(state, STV090x_NCOARSE); 4246 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4247 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6; 4248 4249 return (div + 1) * config->xtal / ratio; /* kHz */ 4250} 4251 4252static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk) 4253{ 4254 const struct stv090x_config *config = state->config; 4255 u32 reg, div, clk_sel; 4256 4257 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4258 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6); 4259 4260 div = ((clk_sel * mclk) / config->xtal) - 1; 4261 4262 reg = stv090x_read_reg(state, STV090x_NCOARSE); 4263 STV090x_SETFIELD(reg, M_DIV_FIELD, div); 4264 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0) 4265 goto err; 4266 4267 state->internal->mclk = stv090x_get_mclk(state); 4268 4269 /*Set the DiseqC frequency to 22KHz */ 4270 div = state->internal->mclk / 704000; 4271 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0) 4272 goto err; 4273 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0) 4274 goto err; 4275 4276 return 0; 4277err: 4278 dprintk(FE_ERROR, 1, "I/O error"); 4279 return -1; 4280} 4281 4282static int stv0900_set_tspath(struct stv090x_state *state) 4283{ 4284 u32 reg; 4285 4286 if (state->internal->dev_ver >= 0x20) { 4287 switch (state->config->ts1_mode) { 4288 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4289 case STV090x_TSMODE_DVBCI: 4290 switch (state->config->ts2_mode) { 4291 case STV090x_TSMODE_SERIAL_PUNCTURED: 4292 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4293 default: 4294 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); 4295 break; 4296 4297 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4298 case STV090x_TSMODE_DVBCI: 4299 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */ 4300 goto err; 4301 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4302 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4303 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4304 goto err; 4305 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); 4306 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4307 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) 4308 goto err; 4309 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) 4310 goto err; 4311 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) 4312 goto err; 4313 break; 4314 } 4315 break; 4316 4317 case STV090x_TSMODE_SERIAL_PUNCTURED: 4318 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4319 default: 4320 switch (state->config->ts2_mode) { 4321 case STV090x_TSMODE_SERIAL_PUNCTURED: 4322 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4323 default: 4324 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) 4325 goto err; 4326 break; 4327 4328 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4329 case STV090x_TSMODE_DVBCI: 4330 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0) 4331 goto err; 4332 break; 4333 } 4334 break; 4335 } 4336 } else { 4337 switch (state->config->ts1_mode) { 4338 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4339 case STV090x_TSMODE_DVBCI: 4340 switch (state->config->ts2_mode) { 4341 case STV090x_TSMODE_SERIAL_PUNCTURED: 4342 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4343 default: 4344 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); 4345 break; 4346 4347 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4348 case STV090x_TSMODE_DVBCI: 4349 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16); 4350 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4351 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4352 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4353 goto err; 4354 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4355 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0); 4356 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4357 goto err; 4358 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) 4359 goto err; 4360 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) 4361 goto err; 4362 break; 4363 } 4364 break; 4365 4366 case STV090x_TSMODE_SERIAL_PUNCTURED: 4367 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4368 default: 4369 switch (state->config->ts2_mode) { 4370 case STV090x_TSMODE_SERIAL_PUNCTURED: 4371 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4372 default: 4373 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); 4374 break; 4375 4376 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4377 case STV090x_TSMODE_DVBCI: 4378 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12); 4379 break; 4380 } 4381 break; 4382 } 4383 } 4384 4385 switch (state->config->ts1_mode) { 4386 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4387 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4388 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4389 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4390 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4391 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4392 goto err; 4393 break; 4394 4395 case STV090x_TSMODE_DVBCI: 4396 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4397 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4398 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4399 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4400 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4401 goto err; 4402 break; 4403 4404 case STV090x_TSMODE_SERIAL_PUNCTURED: 4405 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4406 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4407 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4408 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4409 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4410 goto err; 4411 break; 4412 4413 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4414 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4415 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4416 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4417 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4418 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4419 goto err; 4420 break; 4421 4422 default: 4423 break; 4424 } 4425 4426 switch (state->config->ts2_mode) { 4427 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4428 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4429 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4430 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4431 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4432 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4433 goto err; 4434 break; 4435 4436 case STV090x_TSMODE_DVBCI: 4437 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4438 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4439 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4440 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4441 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4442 goto err; 4443 break; 4444 4445 case STV090x_TSMODE_SERIAL_PUNCTURED: 4446 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4447 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4448 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4449 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4450 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4451 goto err; 4452 break; 4453 4454 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4455 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4456 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4457 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4458 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4459 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4460 goto err; 4461 break; 4462 4463 default: 4464 break; 4465 } 4466 4467 if (state->config->ts1_clk > 0) { 4468 u32 speed; 4469 4470 switch (state->config->ts1_mode) { 4471 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4472 case STV090x_TSMODE_DVBCI: 4473 default: 4474 speed = state->internal->mclk / 4475 (state->config->ts1_clk / 4); 4476 if (speed < 0x08) 4477 speed = 0x08; 4478 if (speed > 0xFF) 4479 speed = 0xFF; 4480 break; 4481 case STV090x_TSMODE_SERIAL_PUNCTURED: 4482 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4483 speed = state->internal->mclk / 4484 (state->config->ts1_clk / 32); 4485 if (speed < 0x20) 4486 speed = 0x20; 4487 if (speed > 0xFF) 4488 speed = 0xFF; 4489 break; 4490 } 4491 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4492 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4493 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4494 goto err; 4495 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) 4496 goto err; 4497 } 4498 4499 if (state->config->ts2_clk > 0) { 4500 u32 speed; 4501 4502 switch (state->config->ts2_mode) { 4503 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4504 case STV090x_TSMODE_DVBCI: 4505 default: 4506 speed = state->internal->mclk / 4507 (state->config->ts2_clk / 4); 4508 if (speed < 0x08) 4509 speed = 0x08; 4510 if (speed > 0xFF) 4511 speed = 0xFF; 4512 break; 4513 case STV090x_TSMODE_SERIAL_PUNCTURED: 4514 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4515 speed = state->internal->mclk / 4516 (state->config->ts2_clk / 32); 4517 if (speed < 0x20) 4518 speed = 0x20; 4519 if (speed > 0xFF) 4520 speed = 0xFF; 4521 break; 4522 } 4523 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); 4524 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4525 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) 4526 goto err; 4527 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0) 4528 goto err; 4529 } 4530 4531 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4532 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4533 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4534 goto err; 4535 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4536 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4537 goto err; 4538 4539 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4540 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4541 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4542 goto err; 4543 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4544 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4545 goto err; 4546 4547 return 0; 4548err: 4549 dprintk(FE_ERROR, 1, "I/O error"); 4550 return -1; 4551} 4552 4553static int stv0903_set_tspath(struct stv090x_state *state) 4554{ 4555 u32 reg; 4556 4557 if (state->internal->dev_ver >= 0x20) { 4558 switch (state->config->ts1_mode) { 4559 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4560 case STV090x_TSMODE_DVBCI: 4561 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); 4562 break; 4563 4564 case STV090x_TSMODE_SERIAL_PUNCTURED: 4565 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4566 default: 4567 stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c); 4568 break; 4569 } 4570 } else { 4571 switch (state->config->ts1_mode) { 4572 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4573 case STV090x_TSMODE_DVBCI: 4574 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); 4575 break; 4576 4577 case STV090x_TSMODE_SERIAL_PUNCTURED: 4578 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4579 default: 4580 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); 4581 break; 4582 } 4583 } 4584 4585 switch (state->config->ts1_mode) { 4586 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4587 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4588 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4589 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4590 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4591 goto err; 4592 break; 4593 4594 case STV090x_TSMODE_DVBCI: 4595 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4596 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4597 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4598 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4599 goto err; 4600 break; 4601 4602 case STV090x_TSMODE_SERIAL_PUNCTURED: 4603 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4604 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4605 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4606 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4607 goto err; 4608 break; 4609 4610 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4611 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4612 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4613 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4614 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4615 goto err; 4616 break; 4617 4618 default: 4619 break; 4620 } 4621 4622 if (state->config->ts1_clk > 0) { 4623 u32 speed; 4624 4625 switch (state->config->ts1_mode) { 4626 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4627 case STV090x_TSMODE_DVBCI: 4628 default: 4629 speed = state->internal->mclk / 4630 (state->config->ts1_clk / 4); 4631 if (speed < 0x08) 4632 speed = 0x08; 4633 if (speed > 0xFF) 4634 speed = 0xFF; 4635 break; 4636 case STV090x_TSMODE_SERIAL_PUNCTURED: 4637 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4638 speed = state->internal->mclk / 4639 (state->config->ts1_clk / 32); 4640 if (speed < 0x20) 4641 speed = 0x20; 4642 if (speed > 0xFF) 4643 speed = 0xFF; 4644 break; 4645 } 4646 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4647 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4648 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4649 goto err; 4650 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) 4651 goto err; 4652 } 4653 4654 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4655 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4656 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4657 goto err; 4658 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4659 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4660 goto err; 4661 4662 return 0; 4663err: 4664 dprintk(FE_ERROR, 1, "I/O error"); 4665 return -1; 4666} 4667 4668static int stv090x_init(struct dvb_frontend *fe) 4669{ 4670 struct stv090x_state *state = fe->demodulator_priv; 4671 const struct stv090x_config *config = state->config; 4672 u32 reg; 4673 4674 if (state->internal->mclk == 0) { 4675 /* call tuner init to configure the tuner's clock output 4676 divider directly before setting up the master clock of 4677 the stv090x. */ 4678 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 4679 goto err; 4680 4681 if (config->tuner_init) { 4682 if (config->tuner_init(fe) < 0) 4683 goto err_gateoff; 4684 } 4685 4686 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 4687 goto err; 4688 4689 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */ 4690 msleep(5); 4691 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 4692 0x20 | config->clk_mode) < 0) 4693 goto err; 4694 stv090x_get_mclk(state); 4695 } 4696 4697 if (stv090x_wakeup(fe) < 0) { 4698 dprintk(FE_ERROR, 1, "Error waking device"); 4699 goto err; 4700 } 4701 4702 if (stv090x_ldpc_mode(state, state->demod_mode) < 0) 4703 goto err; 4704 4705 reg = STV090x_READ_DEMOD(state, TNRCFG2); 4706 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion); 4707 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0) 4708 goto err; 4709 reg = STV090x_READ_DEMOD(state, DEMOD); 4710 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); 4711 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 4712 goto err; 4713 4714 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 4715 goto err; 4716 4717 if (config->tuner_set_mode) { 4718 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0) 4719 goto err_gateoff; 4720 } 4721 4722 if (config->tuner_init) { 4723 if (config->tuner_init(fe) < 0) 4724 goto err_gateoff; 4725 } 4726 4727 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 4728 goto err; 4729 4730 if (state->device == STV0900) { 4731 if (stv0900_set_tspath(state) < 0) 4732 goto err; 4733 } else { 4734 if (stv0903_set_tspath(state) < 0) 4735 goto err; 4736 } 4737 4738 return 0; 4739 4740err_gateoff: 4741 stv090x_i2c_gate_ctrl(state, 0); 4742err: 4743 dprintk(FE_ERROR, 1, "I/O error"); 4744 return -1; 4745} 4746 4747static int stv090x_setup(struct dvb_frontend *fe) 4748{ 4749 struct stv090x_state *state = fe->demodulator_priv; 4750 const struct stv090x_config *config = state->config; 4751 const struct stv090x_reg *stv090x_initval = NULL; 4752 const struct stv090x_reg *stv090x_cut20_val = NULL; 4753 unsigned long t1_size = 0, t2_size = 0; 4754 u32 reg = 0; 4755 4756 int i; 4757 4758 if (state->device == STV0900) { 4759 dprintk(FE_DEBUG, 1, "Initializing STV0900"); 4760 stv090x_initval = stv0900_initval; 4761 t1_size = ARRAY_SIZE(stv0900_initval); 4762 stv090x_cut20_val = stv0900_cut20_val; 4763 t2_size = ARRAY_SIZE(stv0900_cut20_val); 4764 } else if (state->device == STV0903) { 4765 dprintk(FE_DEBUG, 1, "Initializing STV0903"); 4766 stv090x_initval = stv0903_initval; 4767 t1_size = ARRAY_SIZE(stv0903_initval); 4768 stv090x_cut20_val = stv0903_cut20_val; 4769 t2_size = ARRAY_SIZE(stv0903_cut20_val); 4770 } 4771 4772 /* STV090x init */ 4773 4774 /* Stop Demod */ 4775 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0) 4776 goto err; 4777 if (state->device == STV0900) 4778 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0) 4779 goto err; 4780 4781 msleep(5); 4782 4783 /* Set No Tuner Mode */ 4784 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0) 4785 goto err; 4786 if (state->device == STV0900) 4787 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0) 4788 goto err; 4789 4790 /* I2C repeater OFF */ 4791 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level); 4792 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0) 4793 goto err; 4794 if (state->device == STV0900) 4795 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) 4796 goto err; 4797 4798 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */ 4799 goto err; 4800 msleep(5); 4801 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */ 4802 goto err; 4803 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */ 4804 goto err; 4805 msleep(5); 4806 4807 /* write initval */ 4808 dprintk(FE_DEBUG, 1, "Setting up initial values"); 4809 for (i = 0; i < t1_size; i++) { 4810 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0) 4811 goto err; 4812 } 4813 4814 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID); 4815 if (state->internal->dev_ver >= 0x20) { 4816 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) 4817 goto err; 4818 4819 /* write cut20_val*/ 4820 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values"); 4821 for (i = 0; i < t2_size; i++) { 4822 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0) 4823 goto err; 4824 } 4825 4826 } else if (state->internal->dev_ver < 0x20) { 4827 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!", 4828 state->internal->dev_ver); 4829 4830 goto err; 4831 } else if (state->internal->dev_ver > 0x30) { 4832 /* we shouldn't bail out from here */ 4833 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!", 4834 state->internal->dev_ver); 4835 } 4836 4837 /* ADC1 range */ 4838 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 4839 STV090x_SETFIELD(reg, ADC1_INMODE_FIELD, 4840 (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1); 4841 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 4842 goto err; 4843 4844 /* ADC2 range */ 4845 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 4846 STV090x_SETFIELD(reg, ADC2_INMODE_FIELD, 4847 (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1); 4848 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) 4849 goto err; 4850 4851 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0) 4852 goto err; 4853 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0) 4854 goto err; 4855 4856 return 0; 4857err: 4858 dprintk(FE_ERROR, 1, "I/O error"); 4859 return -1; 4860} 4861 4862int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, u8 value, 4863 u8 xor_value) 4864{ 4865 struct stv090x_state *state = fe->demodulator_priv; 4866 u8 reg = 0; 4867 4868 STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir); 4869 STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value); 4870 STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value); 4871 4872 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg); 4873} 4874EXPORT_SYMBOL(stv090x_set_gpio); 4875 4876static struct dvb_frontend_ops stv090x_ops = { 4877 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, 4878 .info = { 4879 .name = "STV090x Multistandard", 4880 .frequency_min = 950000, 4881 .frequency_max = 2150000, 4882 .frequency_stepsize = 0, 4883 .frequency_tolerance = 0, 4884 .symbol_rate_min = 1000000, 4885 .symbol_rate_max = 45000000, 4886 .caps = FE_CAN_INVERSION_AUTO | 4887 FE_CAN_FEC_AUTO | 4888 FE_CAN_QPSK | 4889 FE_CAN_2G_MODULATION 4890 }, 4891 4892 .release = stv090x_release, 4893 .init = stv090x_init, 4894 4895 .sleep = stv090x_sleep, 4896 .get_frontend_algo = stv090x_frontend_algo, 4897 4898 .diseqc_send_master_cmd = stv090x_send_diseqc_msg, 4899 .diseqc_send_burst = stv090x_send_diseqc_burst, 4900 .diseqc_recv_slave_reply = stv090x_recv_slave_reply, 4901 .set_tone = stv090x_set_tone, 4902 4903 .search = stv090x_search, 4904 .read_status = stv090x_read_status, 4905 .read_ber = stv090x_read_per, 4906 .read_signal_strength = stv090x_read_signal_strength, 4907 .read_snr = stv090x_read_cnr, 4908}; 4909 4910 4911struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, 4912 struct i2c_adapter *i2c, 4913 enum stv090x_demodulator demod) 4914{ 4915 struct stv090x_state *state = NULL; 4916 struct stv090x_dev *temp_int; 4917 4918 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL); 4919 if (state == NULL) 4920 goto error; 4921 4922 state->verbose = &verbose; 4923 state->config = config; 4924 state->i2c = i2c; 4925 state->frontend.ops = stv090x_ops; 4926 state->frontend.demodulator_priv = state; 4927 state->demod = demod; 4928 state->demod_mode = config->demod_mode; /* Single or Dual mode */ 4929 state->device = config->device; 4930 state->rolloff = STV090x_RO_35; /* default */ 4931 4932 temp_int = find_dev(state->i2c, 4933 state->config->address); 4934 4935 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) { 4936 state->internal = temp_int->internal; 4937 state->internal->num_used++; 4938 dprintk(FE_INFO, 1, "Found Internal Structure!"); 4939 } else { 4940 state->internal = kmalloc(sizeof(struct stv090x_internal), 4941 GFP_KERNEL); 4942 if (!state->internal) 4943 goto error; 4944 temp_int = append_internal(state->internal); 4945 if (!temp_int) { 4946 kfree(state->internal); 4947 goto error; 4948 } 4949 state->internal->num_used = 1; 4950 state->internal->mclk = 0; 4951 state->internal->dev_ver = 0; 4952 state->internal->i2c_adap = state->i2c; 4953 state->internal->i2c_addr = state->config->address; 4954 dprintk(FE_INFO, 1, "Create New Internal Structure!"); 4955 4956 mutex_init(&state->internal->demod_lock); 4957 mutex_init(&state->internal->tuner_lock); 4958 4959 if (stv090x_setup(&state->frontend) < 0) { 4960 dprintk(FE_ERROR, 1, "Error setting up device"); 4961 goto err_remove; 4962 } 4963 } 4964 4965 if (state->internal->dev_ver >= 0x30) 4966 state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM; 4967 4968 /* workaround for stuck DiSEqC output */ 4969 if (config->diseqc_envelope_mode) 4970 stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A); 4971 4972 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x", 4973 state->device == STV0900 ? "STV0900" : "STV0903", 4974 demod, 4975 state->internal->dev_ver); 4976 4977 return &state->frontend; 4978 4979err_remove: 4980 remove_dev(state->internal); 4981 kfree(state->internal); 4982error: 4983 kfree(state); 4984 return NULL; 4985} 4986EXPORT_SYMBOL(stv090x_attach); 4987MODULE_PARM_DESC(verbose, "Set Verbosity level"); 4988MODULE_AUTHOR("Manu Abraham"); 4989MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend"); 4990MODULE_LICENSE("GPL"); 4991