1/**
2 * Driver for Zarlink zl10036 DVB-S silicon tuner
3 *
4 * Copyright (C) 2006 Tino Reichardt
5 * Copyright (C) 2007-2009 Matthias Schwarzott <zzam@gentoo.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License Version 2, as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 **
21 * The data sheet for this tuner can be found at:
22 *    http://www.mcmilk.de/projects/dvb-card/datasheets/ZL10036.pdf
23 *
24 * This one is working: (at my Avermedia DVB-S Pro)
25 * - zl10036 (40pin, FTA)
26 *
27 * A driver for zl10038 should be very similar.
28 */
29
30#include <linux/module.h>
31#include <linux/dvb/frontend.h>
32#include <linux/slab.h>
33#include <linux/types.h>
34
35#include "zl10036.h"
36
37static int zl10036_debug;
38#define dprintk(level, args...) \
39	do { if (zl10036_debug & level) printk(KERN_DEBUG "zl10036: " args); \
40	} while (0)
41
42#define deb_info(args...)  dprintk(0x01, args)
43#define deb_i2c(args...)  dprintk(0x02, args)
44
45struct zl10036_state {
46	struct i2c_adapter *i2c;
47	const struct zl10036_config *config;
48	u32 frequency;
49	u8 br, bf;
50};
51
52
53/* This driver assumes the tuner is driven by a 10.111MHz Cristal */
54#define _XTAL 10111
55
56/* Some of the possible dividers:
57 *   64, (write 0x05 to reg), freq step size   158kHz
58 *   10, (write 0x0a to reg), freq step size 1.011kHz (used here)
59 *    5, (write 0x09 to reg), freq step size 2.022kHz
60 */
61
62#define _RDIV 10
63#define _RDIV_REG 0x0a
64#define _FR   (_XTAL/_RDIV)
65
66#define STATUS_POR 0x80 /* Power on Reset */
67#define STATUS_FL  0x40 /* Frequency & Phase Lock */
68
69/* read/write for zl10036 and zl10038 */
70
71static int zl10036_read_status_reg(struct zl10036_state *state)
72{
73	u8 status;
74	struct i2c_msg msg[1] = {
75		{ .addr = state->config->tuner_address, .flags = I2C_M_RD,
76		  .buf = &status, .len = sizeof(status) },
77	};
78
79	if (i2c_transfer(state->i2c, msg, 1) != 1) {
80		printk(KERN_ERR "%s: i2c read failed at addr=%02x\n",
81			__func__, state->config->tuner_address);
82		return -EIO;
83	}
84
85	deb_i2c("R(status): %02x  [FL=%d]\n", status,
86		(status & STATUS_FL) ? 1 : 0);
87	if (status & STATUS_POR)
88		deb_info("%s: Power-On-Reset bit enabled - "
89			"need to initialize the tuner\n", __func__);
90
91	return status;
92}
93
94static int zl10036_write(struct zl10036_state *state, u8 buf[], u8 count)
95{
96	struct i2c_msg msg[1] = {
97		{ .addr = state->config->tuner_address, .flags = 0,
98		  .buf = buf, .len = count },
99	};
100	u8 reg = 0;
101	int ret;
102
103	if (zl10036_debug & 0x02) {
104		/* every 8bit-value satisifes this!
105		 * so only check for debug log */
106		if ((buf[0] & 0x80) == 0x00)
107			reg = 2;
108		else if ((buf[0] & 0xc0) == 0x80)
109			reg = 4;
110		else if ((buf[0] & 0xf0) == 0xc0)
111			reg = 6;
112		else if ((buf[0] & 0xf0) == 0xd0)
113			reg = 8;
114		else if ((buf[0] & 0xf0) == 0xe0)
115			reg = 10;
116		else if ((buf[0] & 0xf0) == 0xf0)
117			reg = 12;
118
119		deb_i2c("W(%d):", reg);
120		{
121			int i;
122			for (i = 0; i < count; i++)
123				printk(KERN_CONT " %02x", buf[i]);
124			printk(KERN_CONT "\n");
125		}
126	}
127
128	ret = i2c_transfer(state->i2c, msg, 1);
129	if (ret != 1) {
130		printk(KERN_ERR "%s: i2c error, ret=%d\n", __func__, ret);
131		return -EIO;
132	}
133
134	return 0;
135}
136
137static int zl10036_release(struct dvb_frontend *fe)
138{
139	struct zl10036_state *state = fe->tuner_priv;
140
141	fe->tuner_priv = NULL;
142	kfree(state);
143
144	return 0;
145}
146
147static int zl10036_sleep(struct dvb_frontend *fe)
148{
149	struct zl10036_state *state = fe->tuner_priv;
150	u8 buf[] = { 0xf0, 0x80 }; /* regs 12/13 */
151	int ret;
152
153	deb_info("%s\n", __func__);
154
155	if (fe->ops.i2c_gate_ctrl)
156		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
157
158	ret = zl10036_write(state, buf, sizeof(buf));
159
160	if (fe->ops.i2c_gate_ctrl)
161		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
162
163	return ret;
164}
165
166/**
167 * register map of the ZL10036/ZL10038
168 *
169 * reg[default] content
170 *  2[0x00]:   0 | N14 | N13 | N12 | N11 | N10 |  N9 |  N8
171 *  3[0x00]:  N7 |  N6 |  N5 |  N4 |  N3 |  N2 |  N1 |  N0
172 *  4[0x80]:   1 |   0 | RFG | BA1 | BA0 | BG1 | BG0 | LEN
173 *  5[0x00]:  P0 |  C1 |  C0 |  R4 |  R3 |  R2 |  R1 |  R0
174 *  6[0xc0]:   1 |   1 |   0 |   0 | RSD |   0 |   0 |   0
175 *  7[0x20]:  P1 | BF6 | BF5 | BF4 | BF3 | BF2 | BF1 |   0
176 *  8[0xdb]:   1 |   1 |   0 |   1 |   0 |  CC |   1 |   1
177 *  9[0x30]: VSD |  V2 |  V1 |  V0 |  S3 |  S2 |  S1 |  S0
178 * 10[0xe1]:   1 |   1 |   1 |   0 |   0 | LS2 | LS1 | LS0
179 * 11[0xf5]:  WS | WH2 | WH1 | WH0 | WL2 | WL1 | WL0 | WRE
180 * 12[0xf0]:   1 |   1 |   1 |   1 |   0 |   0 |   0 |   0
181 * 13[0x28]:  PD | BR4 | BR3 | BR2 | BR1 | BR0 | CLR |  TL
182 */
183
184static int zl10036_set_frequency(struct zl10036_state *state, u32 frequency)
185{
186	u8 buf[2];
187	u32 div, foffset;
188
189	div = (frequency + _FR/2) / _FR;
190	state->frequency = div * _FR;
191
192	foffset = frequency - state->frequency;
193
194	buf[0] = (div >> 8) & 0x7f;
195	buf[1] = (div >> 0) & 0xff;
196
197	deb_info("%s: ftodo=%u fpriv=%u ferr=%d div=%u\n", __func__,
198		frequency, state->frequency, foffset, div);
199
200	return zl10036_write(state, buf, sizeof(buf));
201}
202
203static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw)
204{
205	/* fbw is measured in kHz */
206	u8 br, bf;
207	int ret;
208	u8 buf_bf[] = {
209		0xc0, 0x00, /*   6/7: rsd=0 bf=0 */
210	};
211	u8 buf_br[] = {
212		0xf0, 0x00, /* 12/13: br=0xa clr=0 tl=0*/
213	};
214	u8 zl10036_rsd_off[] = { 0xc8 }; /* set RSD=1 */
215
216	/* ensure correct values */
217	if (fbw > 35000)
218		fbw = 35000;
219	if (fbw <  8000)
220		fbw =  8000;
221
222#define _BR_MAXIMUM (_XTAL/575) /* _XTAL / 575kHz = 17 */
223
224	/* <= 28,82 MHz */
225	if (fbw <= 28820) {
226		br = _BR_MAXIMUM;
227	} else {
228		/**
229		 *  f(bw)=34,6MHz f(xtal)=10.111MHz
230		 *  br = (10111/34600) * 63 * 1/K = 14;
231		 */
232		br = ((_XTAL * 21 * 1000) / (fbw * 419));
233	}
234
235	/* ensure correct values */
236	if (br < 4)
237		br = 4;
238	if (br > _BR_MAXIMUM)
239		br = _BR_MAXIMUM;
240
241	/*
242	 * k = 1.257
243	 * bf = fbw/_XTAL * br * k - 1 */
244
245	bf = (fbw * br * 1257) / (_XTAL * 1000) - 1;
246
247	/* ensure correct values */
248	if (bf > 62)
249		bf = 62;
250
251	buf_bf[1] = (bf << 1) & 0x7e;
252	buf_br[1] = (br << 2) & 0x7c;
253	deb_info("%s: BW=%d br=%u bf=%u\n", __func__, fbw, br, bf);
254
255	if (br != state->br) {
256		ret = zl10036_write(state, buf_br, sizeof(buf_br));
257		if (ret < 0)
258			return ret;
259	}
260
261	if (bf != state->bf) {
262		ret = zl10036_write(state, buf_bf, sizeof(buf_bf));
263		if (ret < 0)
264			return ret;
265
266		/* time = br/(32* fxtal) */
267		/* minimal sleep time to be calculated
268		 * maximum br is 63 -> max time = 2 /10 MHz = 2e-7 */
269		msleep(1);
270
271		ret = zl10036_write(state, zl10036_rsd_off,
272			sizeof(zl10036_rsd_off));
273		if (ret < 0)
274			return ret;
275	}
276
277	state->br = br;
278	state->bf = bf;
279
280	return 0;
281}
282
283static int zl10036_set_gain_params(struct zl10036_state *state,
284	int c)
285{
286	u8 buf[2];
287	u8 rfg, ba, bg;
288
289	/* default values */
290	rfg = 0; /* enable when using an lna */
291	ba = 1;
292	bg = 1;
293
294	/* reg 4 */
295	buf[0] = 0x80 | ((rfg << 5) & 0x20)
296		| ((ba  << 3) & 0x18) | ((bg  << 1) & 0x06);
297
298	if (!state->config->rf_loop_enable)
299		buf[0] |= 0x01;
300
301	/* P0=0 */
302	buf[1] = _RDIV_REG | ((c << 5) & 0x60);
303
304	deb_info("%s: c=%u rfg=%u ba=%u bg=%u\n", __func__, c, rfg, ba, bg);
305	return zl10036_write(state, buf, sizeof(buf));
306}
307
308static int zl10036_set_params(struct dvb_frontend *fe)
309{
310	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
311	struct zl10036_state *state = fe->tuner_priv;
312	int ret = 0;
313	u32 frequency = p->frequency;
314	u32 fbw;
315	int i;
316	u8 c;
317
318	/* ensure correct values
319	 * maybe redundant as core already checks this */
320	if ((frequency < fe->ops.info.frequency_min)
321	||  (frequency > fe->ops.info.frequency_max))
322		return -EINVAL;
323
324	/**
325	 * alpha = 1.35 for dvb-s
326	 * fBW = (alpha*symbolrate)/(2*0.8)
327	 * 1.35 / (2*0.8) = 27 / 32
328	 */
329	fbw = (27 * p->symbol_rate) / 32;
330
331	/* scale to kHz */
332	fbw /= 1000;
333
334	/* Add safe margin of 3MHz */
335	fbw += 3000;
336
337	/* setting the charge pump - guessed values */
338	if (frequency < 950000)
339		return -EINVAL;
340	else if (frequency < 1250000)
341		c = 0;
342	else if (frequency < 1750000)
343		c = 1;
344	else if (frequency < 2175000)
345		c = 2;
346	else
347		return -EINVAL;
348
349	if (fe->ops.i2c_gate_ctrl)
350		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
351
352	ret = zl10036_set_gain_params(state, c);
353	if (ret < 0)
354		goto error;
355
356	ret = zl10036_set_frequency(state, p->frequency);
357	if (ret < 0)
358		goto error;
359
360	ret = zl10036_set_bandwidth(state, fbw);
361	if (ret < 0)
362		goto error;
363
364	/* wait for tuner lock - no idea if this is really needed */
365	for (i = 0; i < 20; i++) {
366		ret = zl10036_read_status_reg(state);
367		if (ret < 0)
368			goto error;
369
370		/* check Frequency & Phase Lock Bit */
371		if (ret & STATUS_FL)
372			break;
373
374		msleep(10);
375	}
376
377error:
378	if (fe->ops.i2c_gate_ctrl)
379		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
380
381	return ret;
382}
383
384static int zl10036_get_frequency(struct dvb_frontend *fe, u32 *frequency)
385{
386	struct zl10036_state *state = fe->tuner_priv;
387
388	*frequency = state->frequency;
389
390	return 0;
391}
392
393static int zl10036_init_regs(struct zl10036_state *state)
394{
395	int ret;
396	int i;
397
398	/* could also be one block from reg 2 to 13 and additional 10/11 */
399	u8 zl10036_init_tab[][2] = {
400		{ 0x04, 0x00 },		/*   2/3: div=0x400 - arbitrary value */
401		{ 0x8b, _RDIV_REG },	/*   4/5: rfg=0 ba=1 bg=1 len=? */
402					/*        p0=0 c=0 r=_RDIV_REG */
403		{ 0xc0, 0x20 },		/*   6/7: rsd=0 bf=0x10 */
404		{ 0xd3, 0x40 },		/*   8/9: from datasheet */
405		{ 0xe3, 0x5b },		/* 10/11: lock window level */
406		{ 0xf0, 0x28 },		/* 12/13: br=0xa clr=0 tl=0*/
407		{ 0xe3, 0xf9 },		/* 10/11: unlock window level */
408	};
409
410	/* invalid values to trigger writing */
411	state->br = 0xff;
412	state->bf = 0xff;
413
414	if (!state->config->rf_loop_enable)
415		zl10036_init_tab[1][0] |= 0x01;
416
417	deb_info("%s\n", __func__);
418
419	for (i = 0; i < ARRAY_SIZE(zl10036_init_tab); i++) {
420		ret = zl10036_write(state, zl10036_init_tab[i], 2);
421		if (ret < 0)
422			return ret;
423	}
424
425	return 0;
426}
427
428static int zl10036_init(struct dvb_frontend *fe)
429{
430	struct zl10036_state *state = fe->tuner_priv;
431	int ret = 0;
432
433	if (fe->ops.i2c_gate_ctrl)
434		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
435
436	ret = zl10036_read_status_reg(state);
437	if (ret < 0)
438		return ret;
439
440	/* Only init if Power-on-Reset bit is set? */
441	ret = zl10036_init_regs(state);
442
443	if (fe->ops.i2c_gate_ctrl)
444		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
445
446	return ret;
447}
448
449static struct dvb_tuner_ops zl10036_tuner_ops = {
450	.info = {
451		.name = "Zarlink ZL10036",
452		.frequency_min = 950000,
453		.frequency_max = 2175000
454	},
455	.init = zl10036_init,
456	.release = zl10036_release,
457	.sleep = zl10036_sleep,
458	.set_params = zl10036_set_params,
459	.get_frequency = zl10036_get_frequency,
460};
461
462struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
463				    const struct zl10036_config *config,
464				    struct i2c_adapter *i2c)
465{
466	struct zl10036_state *state;
467	int ret;
468
469	if (!config) {
470		printk(KERN_ERR "%s: no config specified", __func__);
471		return NULL;
472	}
473
474	state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL);
475	if (!state)
476		return NULL;
477
478	state->config = config;
479	state->i2c = i2c;
480
481	if (fe->ops.i2c_gate_ctrl)
482		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
483
484	ret = zl10036_read_status_reg(state);
485	if (ret < 0) {
486		printk(KERN_ERR "%s: No zl10036 found\n", __func__);
487		goto error;
488	}
489
490	ret = zl10036_init_regs(state);
491	if (ret < 0) {
492		printk(KERN_ERR "%s: tuner initialization failed\n",
493			__func__);
494		goto error;
495	}
496
497	if (fe->ops.i2c_gate_ctrl)
498		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
499
500	fe->tuner_priv = state;
501
502	memcpy(&fe->ops.tuner_ops, &zl10036_tuner_ops,
503		sizeof(struct dvb_tuner_ops));
504	printk(KERN_INFO "%s: tuner initialization (%s addr=0x%02x) ok\n",
505		__func__, fe->ops.tuner_ops.info.name, config->tuner_address);
506
507	return fe;
508
509error:
510	kfree(state);
511	return NULL;
512}
513EXPORT_SYMBOL(zl10036_attach);
514
515module_param_named(debug, zl10036_debug, int, 0644);
516MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
517MODULE_DESCRIPTION("DVB ZL10036 driver");
518MODULE_AUTHOR("Tino Reichardt");
519MODULE_AUTHOR("Matthias Schwarzott");
520MODULE_LICENSE("GPL");
521