1b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls/* 2b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * cx18 driver PCI memory mapped IO access routines 3b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * 4b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 56afdeaf865b729287e02aafc61d8d013b89996efAndy Walls * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> 6b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * 7b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * This program is free software; you can redistribute it and/or modify 8b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * it under the terms of the GNU General Public License as published by 9b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * the Free Software Foundation; either version 2 of the License, or 10b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * (at your option) any later version. 11b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * 12b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * This program is distributed in the hope that it will be useful, 13b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * but WITHOUT ANY WARRANTY; without even the implied warranty of 14b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * GNU General Public License for more details. 16b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * 17b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * You should have received a copy of the GNU General Public License 18b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * along with this program; if not, write to the Free Software 19b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 20b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls * 02111-1307 USA 21b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls */ 22b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls 23b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls#ifndef CX18_IO_H 24b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls#define CX18_IO_H 25b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls 26b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls#include "cx18-driver.h" 27b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls 28d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls/* 29d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls * Readback and retry of MMIO access for reliability: 30d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls * The concept was suggested by Steve Toth <stoth@linuxtv.org>. 316afdeaf865b729287e02aafc61d8d013b89996efAndy Walls * The implmentation is the fault of Andy Walls <awalls@md.metrocast.net>. 323f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls * 333f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls * *write* functions are implied to retry the mmio unless suffixed with _noretry 343f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls * *read* functions never retry the mmio (it never helps to do so) 35d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls */ 36d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 37c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls/* Non byteswapping memory mapped IO */ 383f75c6161f28e6a17c547daf552c1127c805c5e7Andy Wallsstatic inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr) 393f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls{ 403f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls return __raw_readl(addr); 413f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls} 423f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls 43d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsstatic inline 44d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsvoid cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) 45c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls{ 46c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls __raw_writel(val, addr); 47c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls} 48b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls 49d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsstatic inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) 50d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls{ 513f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls int i; 523f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { 53d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls cx18_raw_writel_noretry(cx, val, addr); 543f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls if (val == cx18_raw_readl(cx, addr)) 553f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls break; 563f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls } 57d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls} 58d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 593f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls/* Normal memory mapped IO */ 603f75c6161f28e6a17c547daf552c1127c805c5e7Andy Wallsstatic inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr) 61d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls{ 623f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls return readl(addr); 63d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls} 64d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 65d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsstatic inline 663f75c6161f28e6a17c547daf552c1127c805c5e7Andy Wallsvoid cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) 67c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls{ 683f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls writel(val, addr); 69c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls} 70b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls 713f75c6161f28e6a17c547daf552c1127c805c5e7Andy Wallsstatic inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) 72d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls{ 733f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls int i; 743f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { 753f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls cx18_writel_noretry(cx, val, addr); 763f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls if (val == cx18_readl(cx, addr)) 773f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls break; 783f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls } 79d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls} 80d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 81d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsstatic inline 823f75c6161f28e6a17c547daf552c1127c805c5e7Andy Wallsvoid cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, 833f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls u32 eval, u32 mask) 84c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls{ 853f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls int i; 86daa1c164db63540fe7a52c658ce14ae6a8d1ae53Andy Walls u32 r; 873f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls eval &= mask; 883f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { 893f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls cx18_writel_noretry(cx, val, addr); 90daa1c164db63540fe7a52c658ce14ae6a8d1ae53Andy Walls r = cx18_readl(cx, addr); 91daa1c164db63540fe7a52c658ce14ae6a8d1ae53Andy Walls if (r == 0xffffffff && eval != 0xffffffff) 92daa1c164db63540fe7a52c658ce14ae6a8d1ae53Andy Walls continue; 93daa1c164db63540fe7a52c658ce14ae6a8d1ae53Andy Walls if (eval == (r & mask)) 943f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls break; 953f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls } 96c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls} 97b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls 983f75c6161f28e6a17c547daf552c1127c805c5e7Andy Wallsstatic inline u16 cx18_readw(struct cx18 *cx, const void __iomem *addr) 99d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls{ 1003f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls return readw(addr); 101d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls} 102d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 103d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsstatic inline 104d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsvoid cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) 105c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls{ 106c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls writew(val, addr); 107c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls} 108c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls 109d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsstatic inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr) 110d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls{ 1113f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls int i; 1123f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { 113d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls cx18_writew_noretry(cx, val, addr); 1143f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls if (val == cx18_readw(cx, addr)) 1153f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls break; 1163f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls } 117d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls} 118d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 1193f75c6161f28e6a17c547daf552c1127c805c5e7Andy Wallsstatic inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr) 1203f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls{ 1213f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls return readb(addr); 1223f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls} 123d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 124d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsstatic inline 125d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsvoid cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr) 126c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls{ 127c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls writeb(val, addr); 128c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls} 129c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls 130d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsstatic inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr) 131d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls{ 1323f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls int i; 1333f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { 134d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls cx18_writeb_noretry(cx, val, addr); 1353f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls if (val == cx18_readb(cx, addr)) 1363f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls break; 1373f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls } 138d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls} 139d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 140ee2d64f5ccc71b5c5191e92ea91a12b65f9ca060Andy Wallsstatic inline 141b1526421eac9a912b2cda7e147f1da2aa31be278Andy Wallsvoid cx18_memcpy_fromio(struct cx18 *cx, void *to, 142ee2d64f5ccc71b5c5191e92ea91a12b65f9ca060Andy Walls const void __iomem *from, unsigned int len) 143ee2d64f5ccc71b5c5191e92ea91a12b65f9ca060Andy Walls{ 144ee2d64f5ccc71b5c5191e92ea91a12b65f9ca060Andy Walls memcpy_fromio(to, from, len); 145ee2d64f5ccc71b5c5191e92ea91a12b65f9ca060Andy Walls} 146ee2d64f5ccc71b5c5191e92ea91a12b65f9ca060Andy Walls 147b1526421eac9a912b2cda7e147f1da2aa31be278Andy Wallsvoid cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count); 148b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls 149d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 150c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls/* Access "register" region of CX23418 memory mapped I/O */ 151d267d85101c509020a12686b96cbd179deaf4ecdAndy Wallsstatic inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg) 152d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls{ 153d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls cx18_writel_noretry(cx, val, cx->reg_mem + reg); 154d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls} 155d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 156c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Wallsstatic inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg) 157c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls{ 1583f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls cx18_writel(cx, val, cx->reg_mem + reg); 159f056d29eebd2c8800cf42528ba0470c77a928821Andy Walls} 160f056d29eebd2c8800cf42528ba0470c77a928821Andy Walls 161f056d29eebd2c8800cf42528ba0470c77a928821Andy Wallsstatic inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg, 162f056d29eebd2c8800cf42528ba0470c77a928821Andy Walls u32 eval, u32 mask) 163f056d29eebd2c8800cf42528ba0470c77a928821Andy Walls{ 1643f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask); 165c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls} 166c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls 167c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Wallsstatic inline u32 cx18_read_reg(struct cx18 *cx, u32 reg) 168c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls{ 1693f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls return cx18_readl(cx, cx->reg_mem + reg); 170c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls} 171c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls 172d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls 173c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls/* Access "encoder memory" region of CX23418 memory mapped I/O */ 174c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Wallsstatic inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr) 175c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls{ 1763f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls cx18_writel(cx, val, cx->enc_mem + addr); 177c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls} 178c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls 179c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Wallsstatic inline u32 cx18_read_enc(struct cx18 *cx, u32 addr) 180c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls{ 1813f75c6161f28e6a17c547daf552c1127c805c5e7Andy Walls return cx18_readl(cx, cx->enc_mem + addr); 182d267d85101c509020a12686b96cbd179deaf4ecdAndy Walls} 183c641d09c60bfa36c7cf70444f24265090e51f5ceAndy Walls 184b1526421eac9a912b2cda7e147f1da2aa31be278Andy Wallsvoid cx18_sw1_irq_enable(struct cx18 *cx, u32 val); 185b1526421eac9a912b2cda7e147f1da2aa31be278Andy Wallsvoid cx18_sw1_irq_disable(struct cx18 *cx, u32 val); 186b1526421eac9a912b2cda7e147f1da2aa31be278Andy Wallsvoid cx18_sw2_irq_enable(struct cx18 *cx, u32 val); 187b1526421eac9a912b2cda7e147f1da2aa31be278Andy Wallsvoid cx18_sw2_irq_disable(struct cx18 *cx, u32 val); 188d20ceecd0c5370cfe6b6eee2f63fecb65222c747Andy Wallsvoid cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val); 189b1526421eac9a912b2cda7e147f1da2aa31be278Andy Wallsvoid cx18_setup_page(struct cx18 *cx, u32 addr); 190b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls 191b1526421eac9a912b2cda7e147f1da2aa31be278Andy Walls#endif /* CX18_IO_H */ 192