1f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* 2f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * Earthsoft PT3 driver 3f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * 4f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com> 5f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * 6f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * This program is free software; you can redistribute it and/or 7f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * modify it under the terms of the GNU General Public License as 8f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * published by the Free Software Foundation version 2. 9f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * 10f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * 11f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * This program is distributed in the hope that it will be useful, 12f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * but WITHOUT ANY WARRANTY; without even the implied warranty of 13f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * GNU General Public License for more details. 15f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada */ 16f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 17f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#ifndef PT3_H 18f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define PT3_H 19f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 20f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#include <linux/atomic.h> 21f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#include <linux/types.h> 22f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 23f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#include "dvb_demux.h" 24f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#include "dvb_frontend.h" 25f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#include "dmxdev.h" 26f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 27f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#include "tc90522.h" 28f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#include "mxl301rf.h" 29f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#include "qm1d1c0042.h" 30f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 31f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define DRV_NAME KBUILD_MODNAME 32f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 33f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define PT3_NUM_FE 4 34f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 35f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* 36f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * register index of the FPGA chip 37f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada */ 38f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define REG_VERSION 0x00 39f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define REG_BUS 0x04 40f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define REG_SYSTEM_W 0x08 41f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define REG_SYSTEM_R 0x0c 42f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define REG_I2C_W 0x10 43f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define REG_I2C_R 0x14 44f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define REG_RAM_W 0x18 45f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define REG_RAM_R 0x1c 46f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define REG_DMA_BASE 0x40 /* regs for FE[i] = REG_DMA_BASE + 0x18 * i */ 47f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define OFST_DMA_DESC_L 0x00 48f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define OFST_DMA_DESC_H 0x04 49f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define OFST_DMA_CTL 0x08 50f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define OFST_TS_CTL 0x0c 51f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define OFST_STATUS 0x10 52f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define OFST_TS_ERR 0x14 53f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 54f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* 55f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * internal buffer for I2C 56f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada */ 57f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define PT3_I2C_MAX 4091 58f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadastruct pt3_i2cbuf { 59f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada u8 data[PT3_I2C_MAX]; 60f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada u8 tmp; 61f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada u32 num_cmds; 62f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada}; 63f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 64f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* 65f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * DMA things 66f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada */ 67f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define TS_PACKET_SZ 188 68f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* DMA transfers must not cross 4GiB, so use one page / transfer */ 69f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define DATA_XFER_SZ 4096 70f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define DATA_BUF_XFERS 47 71f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* (num_bufs * DATA_BUF_SZ) % TS_PACKET_SZ must be 0 */ 72f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define DATA_BUF_SZ (DATA_BUF_XFERS * DATA_XFER_SZ) 73f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define MAX_DATA_BUFS 16 74f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define MIN_DATA_BUFS 2 75f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 76f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define DESCS_IN_PAGE (PAGE_SIZE / sizeof(struct xfer_desc)) 77f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define MAX_NUM_XFERS (MAX_DATA_BUFS * DATA_BUF_XFERS) 78f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#define MAX_DESC_BUFS DIV_ROUND_UP(MAX_NUM_XFERS, DESCS_IN_PAGE) 79f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 80f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* DMA transfer description. 81f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * device is passed a pointer to this struct, dma-reads it, 82f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * and gets the DMA buffer ring for storing TS data. 83f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada */ 84f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadastruct xfer_desc { 85f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada u32 addr_l; /* bus address of target data buffer */ 86f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada u32 addr_h; 87f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada u32 size; 88f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada u32 next_l; /* bus adddress of the next xfer_desc */ 89f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada u32 next_h; 90f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada}; 91f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 92f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* A DMA mapping of a page containing xfer_desc's */ 93f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadastruct xfer_desc_buffer { 94f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada dma_addr_t b_addr; 95f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct xfer_desc *descs; /* PAGE_SIZE (xfer_desc[DESCS_IN_PAGE]) */ 96f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada}; 97f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 98f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* A DMA mapping of a data buffer */ 99f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadastruct dma_data_buffer { 100f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada dma_addr_t b_addr; 101f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada u8 *data; /* size: u8[PAGE_SIZE] */ 102f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada}; 103f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 104f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* 105f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * device things 106f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada */ 107f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadastruct pt3_adap_config { 108f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct i2c_board_info demod_info; 109f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct tc90522_config demod_cfg; 110f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 111f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct i2c_board_info tuner_info; 112f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada union tuner_config { 113f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct qm1d1c0042_config qm1d1c0042; 114f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct mxl301rf_config mxl301rf; 115f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada } tuner_cfg; 116f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada u32 init_freq; 117f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada}; 118f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 119f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadastruct pt3_adapter { 120f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct dvb_adapter dvb_adap; /* dvb_adap.priv => struct pt3_board */ 121f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada int adap_idx; 122f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 123f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct dvb_demux demux; 124f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct dmxdev dmxdev; 125f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct dvb_frontend *fe; 126f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct i2c_client *i2c_demod; 127f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct i2c_client *i2c_tuner; 128f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 129f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada /* data fetch thread */ 130f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct task_struct *thread; 131f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada int num_feeds; 132f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 133f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada bool cur_lna; 134f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada bool cur_lnb; /* current LNB power status (on/off) */ 135f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 136f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada /* items below are for DMA */ 137f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct dma_data_buffer buffer[MAX_DATA_BUFS]; 138f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada int buf_idx; 139f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada int buf_ofs; 140f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada int num_bufs; /* == pt3_board->num_bufs */ 141f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada int num_discard; /* how many access units to discard initially */ 142f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 143f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct xfer_desc_buffer desc_buf[MAX_DESC_BUFS]; 144f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada int num_desc_bufs; /* == num_bufs * DATA_BUF_XFERS / DESCS_IN_PAGE */ 145f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada}; 146f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 147f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 148f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadastruct pt3_board { 149f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct pci_dev *pdev; 150f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada void __iomem *regs[2]; 151f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada /* regs[0]: registers, regs[1]: internal memory, used for I2C */ 152f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 153f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct mutex lock; 154f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 155f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada /* LNB power shared among sat-FEs */ 156f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada int lnb_on_cnt; /* LNB power on count */ 157f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 158f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada /* LNA shared among terr-FEs */ 159f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada int lna_on_cnt; /* booster enabled count */ 160f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 161f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada int num_bufs; /* number of DMA buffers allocated/mapped per FE */ 162f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 163f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct i2c_adapter i2c_adap; 164f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct pt3_i2cbuf *i2c_buf; 165f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 166f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct pt3_adapter *adaps[PT3_NUM_FE]; 167f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada}; 168f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 169f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 170f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada/* 171f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada * prototypes 172f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada */ 173f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern int pt3_alloc_dmabuf(struct pt3_adapter *adap); 174f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern void pt3_init_dmabuf(struct pt3_adapter *adap); 175f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern void pt3_free_dmabuf(struct pt3_adapter *adap); 176f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern int pt3_start_dma(struct pt3_adapter *adap); 177f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern int pt3_stop_dma(struct pt3_adapter *adap); 178f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern int pt3_proc_dma(struct pt3_adapter *adap); 179f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada 180f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern int pt3_i2c_master_xfer(struct i2c_adapter *adap, 181f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada struct i2c_msg *msgs, int num); 182f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern u32 pt3_i2c_functionality(struct i2c_adapter *adap); 183f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern void pt3_i2c_reset(struct pt3_board *pt3); 184f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern int pt3_init_all_demods(struct pt3_board *pt3); 185f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukadaextern int pt3_init_all_mxl301rf(struct pt3_board *pt3); 186f5a98f37a535a43b3a27c6a63b07f23d248e4b31Akihiro Tsukada#endif /* PT3_H */ 187