vpss.c revision c38cd8729c90495687ad027a993099d9972ffbf1 
1/*
2 * Copyright (C) 2009 Texas Instruments.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * common vpss system module platform driver for all video drivers.
19 */
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/spinlock.h>
26#include <linux/compiler.h>
27#include <linux/io.h>
28#include <media/davinci/vpss.h>
29
30MODULE_LICENSE("GPL");
31MODULE_DESCRIPTION("VPSS Driver");
32MODULE_AUTHOR("Texas Instruments");
33
34/* DM644x defines */
35#define DM644X_SBL_PCR_VPSS		(4)
36
37#define DM355_VPSSBL_INTSEL		0x10
38#define DM355_VPSSBL_EVTSEL		0x14
39/* vpss BL register offsets */
40#define DM355_VPSSBL_CCDCMUX		0x1c
41/* vpss CLK register offsets */
42#define DM355_VPSSCLK_CLKCTRL		0x04
43/* masks and shifts */
44#define VPSS_HSSISEL_SHIFT		4
45/*
46 * VDINT0 - vpss_int0, VDINT1 - vpss_int1, H3A - vpss_int4,
47 * IPIPE_INT1_SDR - vpss_int5
48 */
49#define DM355_VPSSBL_INTSEL_DEFAULT	0xff83ff10
50/* VENCINT - vpss_int8 */
51#define DM355_VPSSBL_EVTSEL_DEFAULT	0x4
52
53#define DM365_ISP5_PCCR 		0x04
54#define DM365_ISP5_INTSEL1		0x10
55#define DM365_ISP5_INTSEL2		0x14
56#define DM365_ISP5_INTSEL3		0x18
57#define DM365_ISP5_CCDCMUX 		0x20
58#define DM365_ISP5_PG_FRAME_SIZE 	0x28
59#define DM365_VPBE_CLK_CTRL 		0x00
60/*
61 * vpss interrupts. VDINT0 - vpss_int0, VDINT1 - vpss_int1,
62 * AF - vpss_int3
63 */
64#define DM365_ISP5_INTSEL1_DEFAULT	0x0b1f0100
65/* AEW - vpss_int6, RSZ_INT_DMA - vpss_int5 */
66#define DM365_ISP5_INTSEL2_DEFAULT	0x1f0a0f1f
67/* VENC - vpss_int8 */
68#define DM365_ISP5_INTSEL3_DEFAULT	0x00000015
69
70/* masks and shifts for DM365*/
71#define DM365_CCDC_PG_VD_POL_SHIFT 	0
72#define DM365_CCDC_PG_HD_POL_SHIFT 	1
73
74#define CCD_SRC_SEL_MASK		(BIT_MASK(5) | BIT_MASK(4))
75#define CCD_SRC_SEL_SHIFT		4
76
77/* Different SoC platforms supported by this driver */
78enum vpss_platform_type {
79	DM644X,
80	DM355,
81	DM365,
82};
83
84/*
85 * vpss operations. Depends on platform. Not all functions are available
86 * on all platforms. The api, first check if a functio is available before
87 * invoking it. In the probe, the function ptrs are initialized based on
88 * vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc.
89 */
90struct vpss_hw_ops {
91	/* enable clock */
92	int (*enable_clock)(enum vpss_clock_sel clock_sel, int en);
93	/* select input to ccdc */
94	void (*select_ccdc_source)(enum vpss_ccdc_source_sel src_sel);
95	/* clear wbl overflow bit */
96	int (*clear_wbl_overflow)(enum vpss_wbl_sel wbl_sel);
97};
98
99/* vpss configuration */
100struct vpss_oper_config {
101	__iomem void *vpss_regs_base0;
102	__iomem void *vpss_regs_base1;
103	enum vpss_platform_type platform;
104	spinlock_t vpss_lock;
105	struct vpss_hw_ops hw_ops;
106};
107
108static struct vpss_oper_config oper_cfg;
109
110/* register access routines */
111static inline u32 bl_regr(u32 offset)
112{
113	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
114}
115
116static inline void bl_regw(u32 val, u32 offset)
117{
118	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
119}
120
121static inline u32 vpss_regr(u32 offset)
122{
123	return __raw_readl(oper_cfg.vpss_regs_base1 + offset);
124}
125
126static inline void vpss_regw(u32 val, u32 offset)
127{
128	__raw_writel(val, oper_cfg.vpss_regs_base1 + offset);
129}
130
131/* For DM365 only */
132static inline u32 isp5_read(u32 offset)
133{
134	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
135}
136
137/* For DM365 only */
138static inline void isp5_write(u32 val, u32 offset)
139{
140	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
141}
142
143static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
144{
145	u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK;
146
147	/* if we are using pattern generator, enable it */
148	if (src_sel == VPSS_PGLPBK || src_sel == VPSS_CCDCPG)
149		temp |= 0x08;
150
151	temp |= (src_sel << CCD_SRC_SEL_SHIFT);
152	isp5_write(temp, DM365_ISP5_CCDCMUX);
153}
154
155static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
156{
157	bl_regw(src_sel << VPSS_HSSISEL_SHIFT, DM355_VPSSBL_CCDCMUX);
158}
159
160int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
161{
162	if (!oper_cfg.hw_ops.select_ccdc_source)
163		return -EINVAL;
164
165	oper_cfg.hw_ops.select_ccdc_source(src_sel);
166	return 0;
167}
168EXPORT_SYMBOL(vpss_select_ccdc_source);
169
170static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
171{
172	u32 mask = 1, val;
173
174	if (wbl_sel < VPSS_PCR_AEW_WBL_0 ||
175	    wbl_sel > VPSS_PCR_CCDC_WBL_O)
176		return -EINVAL;
177
178	/* writing a 0 clear the overflow */
179	mask = ~(mask << wbl_sel);
180	val = bl_regr(DM644X_SBL_PCR_VPSS) & mask;
181	bl_regw(val, DM644X_SBL_PCR_VPSS);
182	return 0;
183}
184
185int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
186{
187	if (!oper_cfg.hw_ops.clear_wbl_overflow)
188		return -EINVAL;
189
190	return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);
191}
192EXPORT_SYMBOL(vpss_clear_wbl_overflow);
193
194/*
195 *  dm355_enable_clock - Enable VPSS Clock
196 *  @clock_sel: CLock to be enabled/disabled
197 *  @en: enable/disable flag
198 *
199 *  This is called to enable or disable a vpss clock
200 */
201static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en)
202{
203	unsigned long flags;
204	u32 utemp, mask = 0x1, shift = 0;
205
206	switch (clock_sel) {
207	case VPSS_VPBE_CLOCK:
208		/* nothing since lsb */
209		break;
210	case VPSS_VENC_CLOCK_SEL:
211		shift = 2;
212		break;
213	case VPSS_CFALD_CLOCK:
214		shift = 3;
215		break;
216	case VPSS_H3A_CLOCK:
217		shift = 4;
218		break;
219	case VPSS_IPIPE_CLOCK:
220		shift = 5;
221		break;
222	case VPSS_CCDC_CLOCK:
223		shift = 6;
224		break;
225	default:
226		printk(KERN_ERR "dm355_enable_clock:"
227				" Invalid selector: %d\n", clock_sel);
228		return -EINVAL;
229	}
230
231	spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
232	utemp = vpss_regr(DM355_VPSSCLK_CLKCTRL);
233	if (!en)
234		utemp &= ~(mask << shift);
235	else
236		utemp |= (mask << shift);
237
238	vpss_regw(utemp, DM355_VPSSCLK_CLKCTRL);
239	spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
240	return 0;
241}
242
243static int dm365_enable_clock(enum vpss_clock_sel clock_sel, int en)
244{
245	unsigned long flags;
246	u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR;
247	u32 (*read)(u32 offset) = isp5_read;
248	void(*write)(u32 val, u32 offset) = isp5_write;
249
250	switch (clock_sel) {
251	case VPSS_BL_CLOCK:
252		break;
253	case VPSS_CCDC_CLOCK:
254		shift = 1;
255		break;
256	case VPSS_H3A_CLOCK:
257		shift = 2;
258		break;
259	case VPSS_RSZ_CLOCK:
260		shift = 3;
261		break;
262	case VPSS_IPIPE_CLOCK:
263		shift = 4;
264		break;
265	case VPSS_IPIPEIF_CLOCK:
266		shift = 5;
267		break;
268	case VPSS_PCLK_INTERNAL:
269		shift = 6;
270		break;
271	case VPSS_PSYNC_CLOCK_SEL:
272		shift = 7;
273		break;
274	case VPSS_VPBE_CLOCK:
275		read = vpss_regr;
276		write = vpss_regw;
277		offset = DM365_VPBE_CLK_CTRL;
278		break;
279	case VPSS_VENC_CLOCK_SEL:
280		shift = 2;
281		read = vpss_regr;
282		write = vpss_regw;
283		offset = DM365_VPBE_CLK_CTRL;
284		break;
285	case VPSS_LDC_CLOCK:
286		shift = 3;
287		read = vpss_regr;
288		write = vpss_regw;
289		offset = DM365_VPBE_CLK_CTRL;
290		break;
291	case VPSS_FDIF_CLOCK:
292		shift = 4;
293		read = vpss_regr;
294		write = vpss_regw;
295		offset = DM365_VPBE_CLK_CTRL;
296		break;
297	case VPSS_OSD_CLOCK_SEL:
298		shift = 6;
299		read = vpss_regr;
300		write = vpss_regw;
301		offset = DM365_VPBE_CLK_CTRL;
302		break;
303	case VPSS_LDC_CLOCK_SEL:
304		shift = 7;
305		read = vpss_regr;
306		write = vpss_regw;
307		offset = DM365_VPBE_CLK_CTRL;
308		break;
309	default:
310		printk(KERN_ERR "dm365_enable_clock: Invalid selector: %d\n",
311		       clock_sel);
312		return -1;
313	}
314
315	spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
316	utemp = read(offset);
317	if (!en) {
318		mask = ~mask;
319		utemp &= (mask << shift);
320	} else
321		utemp |= (mask << shift);
322
323	write(utemp, offset);
324	spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
325
326	return 0;
327}
328
329int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en)
330{
331	if (!oper_cfg.hw_ops.enable_clock)
332		return -EINVAL;
333
334	return oper_cfg.hw_ops.enable_clock(clock_sel, en);
335}
336EXPORT_SYMBOL(vpss_enable_clock);
337
338void dm365_vpss_set_sync_pol(struct vpss_sync_pol sync)
339{
340	int val = 0;
341	val = isp5_read(DM365_ISP5_CCDCMUX);
342
343	val |= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT);
344	val |= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT);
345
346	isp5_write(val, DM365_ISP5_CCDCMUX);
347}
348EXPORT_SYMBOL(dm365_vpss_set_sync_pol);
349
350void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
351{
352	int current_reg = ((frame_size.hlpfr >> 1) - 1) << 16;
353
354	current_reg |= (frame_size.pplen - 1);
355	isp5_write(current_reg, DM365_ISP5_PG_FRAME_SIZE);
356}
357EXPORT_SYMBOL(dm365_vpss_set_pg_frame_size);
358
359static int vpss_probe(struct platform_device *pdev)
360{
361	struct resource		*r1, *r2;
362	char *platform_name;
363	int status;
364
365	if (!pdev->dev.platform_data) {
366		dev_err(&pdev->dev, "no platform data\n");
367		return -ENOENT;
368	}
369
370	platform_name = pdev->dev.platform_data;
371	if (!strcmp(platform_name, "dm355_vpss"))
372		oper_cfg.platform = DM355;
373	else if (!strcmp(platform_name, "dm365_vpss"))
374		oper_cfg.platform = DM365;
375	else if (!strcmp(platform_name, "dm644x_vpss"))
376		oper_cfg.platform = DM644X;
377	else {
378		dev_err(&pdev->dev, "vpss driver not supported on"
379			" this platform\n");
380		return -ENODEV;
381	}
382
383	dev_info(&pdev->dev, "%s vpss probed\n", platform_name);
384	r1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
385	if (!r1)
386		return -ENOENT;
387
388	r1 = request_mem_region(r1->start, resource_size(r1), r1->name);
389	if (!r1)
390		return -EBUSY;
391
392	oper_cfg.vpss_regs_base0 = ioremap(r1->start, resource_size(r1));
393	if (!oper_cfg.vpss_regs_base0) {
394		status = -EBUSY;
395		goto fail1;
396	}
397
398	if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
399		r2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
400		if (!r2) {
401			status = -ENOENT;
402			goto fail2;
403		}
404		r2 = request_mem_region(r2->start, resource_size(r2), r2->name);
405		if (!r2) {
406			status = -EBUSY;
407			goto fail2;
408		}
409
410		oper_cfg.vpss_regs_base1 = ioremap(r2->start,
411						   resource_size(r2));
412		if (!oper_cfg.vpss_regs_base1) {
413			status = -EBUSY;
414			goto fail3;
415		}
416	}
417
418	if (oper_cfg.platform == DM355) {
419		oper_cfg.hw_ops.enable_clock = dm355_enable_clock;
420		oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;
421		/* Setup vpss interrupts */
422		bl_regw(DM355_VPSSBL_INTSEL_DEFAULT, DM355_VPSSBL_INTSEL);
423		bl_regw(DM355_VPSSBL_EVTSEL_DEFAULT, DM355_VPSSBL_EVTSEL);
424	} else if (oper_cfg.platform == DM365) {
425		oper_cfg.hw_ops.enable_clock = dm365_enable_clock;
426		oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;
427		/* Setup vpss interrupts */
428		isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1);
429		isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2);
430		isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3);
431	} else
432		oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;
433
434	spin_lock_init(&oper_cfg.vpss_lock);
435	dev_info(&pdev->dev, "%s vpss probe success\n", platform_name);
436	return 0;
437
438fail3:
439	release_mem_region(r2->start, resource_size(r2));
440fail2:
441	iounmap(oper_cfg.vpss_regs_base0);
442fail1:
443	release_mem_region(r1->start, resource_size(r1));
444	return status;
445}
446
447static int vpss_remove(struct platform_device *pdev)
448{
449	struct resource		*res;
450
451	iounmap(oper_cfg.vpss_regs_base0);
452	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
453	release_mem_region(res->start, resource_size(res));
454	if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
455		iounmap(oper_cfg.vpss_regs_base1);
456		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
457		release_mem_region(res->start, resource_size(res));
458	}
459	return 0;
460}
461
462static struct platform_driver vpss_driver = {
463	.driver = {
464		.name	= "vpss",
465		.owner = THIS_MODULE,
466	},
467	.remove = vpss_remove,
468	.probe = vpss_probe,
469};
470
471static void vpss_exit(void)
472{
473	platform_driver_unregister(&vpss_driver);
474}
475
476static int __init vpss_init(void)
477{
478	return platform_driver_register(&vpss_driver);
479}
480subsys_initcall(vpss_init);
481module_exit(vpss_exit);
482