fimc-is-param.c revision 03385b8e9d7a9f361c178ea33fa76b39793f85b2
1/* 2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * 6 * Authors: Younghwan Joo <yhwan.joo@samsung.com> 7 * Sylwester Nawrocki <s.nawrocki@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__ 14 15#include <linux/bitops.h> 16#include <linux/bug.h> 17#include <linux/device.h> 18#include <linux/errno.h> 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/platform_device.h> 22#include <linux/slab.h> 23#include <linux/types.h> 24#include <linux/videodev2.h> 25 26#include <media/v4l2-device.h> 27#include <media/v4l2-ioctl.h> 28 29#include "fimc-is.h" 30#include "fimc-is-command.h" 31#include "fimc-is-errno.h" 32#include "fimc-is-param.h" 33#include "fimc-is-regs.h" 34#include "fimc-is-sensor.h" 35 36static void __hw_param_copy(void *dst, void *src) 37{ 38 memcpy(dst, src, FIMC_IS_PARAM_MAX_SIZE); 39} 40 41void __fimc_is_hw_update_param_global_shotmode(struct fimc_is *is) 42{ 43 struct param_global_shotmode *dst, *src; 44 45 dst = &is->is_p_region->parameter.global.shotmode; 46 src = &is->config[is->config_index].global.shotmode; 47 __hw_param_copy(dst, src); 48} 49 50void __fimc_is_hw_update_param_sensor_framerate(struct fimc_is *is) 51{ 52 struct param_sensor_framerate *dst, *src; 53 54 dst = &is->is_p_region->parameter.sensor.frame_rate; 55 src = &is->config[is->config_index].sensor.frame_rate; 56 __hw_param_copy(dst, src); 57} 58 59int __fimc_is_hw_update_param(struct fimc_is *is, u32 offset) 60{ 61 struct is_param_region *par = &is->is_p_region->parameter; 62 struct chain_config *cfg = &is->config[is->config_index]; 63 64 switch (offset) { 65 case PARAM_ISP_CONTROL: 66 __hw_param_copy(&par->isp.control, &cfg->isp.control); 67 break; 68 69 case PARAM_ISP_OTF_INPUT: 70 __hw_param_copy(&par->isp.otf_input, &cfg->isp.otf_input); 71 break; 72 73 case PARAM_ISP_DMA1_INPUT: 74 __hw_param_copy(&par->isp.dma1_input, &cfg->isp.dma1_input); 75 break; 76 77 case PARAM_ISP_DMA2_INPUT: 78 __hw_param_copy(&par->isp.dma2_input, &cfg->isp.dma2_input); 79 break; 80 81 case PARAM_ISP_AA: 82 __hw_param_copy(&par->isp.aa, &cfg->isp.aa); 83 break; 84 85 case PARAM_ISP_FLASH: 86 __hw_param_copy(&par->isp.flash, &cfg->isp.flash); 87 break; 88 89 case PARAM_ISP_AWB: 90 __hw_param_copy(&par->isp.awb, &cfg->isp.awb); 91 break; 92 93 case PARAM_ISP_IMAGE_EFFECT: 94 __hw_param_copy(&par->isp.effect, &cfg->isp.effect); 95 break; 96 97 case PARAM_ISP_ISO: 98 __hw_param_copy(&par->isp.iso, &cfg->isp.iso); 99 break; 100 101 case PARAM_ISP_ADJUST: 102 __hw_param_copy(&par->isp.adjust, &cfg->isp.adjust); 103 break; 104 105 case PARAM_ISP_METERING: 106 __hw_param_copy(&par->isp.metering, &cfg->isp.metering); 107 break; 108 109 case PARAM_ISP_AFC: 110 __hw_param_copy(&par->isp.afc, &cfg->isp.afc); 111 break; 112 113 case PARAM_ISP_OTF_OUTPUT: 114 __hw_param_copy(&par->isp.otf_output, &cfg->isp.otf_output); 115 break; 116 117 case PARAM_ISP_DMA1_OUTPUT: 118 __hw_param_copy(&par->isp.dma1_output, &cfg->isp.dma1_output); 119 break; 120 121 case PARAM_ISP_DMA2_OUTPUT: 122 __hw_param_copy(&par->isp.dma2_output, &cfg->isp.dma2_output); 123 break; 124 125 case PARAM_DRC_CONTROL: 126 __hw_param_copy(&par->drc.control, &cfg->drc.control); 127 break; 128 129 case PARAM_DRC_OTF_INPUT: 130 __hw_param_copy(&par->drc.otf_input, &cfg->drc.otf_input); 131 break; 132 133 case PARAM_DRC_DMA_INPUT: 134 __hw_param_copy(&par->drc.dma_input, &cfg->drc.dma_input); 135 break; 136 137 case PARAM_DRC_OTF_OUTPUT: 138 __hw_param_copy(&par->drc.otf_output, &cfg->drc.otf_output); 139 break; 140 141 case PARAM_FD_CONTROL: 142 __hw_param_copy(&par->fd.control, &cfg->fd.control); 143 break; 144 145 case PARAM_FD_OTF_INPUT: 146 __hw_param_copy(&par->fd.otf_input, &cfg->fd.otf_input); 147 break; 148 149 case PARAM_FD_DMA_INPUT: 150 __hw_param_copy(&par->fd.dma_input, &cfg->fd.dma_input); 151 break; 152 153 case PARAM_FD_CONFIG: 154 __hw_param_copy(&par->fd.config, &cfg->fd.config); 155 break; 156 157 default: 158 return -EINVAL; 159 } 160 161 return 0; 162} 163 164unsigned int __get_pending_param_count(struct fimc_is *is) 165{ 166 struct chain_config *config = &is->config[is->config_index]; 167 unsigned long flags; 168 unsigned int count; 169 170 spin_lock_irqsave(&is->slock, flags); 171 count = hweight32(config->p_region_index1); 172 count += hweight32(config->p_region_index2); 173 spin_unlock_irqrestore(&is->slock, flags); 174 175 return count; 176} 177 178int __is_hw_update_params(struct fimc_is *is) 179{ 180 unsigned long *p_index1, *p_index2; 181 int i, id, ret = 0; 182 183 id = is->config_index; 184 p_index1 = &is->config[id].p_region_index1; 185 p_index2 = &is->config[id].p_region_index2; 186 187 if (test_bit(PARAM_GLOBAL_SHOTMODE, p_index1)) 188 __fimc_is_hw_update_param_global_shotmode(is); 189 190 if (test_bit(PARAM_SENSOR_FRAME_RATE, p_index1)) 191 __fimc_is_hw_update_param_sensor_framerate(is); 192 193 for (i = PARAM_ISP_CONTROL; i < PARAM_DRC_CONTROL; i++) { 194 if (test_bit(i, p_index1)) 195 ret = __fimc_is_hw_update_param(is, i); 196 } 197 198 for (i = PARAM_DRC_CONTROL; i < PARAM_SCALERC_CONTROL; i++) { 199 if (test_bit(i, p_index1)) 200 ret = __fimc_is_hw_update_param(is, i); 201 } 202 203 for (i = PARAM_FD_CONTROL; i <= PARAM_FD_CONFIG; i++) { 204 if (test_bit((i - 32), p_index2)) 205 ret = __fimc_is_hw_update_param(is, i); 206 } 207 208 return ret; 209} 210 211void __is_get_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf) 212{ 213 struct isp_param *isp; 214 215 isp = &is->config[is->config_index].isp; 216 mf->width = isp->otf_input.width; 217 mf->height = isp->otf_input.height; 218} 219 220void __is_set_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf) 221{ 222 unsigned int index = is->config_index; 223 struct isp_param *isp; 224 struct drc_param *drc; 225 struct fd_param *fd; 226 227 isp = &is->config[index].isp; 228 drc = &is->config[index].drc; 229 fd = &is->config[index].fd; 230 231 /* Update isp size info (OTF only) */ 232 isp->otf_input.width = mf->width; 233 isp->otf_input.height = mf->height; 234 isp->otf_output.width = mf->width; 235 isp->otf_output.height = mf->height; 236 /* Update drc size info (OTF only) */ 237 drc->otf_input.width = mf->width; 238 drc->otf_input.height = mf->height; 239 drc->otf_output.width = mf->width; 240 drc->otf_output.height = mf->height; 241 /* Update fd size info (OTF only) */ 242 fd->otf_input.width = mf->width; 243 fd->otf_input.height = mf->height; 244 245 if (test_bit(PARAM_ISP_OTF_INPUT, 246 &is->config[index].p_region_index1)) 247 return; 248 249 /* Update field */ 250 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT); 251 fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT); 252 fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT); 253 fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT); 254 fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT); 255} 256 257int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is) 258{ 259 switch (is->sensor->drvdata->id) { 260 case FIMC_IS_SENSOR_ID_S5K6A3: 261 return 30; 262 default: 263 return 15; 264 } 265} 266 267void __is_set_sensor(struct fimc_is *is, int fps) 268{ 269 unsigned int index = is->config_index; 270 struct sensor_param *sensor; 271 struct isp_param *isp; 272 273 sensor = &is->config[index].sensor; 274 isp = &is->config[index].isp; 275 276 if (fps == 0) { 277 sensor->frame_rate.frame_rate = 278 fimc_is_hw_get_sensor_max_framerate(is); 279 isp->otf_input.frametime_min = 0; 280 isp->otf_input.frametime_max = 66666; 281 } else { 282 sensor->frame_rate.frame_rate = fps; 283 isp->otf_input.frametime_min = 0; 284 isp->otf_input.frametime_max = (u32)1000000 / fps; 285 } 286 287 fimc_is_set_param_bit(is, PARAM_SENSOR_FRAME_RATE); 288 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT); 289} 290 291void __is_set_init_isp_aa(struct fimc_is *is) 292{ 293 struct isp_param *isp; 294 295 isp = &is->config[is->config_index].isp; 296 297 isp->aa.cmd = ISP_AA_COMMAND_START; 298 isp->aa.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE | 299 ISP_AA_TARGET_AWB; 300 isp->aa.mode = 0; 301 isp->aa.scene = 0; 302 isp->aa.sleep = 0; 303 isp->aa.face = 0; 304 isp->aa.touch_x = 0; 305 isp->aa.touch_y = 0; 306 isp->aa.manual_af_setting = 0; 307 isp->aa.err = ISP_AF_ERROR_NONE; 308 309 fimc_is_set_param_bit(is, PARAM_ISP_AA); 310} 311 312void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye) 313{ 314 unsigned int index = is->config_index; 315 struct isp_param *isp = &is->config[index].isp; 316 317 isp->flash.cmd = cmd; 318 isp->flash.redeye = redeye; 319 isp->flash.err = ISP_FLASH_ERROR_NONE; 320 321 fimc_is_set_param_bit(is, PARAM_ISP_FLASH); 322} 323 324void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val) 325{ 326 unsigned int index = is->config_index; 327 struct isp_param *isp; 328 329 isp = &is->config[index].isp; 330 331 isp->awb.cmd = cmd; 332 isp->awb.illumination = val; 333 isp->awb.err = ISP_AWB_ERROR_NONE; 334 335 fimc_is_set_param_bit(is, PARAM_ISP_AWB); 336} 337 338void __is_set_isp_effect(struct fimc_is *is, u32 cmd) 339{ 340 unsigned int index = is->config_index; 341 struct isp_param *isp; 342 343 isp = &is->config[index].isp; 344 345 isp->effect.cmd = cmd; 346 isp->effect.err = ISP_IMAGE_EFFECT_ERROR_NONE; 347 348 fimc_is_set_param_bit(is, PARAM_ISP_IMAGE_EFFECT); 349} 350 351void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val) 352{ 353 unsigned int index = is->config_index; 354 struct isp_param *isp; 355 356 isp = &is->config[index].isp; 357 358 isp->iso.cmd = cmd; 359 isp->iso.value = val; 360 isp->iso.err = ISP_ISO_ERROR_NONE; 361 362 fimc_is_set_param_bit(is, PARAM_ISP_ISO); 363} 364 365void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val) 366{ 367 unsigned int index = is->config_index; 368 unsigned long *p_index; 369 struct isp_param *isp; 370 371 p_index = &is->config[index].p_region_index1; 372 isp = &is->config[index].isp; 373 374 switch (cmd) { 375 case ISP_ADJUST_COMMAND_MANUAL_CONTRAST: 376 isp->adjust.contrast = val; 377 break; 378 case ISP_ADJUST_COMMAND_MANUAL_SATURATION: 379 isp->adjust.saturation = val; 380 break; 381 case ISP_ADJUST_COMMAND_MANUAL_SHARPNESS: 382 isp->adjust.sharpness = val; 383 break; 384 case ISP_ADJUST_COMMAND_MANUAL_EXPOSURE: 385 isp->adjust.exposure = val; 386 break; 387 case ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS: 388 isp->adjust.brightness = val; 389 break; 390 case ISP_ADJUST_COMMAND_MANUAL_HUE: 391 isp->adjust.hue = val; 392 break; 393 case ISP_ADJUST_COMMAND_AUTO: 394 isp->adjust.contrast = 0; 395 isp->adjust.saturation = 0; 396 isp->adjust.sharpness = 0; 397 isp->adjust.exposure = 0; 398 isp->adjust.brightness = 0; 399 isp->adjust.hue = 0; 400 break; 401 } 402 403 if (!test_bit(PARAM_ISP_ADJUST, p_index)) { 404 isp->adjust.cmd = cmd; 405 isp->adjust.err = ISP_ADJUST_ERROR_NONE; 406 fimc_is_set_param_bit(is, PARAM_ISP_ADJUST); 407 } else { 408 isp->adjust.cmd |= cmd; 409 } 410} 411 412void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val) 413{ 414 unsigned int index = is->config_index; 415 struct isp_param *isp; 416 unsigned long *p_index; 417 418 p_index = &is->config[index].p_region_index1; 419 isp = &is->config[index].isp; 420 421 switch (id) { 422 case IS_METERING_CONFIG_CMD: 423 isp->metering.cmd = val; 424 break; 425 case IS_METERING_CONFIG_WIN_POS_X: 426 isp->metering.win_pos_x = val; 427 break; 428 case IS_METERING_CONFIG_WIN_POS_Y: 429 isp->metering.win_pos_y = val; 430 break; 431 case IS_METERING_CONFIG_WIN_WIDTH: 432 isp->metering.win_width = val; 433 break; 434 case IS_METERING_CONFIG_WIN_HEIGHT: 435 isp->metering.win_height = val; 436 break; 437 default: 438 return; 439 } 440 441 if (!test_bit(PARAM_ISP_METERING, p_index)) { 442 isp->metering.err = ISP_METERING_ERROR_NONE; 443 fimc_is_set_param_bit(is, PARAM_ISP_METERING); 444 } 445} 446 447void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val) 448{ 449 unsigned int index = is->config_index; 450 struct isp_param *isp; 451 452 isp = &is->config[index].isp; 453 454 isp->afc.cmd = cmd; 455 isp->afc.manual = val; 456 isp->afc.err = ISP_AFC_ERROR_NONE; 457 458 fimc_is_set_param_bit(is, PARAM_ISP_AFC); 459} 460 461void __is_set_drc_control(struct fimc_is *is, u32 val) 462{ 463 unsigned int index = is->config_index; 464 struct drc_param *drc; 465 466 drc = &is->config[index].drc; 467 468 drc->control.bypass = val; 469 470 fimc_is_set_param_bit(is, PARAM_DRC_CONTROL); 471} 472 473void __is_set_fd_control(struct fimc_is *is, u32 val) 474{ 475 unsigned int index = is->config_index; 476 struct fd_param *fd; 477 unsigned long *p_index; 478 479 p_index = &is->config[index].p_region_index2; 480 fd = &is->config[index].fd; 481 482 fd->control.cmd = val; 483 484 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) 485 fimc_is_set_param_bit(is, PARAM_FD_CONTROL); 486} 487 488void __is_set_fd_config_maxface(struct fimc_is *is, u32 val) 489{ 490 unsigned int index = is->config_index; 491 struct fd_param *fd; 492 unsigned long *p_index; 493 494 p_index = &is->config[index].p_region_index2; 495 fd = &is->config[index].fd; 496 497 fd->config.max_number = val; 498 499 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) { 500 fd->config.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER; 501 fd->config.err = ERROR_FD_NONE; 502 fimc_is_set_param_bit(is, PARAM_FD_CONFIG); 503 } else { 504 fd->config.cmd |= FD_CONFIG_COMMAND_MAXIMUM_NUMBER; 505 } 506} 507 508void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val) 509{ 510 unsigned int index = is->config_index; 511 struct fd_param *fd; 512 unsigned long *p_index; 513 514 p_index = &is->config[index].p_region_index2; 515 fd = &is->config[index].fd; 516 517 fd->config.roll_angle = val; 518 519 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) { 520 fd->config.cmd = FD_CONFIG_COMMAND_ROLL_ANGLE; 521 fd->config.err = ERROR_FD_NONE; 522 fimc_is_set_param_bit(is, PARAM_FD_CONFIG); 523 } else { 524 fd->config.cmd |= FD_CONFIG_COMMAND_ROLL_ANGLE; 525 } 526} 527 528void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val) 529{ 530 unsigned int index = is->config_index; 531 struct fd_param *fd; 532 unsigned long *p_index; 533 534 p_index = &is->config[index].p_region_index2; 535 fd = &is->config[index].fd; 536 537 fd->config.yaw_angle = val; 538 539 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) { 540 fd->config.cmd = FD_CONFIG_COMMAND_YAW_ANGLE; 541 fd->config.err = ERROR_FD_NONE; 542 fimc_is_set_param_bit(is, PARAM_FD_CONFIG); 543 } else { 544 fd->config.cmd |= FD_CONFIG_COMMAND_YAW_ANGLE; 545 } 546} 547 548void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val) 549{ 550 unsigned int index = is->config_index; 551 struct fd_param *fd; 552 unsigned long *p_index; 553 554 p_index = &is->config[index].p_region_index2; 555 fd = &is->config[index].fd; 556 557 fd->config.smile_mode = val; 558 559 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) { 560 fd->config.cmd = FD_CONFIG_COMMAND_SMILE_MODE; 561 fd->config.err = ERROR_FD_NONE; 562 fimc_is_set_param_bit(is, PARAM_FD_CONFIG); 563 } else { 564 fd->config.cmd |= FD_CONFIG_COMMAND_SMILE_MODE; 565 } 566} 567 568void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val) 569{ 570 unsigned int index = is->config_index; 571 struct fd_param *fd; 572 unsigned long *p_index; 573 574 p_index = &is->config[index].p_region_index2; 575 fd = &is->config[index].fd; 576 577 fd->config.blink_mode = val; 578 579 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) { 580 fd->config.cmd = FD_CONFIG_COMMAND_BLINK_MODE; 581 fd->config.err = ERROR_FD_NONE; 582 fimc_is_set_param_bit(is, PARAM_FD_CONFIG); 583 } else { 584 fd->config.cmd |= FD_CONFIG_COMMAND_BLINK_MODE; 585 } 586} 587 588void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val) 589{ 590 unsigned int index = is->config_index; 591 struct fd_param *fd; 592 unsigned long *p_index; 593 594 p_index = &is->config[index].p_region_index2; 595 fd = &is->config[index].fd; 596 597 fd->config.eye_detect = val; 598 599 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) { 600 fd->config.cmd = FD_CONFIG_COMMAND_EYES_DETECT; 601 fd->config.err = ERROR_FD_NONE; 602 fimc_is_set_param_bit(is, PARAM_FD_CONFIG); 603 } else { 604 fd->config.cmd |= FD_CONFIG_COMMAND_EYES_DETECT; 605 } 606} 607 608void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val) 609{ 610 unsigned int index = is->config_index; 611 struct fd_param *fd; 612 unsigned long *p_index; 613 614 p_index = &is->config[index].p_region_index2; 615 fd = &is->config[index].fd; 616 617 fd->config.mouth_detect = val; 618 619 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) { 620 fd->config.cmd = FD_CONFIG_COMMAND_MOUTH_DETECT; 621 fd->config.err = ERROR_FD_NONE; 622 fimc_is_set_param_bit(is, PARAM_FD_CONFIG); 623 } else { 624 fd->config.cmd |= FD_CONFIG_COMMAND_MOUTH_DETECT; 625 } 626} 627 628void __is_set_fd_config_orientation(struct fimc_is *is, u32 val) 629{ 630 unsigned int index = is->config_index; 631 struct fd_param *fd; 632 unsigned long *p_index; 633 634 p_index = &is->config[index].p_region_index2; 635 fd = &is->config[index].fd; 636 637 fd->config.orientation = val; 638 639 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) { 640 fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION; 641 fd->config.err = ERROR_FD_NONE; 642 fimc_is_set_param_bit(is, PARAM_FD_CONFIG); 643 } else { 644 fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION; 645 } 646} 647 648void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val) 649{ 650 unsigned int index = is->config_index; 651 struct fd_param *fd; 652 unsigned long *p_index; 653 654 p_index = &is->config[index].p_region_index2; 655 fd = &is->config[index].fd; 656 657 fd->config.orientation_value = val; 658 659 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) { 660 fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION_VALUE; 661 fd->config.err = ERROR_FD_NONE; 662 fimc_is_set_param_bit(is, PARAM_FD_CONFIG); 663 } else { 664 fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION_VALUE; 665 } 666} 667 668void fimc_is_set_initial_params(struct fimc_is *is) 669{ 670 struct global_param *global; 671 struct sensor_param *sensor; 672 struct isp_param *isp; 673 struct drc_param *drc; 674 struct fd_param *fd; 675 unsigned long *p_index1, *p_index2; 676 unsigned int index; 677 678 index = is->config_index; 679 global = &is->config[index].global; 680 sensor = &is->config[index].sensor; 681 isp = &is->config[index].isp; 682 drc = &is->config[index].drc; 683 fd = &is->config[index].fd; 684 p_index1 = &is->config[index].p_region_index1; 685 p_index2 = &is->config[index].p_region_index2; 686 687 /* Global */ 688 global->shotmode.cmd = 1; 689 fimc_is_set_param_bit(is, PARAM_GLOBAL_SHOTMODE); 690 691 /* ISP */ 692 isp->control.cmd = CONTROL_COMMAND_START; 693 isp->control.bypass = CONTROL_BYPASS_DISABLE; 694 isp->control.err = CONTROL_ERROR_NONE; 695 fimc_is_set_param_bit(is, PARAM_ISP_CONTROL); 696 697 isp->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE; 698 if (!test_bit(PARAM_ISP_OTF_INPUT, p_index1)) { 699 isp->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH; 700 isp->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT; 701 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT); 702 } 703 if (is->sensor->test_pattern) 704 isp->otf_input.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER; 705 else 706 isp->otf_input.format = OTF_INPUT_FORMAT_BAYER; 707 isp->otf_input.bitwidth = 10; 708 isp->otf_input.order = OTF_INPUT_ORDER_BAYER_GR_BG; 709 isp->otf_input.crop_offset_x = 0; 710 isp->otf_input.crop_offset_y = 0; 711 isp->otf_input.err = OTF_INPUT_ERROR_NONE; 712 713 isp->dma1_input.cmd = DMA_INPUT_COMMAND_DISABLE; 714 isp->dma1_input.width = 0; 715 isp->dma1_input.height = 0; 716 isp->dma1_input.format = 0; 717 isp->dma1_input.bitwidth = 0; 718 isp->dma1_input.plane = 0; 719 isp->dma1_input.order = 0; 720 isp->dma1_input.buffer_number = 0; 721 isp->dma1_input.width = 0; 722 isp->dma1_input.err = DMA_INPUT_ERROR_NONE; 723 fimc_is_set_param_bit(is, PARAM_ISP_DMA1_INPUT); 724 725 isp->dma2_input.cmd = DMA_INPUT_COMMAND_DISABLE; 726 isp->dma2_input.width = 0; 727 isp->dma2_input.height = 0; 728 isp->dma2_input.format = 0; 729 isp->dma2_input.bitwidth = 0; 730 isp->dma2_input.plane = 0; 731 isp->dma2_input.order = 0; 732 isp->dma2_input.buffer_number = 0; 733 isp->dma2_input.width = 0; 734 isp->dma2_input.err = DMA_INPUT_ERROR_NONE; 735 fimc_is_set_param_bit(is, PARAM_ISP_DMA2_INPUT); 736 737 isp->aa.cmd = ISP_AA_COMMAND_START; 738 isp->aa.target = ISP_AA_TARGET_AE | ISP_AA_TARGET_AWB; 739 fimc_is_set_param_bit(is, PARAM_ISP_AA); 740 741 if (!test_bit(PARAM_ISP_FLASH, p_index1)) 742 __is_set_isp_flash(is, ISP_FLASH_COMMAND_DISABLE, 743 ISP_FLASH_REDEYE_DISABLE); 744 745 if (!test_bit(PARAM_ISP_AWB, p_index1)) 746 __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0); 747 748 if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index1)) 749 __is_set_isp_effect(is, ISP_IMAGE_EFFECT_DISABLE); 750 751 if (!test_bit(PARAM_ISP_ISO, p_index1)) 752 __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0); 753 754 if (!test_bit(PARAM_ISP_ADJUST, p_index1)) { 755 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST, 0); 756 __is_set_isp_adjust(is, 757 ISP_ADJUST_COMMAND_MANUAL_SATURATION, 0); 758 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS, 0); 759 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE, 0); 760 __is_set_isp_adjust(is, 761 ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS, 0); 762 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE, 0); 763 } 764 765 if (!test_bit(PARAM_ISP_METERING, p_index1)) { 766 __is_set_isp_metering(is, 0, ISP_METERING_COMMAND_CENTER); 767 __is_set_isp_metering(is, 1, 0); 768 __is_set_isp_metering(is, 2, 0); 769 __is_set_isp_metering(is, 3, 0); 770 __is_set_isp_metering(is, 4, 0); 771 } 772 773 if (!test_bit(PARAM_ISP_AFC, p_index1)) 774 __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0); 775 776 isp->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE; 777 if (!test_bit(PARAM_ISP_OTF_OUTPUT, p_index1)) { 778 isp->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH; 779 isp->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT; 780 fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT); 781 } 782 isp->otf_output.format = OTF_OUTPUT_FORMAT_YUV444; 783 isp->otf_output.bitwidth = 12; 784 isp->otf_output.order = 0; 785 isp->otf_output.err = OTF_OUTPUT_ERROR_NONE; 786 787 if (!test_bit(PARAM_ISP_DMA1_OUTPUT, p_index1)) { 788 isp->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE; 789 isp->dma1_output.width = 0; 790 isp->dma1_output.height = 0; 791 isp->dma1_output.format = 0; 792 isp->dma1_output.bitwidth = 0; 793 isp->dma1_output.plane = 0; 794 isp->dma1_output.order = 0; 795 isp->dma1_output.buffer_number = 0; 796 isp->dma1_output.buffer_address = 0; 797 isp->dma1_output.notify_dma_done = 0; 798 isp->dma1_output.dma_out_mask = 0; 799 isp->dma1_output.err = DMA_OUTPUT_ERROR_NONE; 800 fimc_is_set_param_bit(is, PARAM_ISP_DMA1_OUTPUT); 801 } 802 803 if (!test_bit(PARAM_ISP_DMA2_OUTPUT, p_index1)) { 804 isp->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE; 805 isp->dma2_output.width = 0; 806 isp->dma2_output.height = 0; 807 isp->dma2_output.format = 0; 808 isp->dma2_output.bitwidth = 0; 809 isp->dma2_output.plane = 0; 810 isp->dma2_output.order = 0; 811 isp->dma2_output.buffer_number = 0; 812 isp->dma2_output.buffer_address = 0; 813 isp->dma2_output.notify_dma_done = 0; 814 isp->dma2_output.dma_out_mask = 0; 815 isp->dma2_output.err = DMA_OUTPUT_ERROR_NONE; 816 fimc_is_set_param_bit(is, PARAM_ISP_DMA2_OUTPUT); 817 } 818 819 /* Sensor */ 820 if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index1)) { 821 if (is->config_index == 0) 822 __is_set_sensor(is, 0); 823 } 824 825 /* DRC */ 826 drc->control.cmd = CONTROL_COMMAND_START; 827 __is_set_drc_control(is, CONTROL_BYPASS_ENABLE); 828 829 drc->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE; 830 if (!test_bit(PARAM_DRC_OTF_INPUT, p_index1)) { 831 drc->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH; 832 drc->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT; 833 fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT); 834 } 835 drc->otf_input.format = OTF_INPUT_FORMAT_YUV444; 836 drc->otf_input.bitwidth = 12; 837 drc->otf_input.order = 0; 838 drc->otf_input.err = OTF_INPUT_ERROR_NONE; 839 840 drc->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE; 841 drc->dma_input.width = 0; 842 drc->dma_input.height = 0; 843 drc->dma_input.format = 0; 844 drc->dma_input.bitwidth = 0; 845 drc->dma_input.plane = 0; 846 drc->dma_input.order = 0; 847 drc->dma_input.buffer_number = 0; 848 drc->dma_input.width = 0; 849 drc->dma_input.err = DMA_INPUT_ERROR_NONE; 850 fimc_is_set_param_bit(is, PARAM_DRC_DMA_INPUT); 851 852 drc->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE; 853 if (!test_bit(PARAM_DRC_OTF_OUTPUT, p_index1)) { 854 drc->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH; 855 drc->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT; 856 fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT); 857 } 858 drc->otf_output.format = OTF_OUTPUT_FORMAT_YUV444; 859 drc->otf_output.bitwidth = 8; 860 drc->otf_output.order = 0; 861 drc->otf_output.err = OTF_OUTPUT_ERROR_NONE; 862 863 /* FD */ 864 __is_set_fd_control(is, CONTROL_COMMAND_STOP); 865 fd->control.bypass = CONTROL_BYPASS_DISABLE; 866 867 fd->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE; 868 if (!test_bit((PARAM_FD_OTF_INPUT - 32), p_index2)) { 869 fd->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH; 870 fd->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT; 871 fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT); 872 } 873 874 fd->otf_input.format = OTF_INPUT_FORMAT_YUV444; 875 fd->otf_input.bitwidth = 8; 876 fd->otf_input.order = 0; 877 fd->otf_input.err = OTF_INPUT_ERROR_NONE; 878 879 fd->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE; 880 fd->dma_input.width = 0; 881 fd->dma_input.height = 0; 882 fd->dma_input.format = 0; 883 fd->dma_input.bitwidth = 0; 884 fd->dma_input.plane = 0; 885 fd->dma_input.order = 0; 886 fd->dma_input.buffer_number = 0; 887 fd->dma_input.width = 0; 888 fd->dma_input.err = DMA_INPUT_ERROR_NONE; 889 fimc_is_set_param_bit(is, PARAM_FD_DMA_INPUT); 890 891 __is_set_fd_config_maxface(is, 5); 892 __is_set_fd_config_rollangle(is, FD_CONFIG_ROLL_ANGLE_FULL); 893 __is_set_fd_config_yawangle(is, FD_CONFIG_YAW_ANGLE_45_90); 894 __is_set_fd_config_smilemode(is, FD_CONFIG_SMILE_MODE_DISABLE); 895 __is_set_fd_config_blinkmode(is, FD_CONFIG_BLINK_MODE_DISABLE); 896 __is_set_fd_config_eyedetect(is, FD_CONFIG_EYES_DETECT_ENABLE); 897 __is_set_fd_config_mouthdetect(is, FD_CONFIG_MOUTH_DETECT_DISABLE); 898 __is_set_fd_config_orientation(is, FD_CONFIG_ORIENTATION_DISABLE); 899 __is_set_fd_config_orientation_val(is, 0); 900} 901