fimc-is.h revision 9a761e436843f228eaa2decda6d2c6dbd5ef1480 
1/*
2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * Authors: Younghwan Joo <yhwan.joo@samsung.com>
7 *          Sylwester Nawrocki <s.nawrocki@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef FIMC_IS_H_
14#define FIMC_IS_H_
15
16#include <asm/barrier.h>
17#include <linux/clk.h>
18#include <linux/device.h>
19#include <linux/kernel.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/platform_device.h>
22#include <linux/sizes.h>
23#include <linux/spinlock.h>
24#include <linux/types.h>
25#include <media/videobuf2-core.h>
26#include <media/v4l2-ctrls.h>
27
28#include "fimc-isp.h"
29#include "fimc-is-command.h"
30#include "fimc-is-sensor.h"
31#include "fimc-is-param.h"
32#include "fimc-is-regs.h"
33
34#define FIMC_IS_DRV_NAME		"exynos4-fimc-is"
35
36#define FIMC_IS_FW_FILENAME		"fimc_is_fw.bin"
37#define FIMC_IS_SETFILE_6A3		"setfile.bin"
38
39#define FIMC_IS_FW_LOAD_TIMEOUT		1000 /* ms */
40#define FIMC_IS_POWER_ON_TIMEOUT	1000 /* us */
41
42#define FIMC_IS_SENSOR_NUM		2
43
44/* Memory definitions */
45#define FIMC_IS_CPU_MEM_SIZE		(0xa00000)
46#define FIMC_IS_CPU_BASE_MASK		((1 << 26) - 1)
47#define FIMC_IS_REGION_SIZE		0x5000
48
49#define FIMC_IS_DEBUG_REGION_OFFSET	0x0084b000
50#define FIMC_IS_SHARED_REGION_OFFSET	0x008c0000
51#define FIMC_IS_FW_INFO_LEN		31
52#define FIMC_IS_FW_VER_LEN		7
53#define FIMC_IS_FW_DESC_LEN		(FIMC_IS_FW_INFO_LEN + \
54					 FIMC_IS_FW_VER_LEN)
55#define FIMC_IS_SETFILE_INFO_LEN	39
56
57#define FIMC_IS_EXTRA_MEM_SIZE		(FIMC_IS_EXTRA_FW_SIZE + \
58					 FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000)
59#define FIMC_IS_EXTRA_FW_SIZE		0x180000
60#define FIMC_IS_EXTRA_SETFILE_SIZE	0x4b000
61
62/* TODO: revisit */
63#define FIMC_IS_FW_ADDR_MASK		((1 << 26) - 1)
64#define FIMC_IS_FW_SIZE_MAX		(SZ_4M)
65#define FIMC_IS_FW_SIZE_MIN		(SZ_32K)
66
67#define ATCLK_MCUISP_FREQUENCY		100000000UL
68#define ACLK_AXI_FREQUENCY		100000000UL
69
70enum {
71	ISS_CLK_PPMUISPX,
72	ISS_CLK_PPMUISPMX,
73	ISS_CLK_LITE0,
74	ISS_CLK_LITE1,
75	ISS_CLK_MPLL,
76	ISS_CLK_SYSREG,
77	ISS_CLK_ISP,
78	ISS_CLK_DRC,
79	ISS_CLK_FD,
80	ISS_CLK_MCUISP,
81	ISS_CLK_UART,
82	ISS_GATE_CLKS_MAX,
83	ISS_CLK_ISP_DIV0 = ISS_GATE_CLKS_MAX,
84	ISS_CLK_ISP_DIV1,
85	ISS_CLK_MCUISP_DIV0,
86	ISS_CLK_MCUISP_DIV1,
87	ISS_CLK_ACLK200,
88	ISS_CLK_ACLK200_DIV,
89	ISS_CLK_ACLK400MCUISP,
90	ISS_CLK_ACLK400MCUISP_DIV,
91	ISS_CLKS_MAX
92};
93
94/* The driver's internal state flags */
95enum {
96	IS_ST_IDLE,
97	IS_ST_PWR_ON,
98	IS_ST_A5_PWR_ON,
99	IS_ST_FW_LOADED,
100	IS_ST_OPEN_SENSOR,
101	IS_ST_SETFILE_LOADED,
102	IS_ST_INIT_DONE,
103	IS_ST_STREAM_ON,
104	IS_ST_STREAM_OFF,
105	IS_ST_CHANGE_MODE,
106	IS_ST_BLOCK_CMD_CLEARED,
107	IS_ST_SET_ZOOM,
108	IS_ST_PWR_SUBIP_ON,
109	IS_ST_END,
110};
111
112enum af_state {
113	FIMC_IS_AF_IDLE		= 0,
114	FIMC_IS_AF_SETCONFIG	= 1,
115	FIMC_IS_AF_RUNNING	= 2,
116	FIMC_IS_AF_LOCK		= 3,
117	FIMC_IS_AF_ABORT	= 4,
118	FIMC_IS_AF_FAILED	= 5,
119};
120
121enum af_lock_state {
122	FIMC_IS_AF_UNLOCKED	= 0,
123	FIMC_IS_AF_LOCKED	= 2
124};
125
126enum ae_lock_state {
127	FIMC_IS_AE_UNLOCKED	= 0,
128	FIMC_IS_AE_LOCKED	= 1
129};
130
131enum awb_lock_state {
132	FIMC_IS_AWB_UNLOCKED	= 0,
133	FIMC_IS_AWB_LOCKED	= 1
134};
135
136enum {
137	IS_METERING_CONFIG_CMD,
138	IS_METERING_CONFIG_WIN_POS_X,
139	IS_METERING_CONFIG_WIN_POS_Y,
140	IS_METERING_CONFIG_WIN_WIDTH,
141	IS_METERING_CONFIG_WIN_HEIGHT,
142	IS_METERING_CONFIG_MAX
143};
144
145struct is_setfile {
146	const struct firmware *info;
147	int state;
148	u32 sub_index;
149	u32 base;
150	size_t size;
151};
152
153struct is_fd_result_header {
154	u32 offset;
155	u32 count;
156	u32 index;
157	u32 curr_index;
158	u32 width;
159	u32 height;
160};
161
162struct is_af_info {
163	u16 mode;
164	u32 af_state;
165	u32 af_lock_state;
166	u32 ae_lock_state;
167	u32 awb_lock_state;
168	u16 pos_x;
169	u16 pos_y;
170	u16 prev_pos_x;
171	u16 prev_pos_y;
172	u16 use_af;
173};
174
175struct fimc_is_firmware {
176	const struct firmware *f_w;
177
178	dma_addr_t paddr;
179	void *vaddr;
180	unsigned int size;
181
182	char info[FIMC_IS_FW_INFO_LEN + 1];
183	char version[FIMC_IS_FW_VER_LEN + 1];
184	char setfile_info[FIMC_IS_SETFILE_INFO_LEN + 1];
185	u8 state;
186};
187
188struct fimc_is_memory {
189	/* physical base address */
190	dma_addr_t paddr;
191	/* virtual base address */
192	void *vaddr;
193	/* total length */
194	unsigned int size;
195};
196
197#define FIMC_IS_I2H_MAX_ARGS	12
198
199struct i2h_cmd {
200	u32 cmd;
201	u32 sensor_id;
202	u16 num_args;
203	u32 args[FIMC_IS_I2H_MAX_ARGS];
204};
205
206struct h2i_cmd {
207	u16 cmd_type;
208	u32 entry_id;
209};
210
211#define FIMC_IS_DEBUG_MSG	0x3f
212#define FIMC_IS_DEBUG_LEVEL	3
213
214struct fimc_is_setfile {
215	const struct firmware *info;
216	unsigned int state;
217	unsigned int size;
218	u32 sub_index;
219	u32 base;
220};
221
222struct is_config_param {
223	struct global_param	global;
224	struct sensor_param	sensor;
225	struct isp_param	isp;
226	struct drc_param	drc;
227	struct fd_param		fd;
228
229	atomic_t		p_region_num;
230	unsigned long		p_region_index1;
231	unsigned long		p_region_index2;
232};
233
234/**
235 * struct fimc_is - fimc-is data structure
236 * @pdev: pointer to FIMC-IS platform device
237 * @pctrl: pointer to pinctrl structure for this device
238 * @v4l2_dev: pointer to top the level v4l2_device
239 * @alloc_ctx: videobuf2 memory allocator context
240 * @lock: mutex serializing video device and the subdev operations
241 * @slock: spinlock protecting this data structure and the hw registers
242 * @clocks: FIMC-LITE gate clock
243 * @regs: MCUCTL mmapped registers region
244 * @pmu_regs: PMU ISP mmapped registers region
245 * @irq_queue: interrupt handling waitqueue
246 * @lpm: low power mode flag
247 * @state: internal driver's state flags
248 */
249struct fimc_is {
250	struct platform_device		*pdev;
251	struct pinctrl			*pctrl;
252	struct v4l2_device		*v4l2_dev;
253
254	struct fimc_is_firmware		fw;
255	struct fimc_is_memory		memory;
256	struct firmware			*f_w;
257
258	struct fimc_isp			isp;
259	struct fimc_is_sensor		*sensor;
260	struct fimc_is_setfile		setfile;
261
262	struct vb2_alloc_ctx		*alloc_ctx;
263	struct v4l2_ctrl_handler	ctrl_handler;
264
265	struct mutex			lock;
266	spinlock_t			slock;
267
268	struct clk			*clocks[ISS_CLKS_MAX];
269	bool				clk_init;
270	void __iomem			*regs;
271	void __iomem			*pmu_regs;
272	int				irq;
273	wait_queue_head_t		irq_queue;
274	u8				lpm;
275
276	unsigned long			state;
277	unsigned int			sensor_index;
278
279	struct i2h_cmd			i2h_cmd;
280	struct h2i_cmd			h2i_cmd;
281	struct is_fd_result_header	fd_header;
282
283	struct is_config_param		cfg_param[IS_SC_MAX];
284	struct is_region		*is_p_region;
285	dma_addr_t			is_dma_p_region;
286	struct is_share_region		*is_shared_region;
287	struct is_af_info		af;
288	u32				scenario_id;
289
290	struct dentry			*debugfs_entry;
291};
292
293static inline struct fimc_is *fimc_isp_to_is(struct fimc_isp *isp)
294{
295	return container_of(isp, struct fimc_is, isp);
296}
297
298static inline void fimc_is_mem_barrier(void)
299{
300	mb();
301}
302
303static inline void fimc_is_set_param_bit(struct fimc_is *is, int num)
304{
305	struct is_config_param *cfg = &is->cfg_param[is->scenario_id];
306
307	if (num >= 32)
308		set_bit(num - 32, &cfg->p_region_index2);
309	else
310		set_bit(num, &cfg->p_region_index1);
311}
312
313static inline void fimc_is_set_param_ctrl_cmd(struct fimc_is *is, int cmd)
314{
315	is->is_p_region->parameter.isp.control.cmd = cmd;
316}
317
318static inline void mcuctl_write(u32 v, struct fimc_is *is, unsigned int offset)
319{
320	writel(v, is->regs + offset);
321}
322
323static inline u32 mcuctl_read(struct fimc_is *is, unsigned int offset)
324{
325	return readl(is->regs + offset);
326}
327
328static inline void pmuisp_write(u32 v, struct fimc_is *is, unsigned int offset)
329{
330	writel(v, is->pmu_regs + offset);
331}
332
333static inline u32 pmuisp_read(struct fimc_is *is, unsigned int offset)
334{
335	return readl(is->pmu_regs + offset);
336}
337
338int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
339		       unsigned int state, unsigned int timeout);
340int fimc_is_cpu_set_power(struct fimc_is *is, int on);
341int fimc_is_start_firmware(struct fimc_is *is);
342int fimc_is_hw_initialize(struct fimc_is *is);
343void fimc_is_log_dump(const char *level, const void *buf, size_t len);
344
345#endif /* FIMC_IS_H_ */
346