mcam-core.h revision 4e032f3f58800a998bae79150909410d7a37206f 
1/*
2 * Marvell camera core structures.
3 *
4 * Copyright 2011 Jonathan Corbet corbet@lwn.net
5 */
6#ifndef _MCAM_CORE_H
7#define _MCAM_CORE_H
8
9#include <linux/list.h>
10#include <media/v4l2-common.h>
11#include <media/v4l2-ctrls.h>
12#include <media/v4l2-dev.h>
13#include <media/videobuf2-core.h>
14
15/*
16 * Create our own symbols for the supported buffer modes, but, for now,
17 * base them entirely on which videobuf2 options have been selected.
18 */
19#if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC)
20#define MCAM_MODE_VMALLOC 1
21#endif
22
23#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG)
24#define MCAM_MODE_DMA_CONTIG 1
25#endif
26
27#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG)
28#define MCAM_MODE_DMA_SG 1
29#endif
30
31#if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \
32	!defined(MCAM_MODE_DMA_SG)
33#error One of the videobuf buffer modes must be selected in the config
34#endif
35
36
37enum mcam_state {
38	S_NOTREADY,	/* Not yet initialized */
39	S_IDLE,		/* Just hanging around */
40	S_FLAKED,	/* Some sort of problem */
41	S_STREAMING,	/* Streaming data */
42	S_BUFWAIT	/* streaming requested but no buffers yet */
43};
44#define MAX_DMA_BUFS 3
45
46/*
47 * Different platforms work best with different buffer modes, so we
48 * let the platform pick.
49 */
50enum mcam_buffer_mode {
51	B_vmalloc = 0,
52	B_DMA_contig = 1,
53	B_DMA_sg = 2
54};
55
56enum mcam_chip_id {
57	MCAM_CAFE,
58	MCAM_ARMADA610,
59};
60
61/*
62 * Is a given buffer mode supported by the current kernel configuration?
63 */
64static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode)
65{
66	switch (mode) {
67#ifdef MCAM_MODE_VMALLOC
68	case B_vmalloc:
69#endif
70#ifdef MCAM_MODE_DMA_CONTIG
71	case B_DMA_contig:
72#endif
73#ifdef MCAM_MODE_DMA_SG
74	case B_DMA_sg:
75#endif
76		return 1;
77	default:
78		return 0;
79	}
80}
81
82/*
83 * Basic frame states
84 */
85struct mcam_frame_state {
86	unsigned int frames;
87	unsigned int singles;
88	unsigned int delivered;
89};
90
91/*
92 * A description of one of our devices.
93 * Locking: controlled by s_mutex.  Certain fields, however, require
94 *          the dev_lock spinlock; they are marked as such by comments.
95 *          dev_lock is also required for access to device registers.
96 */
97struct mcam_camera {
98	/*
99	 * These fields should be set by the platform code prior to
100	 * calling mcam_register().
101	 */
102	struct i2c_adapter *i2c_adapter;
103	unsigned char __iomem *regs;
104	unsigned regs_size; /* size in bytes of the register space */
105	spinlock_t dev_lock;
106	struct device *dev; /* For messages, dma alloc */
107	enum mcam_chip_id chip_id;
108	short int clock_speed;	/* Sensor clock speed, default 30 */
109	short int use_smbus;	/* SMBUS or straight I2c? */
110	enum mcam_buffer_mode buffer_mode;
111	/*
112	 * Callbacks from the core to the platform code.
113	 */
114	void (*plat_power_up) (struct mcam_camera *cam);
115	void (*plat_power_down) (struct mcam_camera *cam);
116
117	/*
118	 * Everything below here is private to the mcam core and
119	 * should not be touched by the platform code.
120	 */
121	struct v4l2_device v4l2_dev;
122	struct v4l2_ctrl_handler ctrl_handler;
123	enum mcam_state state;
124	unsigned long flags;		/* Buffer status, mainly (dev_lock) */
125	int users;			/* How many open FDs */
126
127	struct mcam_frame_state frame_state;	/* Frame state counter */
128	/*
129	 * Subsystem structures.
130	 */
131	struct video_device vdev;
132	struct v4l2_subdev *sensor;
133	unsigned short sensor_addr;
134
135	/* Videobuf2 stuff */
136	struct vb2_queue vb_queue;
137	struct list_head buffers;	/* Available frames */
138
139	unsigned int nbufs;		/* How many are alloc'd */
140	int next_buf;			/* Next to consume (dev_lock) */
141
142	/* DMA buffers - vmalloc mode */
143#ifdef MCAM_MODE_VMALLOC
144	unsigned int dma_buf_size;	/* allocated size */
145	void *dma_bufs[MAX_DMA_BUFS];	/* Internal buffer addresses */
146	dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
147	struct tasklet_struct s_tasklet;
148#endif
149	unsigned int sequence;		/* Frame sequence number */
150	unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual bufs */
151
152	/* DMA buffers - DMA modes */
153	struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS];
154	struct vb2_alloc_ctx *vb_alloc_ctx;
155
156	/* Mode-specific ops, set at open time */
157	void (*dma_setup)(struct mcam_camera *cam);
158	void (*frame_complete)(struct mcam_camera *cam, int frame);
159
160	/* Current operating parameters */
161	struct v4l2_pix_format pix_format;
162	enum v4l2_mbus_pixelcode mbus_code;
163
164	/* Locks */
165	struct mutex s_mutex; /* Access to this structure */
166};
167
168
169/*
170 * Register I/O functions.  These are here because the platform code
171 * may legitimately need to mess with the register space.
172 */
173/*
174 * Device register I/O
175 */
176static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg,
177		unsigned int val)
178{
179	iowrite32(val, cam->regs + reg);
180}
181
182static inline unsigned int mcam_reg_read(struct mcam_camera *cam,
183		unsigned int reg)
184{
185	return ioread32(cam->regs + reg);
186}
187
188
189static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg,
190		unsigned int val, unsigned int mask)
191{
192	unsigned int v = mcam_reg_read(cam, reg);
193
194	v = (v & ~mask) | (val & mask);
195	mcam_reg_write(cam, reg, v);
196}
197
198static inline void mcam_reg_clear_bit(struct mcam_camera *cam,
199		unsigned int reg, unsigned int val)
200{
201	mcam_reg_write_mask(cam, reg, 0, val);
202}
203
204static inline void mcam_reg_set_bit(struct mcam_camera *cam,
205		unsigned int reg, unsigned int val)
206{
207	mcam_reg_write_mask(cam, reg, val, val);
208}
209
210/*
211 * Functions for use by platform code.
212 */
213int mccic_register(struct mcam_camera *cam);
214int mccic_irq(struct mcam_camera *cam, unsigned int irqs);
215void mccic_shutdown(struct mcam_camera *cam);
216#ifdef CONFIG_PM
217void mccic_suspend(struct mcam_camera *cam);
218int mccic_resume(struct mcam_camera *cam);
219#endif
220
221/*
222 * Register definitions for the m88alp01 camera interface.  Offsets in bytes
223 * as given in the spec.
224 */
225#define REG_Y0BAR	0x00
226#define REG_Y1BAR	0x04
227#define REG_Y2BAR	0x08
228/* ... */
229
230#define REG_IMGPITCH	0x24	/* Image pitch register */
231#define   IMGP_YP_SHFT	  2		/* Y pitch params */
232#define   IMGP_YP_MASK	  0x00003ffc	/* Y pitch field */
233#define	  IMGP_UVP_SHFT	  18		/* UV pitch (planar) */
234#define   IMGP_UVP_MASK   0x3ffc0000
235#define REG_IRQSTATRAW	0x28	/* RAW IRQ Status */
236#define   IRQ_EOF0	  0x00000001	/* End of frame 0 */
237#define   IRQ_EOF1	  0x00000002	/* End of frame 1 */
238#define   IRQ_EOF2	  0x00000004	/* End of frame 2 */
239#define   IRQ_SOF0	  0x00000008	/* Start of frame 0 */
240#define   IRQ_SOF1	  0x00000010	/* Start of frame 1 */
241#define   IRQ_SOF2	  0x00000020	/* Start of frame 2 */
242#define   IRQ_OVERFLOW	  0x00000040	/* FIFO overflow */
243#define   IRQ_TWSIW	  0x00010000	/* TWSI (smbus) write */
244#define   IRQ_TWSIR	  0x00020000	/* TWSI read */
245#define   IRQ_TWSIE	  0x00040000	/* TWSI error */
246#define   TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
247#define   FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
248#define   ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
249#define REG_IRQMASK	0x2c	/* IRQ mask - same bits as IRQSTAT */
250#define REG_IRQSTAT	0x30	/* IRQ status / clear */
251
252#define REG_IMGSIZE	0x34	/* Image size */
253#define  IMGSZ_V_MASK	  0x1fff0000
254#define  IMGSZ_V_SHIFT	  16
255#define	 IMGSZ_H_MASK	  0x00003fff
256#define REG_IMGOFFSET	0x38	/* IMage offset */
257
258#define REG_CTRL0	0x3c	/* Control 0 */
259#define   C0_ENABLE	  0x00000001	/* Makes the whole thing go */
260
261/* Mask for all the format bits */
262#define   C0_DF_MASK	  0x00fffffc    /* Bits 2-23 */
263
264/* RGB ordering */
265#define	  C0_RGB4_RGBX	  0x00000000
266#define	  C0_RGB4_XRGB	  0x00000004
267#define	  C0_RGB4_BGRX	  0x00000008
268#define	  C0_RGB4_XBGR	  0x0000000c
269#define	  C0_RGB5_RGGB	  0x00000000
270#define	  C0_RGB5_GRBG	  0x00000004
271#define	  C0_RGB5_GBRG	  0x00000008
272#define	  C0_RGB5_BGGR	  0x0000000c
273
274/* Spec has two fields for DIN and DOUT, but they must match, so
275   combine them here. */
276#define	  C0_DF_YUV	  0x00000000	/* Data is YUV	    */
277#define	  C0_DF_RGB	  0x000000a0	/* ... RGB		    */
278#define	  C0_DF_BAYER	  0x00000140	/* ... Bayer		    */
279/* 8-8-8 must be missing from the below - ask */
280#define	  C0_RGBF_565	  0x00000000
281#define	  C0_RGBF_444	  0x00000800
282#define	  C0_RGB_BGR	  0x00001000	/* Blue comes first */
283#define	  C0_YUV_PLANAR	  0x00000000	/* YUV 422 planar format */
284#define	  C0_YUV_PACKED	  0x00008000	/* YUV 422 packed	*/
285#define	  C0_YUV_420PL	  0x0000a000	/* YUV 420 planar	*/
286/* Think that 420 packed must be 111 - ask */
287#define	  C0_YUVE_YUYV	  0x00000000	/* Y1CbY0Cr		*/
288#define	  C0_YUVE_YVYU	  0x00010000	/* Y1CrY0Cb		*/
289#define	  C0_YUVE_VYUY	  0x00020000	/* CrY1CbY0		*/
290#define	  C0_YUVE_UYVY	  0x00030000	/* CbY1CrY0		*/
291#define	  C0_YUVE_XYUV	  0x00000000	/* 420: .YUV		*/
292#define	  C0_YUVE_XYVU	  0x00010000	/* 420: .YVU		*/
293#define	  C0_YUVE_XUVY	  0x00020000	/* 420: .UVY		*/
294#define	  C0_YUVE_XVUY	  0x00030000	/* 420: .VUY		*/
295/* Bayer bits 18,19 if needed */
296#define	  C0_HPOL_LOW	  0x01000000	/* HSYNC polarity active low */
297#define	  C0_VPOL_LOW	  0x02000000	/* VSYNC polarity active low */
298#define	  C0_VCLK_LOW	  0x04000000	/* VCLK on falling edge */
299#define	  C0_DOWNSCALE	  0x08000000	/* Enable downscaler */
300#define	  C0_SIFM_MASK	  0xc0000000	/* SIF mode bits */
301#define	  C0_SIF_HVSYNC	  0x00000000	/* Use H/VSYNC */
302#define	  CO_SOF_NOSYNC	  0x40000000	/* Use inband active signaling */
303
304/* Bits below C1_444ALPHA are not present in Cafe */
305#define REG_CTRL1	0x40	/* Control 1 */
306#define	  C1_CLKGATE	  0x00000001	/* Sensor clock gate */
307#define   C1_DESC_ENA	  0x00000100	/* DMA descriptor enable */
308#define   C1_DESC_3WORD   0x00000200	/* Three-word descriptors used */
309#define	  C1_444ALPHA	  0x00f00000	/* Alpha field in RGB444 */
310#define	  C1_ALPHA_SHFT	  20
311#define	  C1_DMAB32	  0x00000000	/* 32-byte DMA burst */
312#define	  C1_DMAB16	  0x02000000	/* 16-byte DMA burst */
313#define	  C1_DMAB64	  0x04000000	/* 64-byte DMA burst */
314#define	  C1_DMAB_MASK	  0x06000000
315#define	  C1_TWOBUFS	  0x08000000	/* Use only two DMA buffers */
316#define	  C1_PWRDWN	  0x10000000	/* Power down */
317
318#define REG_CLKCTRL	0x88	/* Clock control */
319#define	  CLK_DIV_MASK	  0x0000ffff	/* Upper bits RW "reserved" */
320
321/* This appears to be a Cafe-only register */
322#define REG_UBAR	0xc4	/* Upper base address register */
323
324/* Armada 610 DMA descriptor registers */
325#define	REG_DMA_DESC_Y	0x200
326#define	REG_DMA_DESC_U	0x204
327#define	REG_DMA_DESC_V	0x208
328#define REG_DESC_LEN_Y	0x20c	/* Lengths are in bytes */
329#define	REG_DESC_LEN_U	0x210
330#define REG_DESC_LEN_V	0x214
331
332/*
333 * Useful stuff that probably belongs somewhere global.
334 */
335#define VGA_WIDTH	640
336#define VGA_HEIGHT	480
337
338#endif /* _MCAM_CORE_H */
339