regs-mfc-v8.h revision e2b9deb2ad34c9ca6e11a6193bf29088716c2b62 
1/*
2 * Register definition file for Samsung MFC V8.x Interface (FIMV) driver
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 *		http://www.samsung.com/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _REGS_MFC_V8_H
13#define _REGS_MFC_V8_H
14
15#include <linux/sizes.h>
16#include "regs-mfc-v7.h"
17
18/* Additional registers for v8 */
19#define S5P_FIMV_D_MVC_NUM_VIEWS_V8		0xf104
20#define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8	0xf144
21#define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8	0xf148
22#define S5P_FIMV_D_MV_BUFFER_SIZE_V8		0xf150
23
24#define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8	0xf138
25#define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8	0xf13c
26
27#define S5P_FIMV_D_FIRST_PLANE_DPB_V8		0xf160
28#define S5P_FIMV_D_SECOND_PLANE_DPB_V8		0xf260
29#define S5P_FIMV_D_MV_BUFFER_V8			0xf460
30
31#define S5P_FIMV_D_NUM_MV_V8			0xf134
32#define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8	0xf154
33
34#define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8	0xf560
35#define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8	0xf564
36
37#define S5P_FIMV_D_CPB_BUFFER_ADDR_V8		0xf5b0
38#define S5P_FIMV_D_CPB_BUFFER_SIZE_V8		0xf5b4
39#define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8	0xf5bc
40#define S5P_FIMV_D_CPB_BUFFER_OFFSET_V8		0xf5c0
41#define S5P_FIMV_D_SLICE_IF_ENABLE_V8		0xf5c4
42#define S5P_FIMV_D_STREAM_DATA_SIZE_V8		0xf5d0
43
44/* Display information register */
45#define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8	0xf600
46#define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8	0xf604
47
48/* Display status */
49#define S5P_FIMV_D_DISPLAY_STATUS_V8		0xf608
50
51#define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8	0xf60c
52#define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8	0xf610
53
54#define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8	0xf618
55#define S5P_FIMV_D_DISPLAY_CROP_INFO1_V8	0xf61c
56#define S5P_FIMV_D_DISPLAY_CROP_INFO2_V8	0xf620
57#define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V8	0xf624
58
59/* Decoded picture information register */
60#define S5P_FIMV_D_DECODED_STATUS_V8		0xf644
61#define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8	0xf648
62#define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8	0xf64c
63#define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR_V8	0xf650
64#define S5P_FIMV_D_DECODED_FRAME_TYPE_V8	0xf654
65#define S5P_FIMV_D_DECODED_NAL_SIZE_V8          0xf664
66
67/* Returned value register for specific setting */
68#define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8	0xf674
69#define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8	0xf678
70#define S5P_FIMV_D_MVC_VIEW_ID_V8		0xf6d8
71
72/* SEI related information */
73#define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8	0xf6dc
74
75/* MFCv8 Context buffer sizes */
76#define MFC_CTX_BUF_SIZE_V8		(30 * SZ_1K)	/*  30KB */
77#define MFC_H264_DEC_CTX_BUF_SIZE_V8	(2 * SZ_1M)	/*  2MB */
78#define MFC_OTHER_DEC_CTX_BUF_SIZE_V8	(20 * SZ_1K)	/*  20KB */
79
80/* Buffer size defines */
81#define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h)	(((w) * 704) + 2176)
82#define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \
83		(((w) * 576 + (h) * 128)  + 4128)
84
85/* BUffer alignment defines */
86#define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8	64
87
88/* MFCv8 variant defines */
89#define MAX_FW_SIZE_V8			(SZ_1M)		/* 1MB */
90#define MAX_CPB_SIZE_V8			(3 * SZ_1M)	/* 3MB */
91#define MFC_VERSION_V8			0x80
92#define MFC_NUM_PORTS_V8		1
93
94#endif /*_REGS_MFC_V8_H*/
95