s5p_mfc.c revision 1957f0d71c5a6dc8c6f2435ec477ec777d080603
1/* 2 * Samsung S5P Multi Format Codec v 5.1 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Kamil Debski, <k.debski@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22#include <media/v4l2-event.h> 23#include <linux/workqueue.h> 24#include <linux/of.h> 25#include <media/videobuf2-core.h> 26#include "s5p_mfc_common.h" 27#include "s5p_mfc_ctrl.h" 28#include "s5p_mfc_debug.h" 29#include "s5p_mfc_dec.h" 30#include "s5p_mfc_enc.h" 31#include "s5p_mfc_intr.h" 32#include "s5p_mfc_opr.h" 33#include "s5p_mfc_cmd.h" 34#include "s5p_mfc_pm.h" 35 36#define S5P_MFC_NAME "s5p-mfc" 37#define S5P_MFC_DEC_NAME "s5p-mfc-dec" 38#define S5P_MFC_ENC_NAME "s5p-mfc-enc" 39 40int debug; 41module_param(debug, int, S_IRUGO | S_IWUSR); 42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); 43 44/* Helper functions for interrupt processing */ 45 46/* Remove from hw execution round robin */ 47void clear_work_bit(struct s5p_mfc_ctx *ctx) 48{ 49 struct s5p_mfc_dev *dev = ctx->dev; 50 51 spin_lock(&dev->condlock); 52 __clear_bit(ctx->num, &dev->ctx_work_bits); 53 spin_unlock(&dev->condlock); 54} 55 56/* Add to hw execution round robin */ 57void set_work_bit(struct s5p_mfc_ctx *ctx) 58{ 59 struct s5p_mfc_dev *dev = ctx->dev; 60 61 spin_lock(&dev->condlock); 62 __set_bit(ctx->num, &dev->ctx_work_bits); 63 spin_unlock(&dev->condlock); 64} 65 66/* Remove from hw execution round robin */ 67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 68{ 69 struct s5p_mfc_dev *dev = ctx->dev; 70 unsigned long flags; 71 72 spin_lock_irqsave(&dev->condlock, flags); 73 __clear_bit(ctx->num, &dev->ctx_work_bits); 74 spin_unlock_irqrestore(&dev->condlock, flags); 75} 76 77/* Add to hw execution round robin */ 78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 79{ 80 struct s5p_mfc_dev *dev = ctx->dev; 81 unsigned long flags; 82 83 spin_lock_irqsave(&dev->condlock, flags); 84 __set_bit(ctx->num, &dev->ctx_work_bits); 85 spin_unlock_irqrestore(&dev->condlock, flags); 86} 87 88/* Wake up context wait_queue */ 89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, 90 unsigned int err) 91{ 92 ctx->int_cond = 1; 93 ctx->int_type = reason; 94 ctx->int_err = err; 95 wake_up(&ctx->queue); 96} 97 98/* Wake up device wait_queue */ 99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, 100 unsigned int err) 101{ 102 dev->int_cond = 1; 103 dev->int_type = reason; 104 dev->int_err = err; 105 wake_up(&dev->queue); 106} 107 108static void s5p_mfc_watchdog(unsigned long arg) 109{ 110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; 111 112 if (test_bit(0, &dev->hw_lock)) 113 atomic_inc(&dev->watchdog_cnt); 114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { 115 /* This means that hw is busy and no interrupts were 116 * generated by hw for the Nth time of running this 117 * watchdog timer. This usually means a serious hw 118 * error. Now it is time to kill all instances and 119 * reset the MFC. */ 120 mfc_err("Time out during waiting for HW\n"); 121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work); 122 } 123 dev->watchdog_timer.expires = jiffies + 124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 125 add_timer(&dev->watchdog_timer); 126} 127 128static void s5p_mfc_watchdog_worker(struct work_struct *work) 129{ 130 struct s5p_mfc_dev *dev; 131 struct s5p_mfc_ctx *ctx; 132 unsigned long flags; 133 int mutex_locked; 134 int i, ret; 135 136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work); 137 138 mfc_err("Driver timeout error handling\n"); 139 /* Lock the mutex that protects open and release. 140 * This is necessary as they may load and unload firmware. */ 141 mutex_locked = mutex_trylock(&dev->mfc_mutex); 142 if (!mutex_locked) 143 mfc_err("Error: some instance may be closing/opening\n"); 144 spin_lock_irqsave(&dev->irqlock, flags); 145 146 s5p_mfc_clock_off(); 147 148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) { 149 ctx = dev->ctx[i]; 150 if (!ctx) 151 continue; 152 ctx->state = MFCINST_ERROR; 153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 154 &ctx->vq_dst); 155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 156 &ctx->vq_src); 157 clear_work_bit(ctx); 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); 159 } 160 clear_bit(0, &dev->hw_lock); 161 spin_unlock_irqrestore(&dev->irqlock, flags); 162 /* Double check if there is at least one instance running. 163 * If no instance is in memory than no firmware should be present */ 164 if (dev->num_inst > 0) { 165 ret = s5p_mfc_reload_firmware(dev); 166 if (ret) { 167 mfc_err("Failed to reload FW\n"); 168 goto unlock; 169 } 170 s5p_mfc_clock_on(); 171 ret = s5p_mfc_init_hw(dev); 172 if (ret) 173 mfc_err("Failed to reinit FW\n"); 174 } 175unlock: 176 if (mutex_locked) 177 mutex_unlock(&dev->mfc_mutex); 178} 179 180static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file) 181{ 182 struct video_device *vdev = video_devdata(file); 183 184 if (!vdev) { 185 mfc_err("failed to get video_device"); 186 return MFCNODE_INVALID; 187 } 188 if (vdev->index == 0) 189 return MFCNODE_DECODER; 190 else if (vdev->index == 1) 191 return MFCNODE_ENCODER; 192 return MFCNODE_INVALID; 193} 194 195static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) 196{ 197 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 198 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 199 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 200} 201 202static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) 203{ 204 struct s5p_mfc_buf *dst_buf; 205 struct s5p_mfc_dev *dev = ctx->dev; 206 207 ctx->state = MFCINST_FINISHED; 208 ctx->sequence++; 209 while (!list_empty(&ctx->dst_queue)) { 210 dst_buf = list_entry(ctx->dst_queue.next, 211 struct s5p_mfc_buf, list); 212 mfc_debug(2, "Cleaning up buffer: %d\n", 213 dst_buf->b->v4l2_buf.index); 214 vb2_set_plane_payload(dst_buf->b, 0, 0); 215 vb2_set_plane_payload(dst_buf->b, 1, 0); 216 list_del(&dst_buf->list); 217 ctx->dst_queue_cnt--; 218 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); 219 220 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == 221 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) 222 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 223 else 224 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; 225 226 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); 227 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); 228 } 229} 230 231static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) 232{ 233 struct s5p_mfc_dev *dev = ctx->dev; 234 struct s5p_mfc_buf *dst_buf, *src_buf; 235 size_t dec_y_addr; 236 unsigned int frame_type; 237 238 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); 239 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 240 241 /* Copy timestamp / timecode from decoded src to dst and set 242 appropraite flags */ 243 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 244 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 245 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { 246 dst_buf->b->v4l2_buf.timecode = 247 src_buf->b->v4l2_buf.timecode; 248 dst_buf->b->v4l2_buf.timestamp = 249 src_buf->b->v4l2_buf.timestamp; 250 switch (frame_type) { 251 case S5P_FIMV_DECODE_FRAME_I_FRAME: 252 dst_buf->b->v4l2_buf.flags |= 253 V4L2_BUF_FLAG_KEYFRAME; 254 break; 255 case S5P_FIMV_DECODE_FRAME_P_FRAME: 256 dst_buf->b->v4l2_buf.flags |= 257 V4L2_BUF_FLAG_PFRAME; 258 break; 259 case S5P_FIMV_DECODE_FRAME_B_FRAME: 260 dst_buf->b->v4l2_buf.flags |= 261 V4L2_BUF_FLAG_BFRAME; 262 break; 263 } 264 break; 265 } 266 } 267} 268 269static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) 270{ 271 struct s5p_mfc_dev *dev = ctx->dev; 272 struct s5p_mfc_buf *dst_buf; 273 size_t dspl_y_addr; 274 unsigned int frame_type; 275 276 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); 277 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx); 278 279 /* If frame is same as previous then skip and do not dequeue */ 280 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { 281 if (!ctx->after_packed_pb) 282 ctx->sequence++; 283 ctx->after_packed_pb = 0; 284 return; 285 } 286 ctx->sequence++; 287 /* The MFC returns address of the buffer, now we have to 288 * check which videobuf does it correspond to */ 289 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 290 /* Check if this is the buffer we're looking for */ 291 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { 292 list_del(&dst_buf->list); 293 ctx->dst_queue_cnt--; 294 dst_buf->b->v4l2_buf.sequence = ctx->sequence; 295 if (s5p_mfc_hw_call(dev->mfc_ops, 296 get_pic_type_top, ctx) == 297 s5p_mfc_hw_call(dev->mfc_ops, 298 get_pic_type_bot, ctx)) 299 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 300 else 301 dst_buf->b->v4l2_buf.field = 302 V4L2_FIELD_INTERLACED; 303 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); 304 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); 305 clear_bit(dst_buf->b->v4l2_buf.index, 306 &ctx->dec_dst_flag); 307 308 vb2_buffer_done(dst_buf->b, 309 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 310 311 break; 312 } 313 } 314} 315 316/* Handle frame decoding interrupt */ 317static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, 318 unsigned int reason, unsigned int err) 319{ 320 struct s5p_mfc_dev *dev = ctx->dev; 321 unsigned int dst_frame_status; 322 struct s5p_mfc_buf *src_buf; 323 unsigned long flags; 324 unsigned int res_change; 325 326 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 327 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 328 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 329 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) 330 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; 331 mfc_debug(2, "Frame Status: %x\n", dst_frame_status); 332 if (ctx->state == MFCINST_RES_CHANGE_INIT) 333 ctx->state = MFCINST_RES_CHANGE_FLUSH; 334 if (res_change == S5P_FIMV_RES_INCREASE || 335 res_change == S5P_FIMV_RES_DECREASE) { 336 ctx->state = MFCINST_RES_CHANGE_INIT; 337 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 338 wake_up_ctx(ctx, reason, err); 339 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 340 BUG(); 341 s5p_mfc_clock_off(); 342 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 343 return; 344 } 345 if (ctx->dpb_flush_flag) 346 ctx->dpb_flush_flag = 0; 347 348 spin_lock_irqsave(&dev->irqlock, flags); 349 /* All frames remaining in the buffer have been extracted */ 350 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { 351 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { 352 s5p_mfc_handle_frame_all_extracted(ctx); 353 ctx->state = MFCINST_RES_CHANGE_END; 354 goto leave_handle_frame; 355 } else { 356 s5p_mfc_handle_frame_all_extracted(ctx); 357 } 358 } 359 360 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY || 361 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) 362 s5p_mfc_handle_frame_copy_time(ctx); 363 364 /* A frame has been decoded and is in the buffer */ 365 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || 366 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { 367 s5p_mfc_handle_frame_new(ctx, err); 368 } else { 369 mfc_debug(2, "No frame decode\n"); 370 } 371 /* Mark source buffer as complete */ 372 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 373 && !list_empty(&ctx->src_queue)) { 374 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 375 list); 376 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, 377 get_consumed_stream, dev); 378 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && 379 ctx->consumed_stream + STUFF_BYTE < 380 src_buf->b->v4l2_planes[0].bytesused) { 381 /* Run MFC again on the same buffer */ 382 mfc_debug(2, "Running again the same buffer\n"); 383 ctx->after_packed_pb = 1; 384 } else { 385 mfc_debug(2, "MFC needs next buffer\n"); 386 ctx->consumed_stream = 0; 387 if (src_buf->flags & MFC_BUF_FLAG_EOS) 388 ctx->state = MFCINST_FINISHING; 389 list_del(&src_buf->list); 390 ctx->src_queue_cnt--; 391 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) 392 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); 393 else 394 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); 395 } 396 } 397leave_handle_frame: 398 spin_unlock_irqrestore(&dev->irqlock, flags); 399 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 400 || ctx->dst_queue_cnt < ctx->pb_count) 401 clear_work_bit(ctx); 402 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 403 wake_up_ctx(ctx, reason, err); 404 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 405 BUG(); 406 s5p_mfc_clock_off(); 407 /* if suspending, wake up device and do not try_run again*/ 408 if (test_bit(0, &dev->enter_suspend)) 409 wake_up_dev(dev, reason, err); 410 else 411 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 412} 413 414/* Error handling for interrupt */ 415static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, 416 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) 417{ 418 unsigned long flags; 419 420 mfc_err("Interrupt Error: %08x\n", err); 421 422 if (ctx != NULL) { 423 /* Error recovery is dependent on the state of context */ 424 switch (ctx->state) { 425 case MFCINST_RES_CHANGE_INIT: 426 case MFCINST_RES_CHANGE_FLUSH: 427 case MFCINST_RES_CHANGE_END: 428 case MFCINST_FINISHING: 429 case MFCINST_FINISHED: 430 case MFCINST_RUNNING: 431 /* It is higly probable that an error occured 432 * while decoding a frame */ 433 clear_work_bit(ctx); 434 ctx->state = MFCINST_ERROR; 435 /* Mark all dst buffers as having an error */ 436 spin_lock_irqsave(&dev->irqlock, flags); 437 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 438 &ctx->dst_queue, &ctx->vq_dst); 439 /* Mark all src buffers as having an error */ 440 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 441 &ctx->src_queue, &ctx->vq_src); 442 spin_unlock_irqrestore(&dev->irqlock, flags); 443 wake_up_ctx(ctx, reason, err); 444 break; 445 default: 446 clear_work_bit(ctx); 447 ctx->state = MFCINST_ERROR; 448 wake_up_ctx(ctx, reason, err); 449 break; 450 } 451 } 452 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 453 BUG(); 454 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 455 s5p_mfc_clock_off(); 456 wake_up_dev(dev, reason, err); 457 return; 458} 459 460/* Header parsing interrupt handling */ 461static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 462 unsigned int reason, unsigned int err) 463{ 464 struct s5p_mfc_dev *dev; 465 466 if (ctx == NULL) 467 return; 468 dev = ctx->dev; 469 if (ctx->c_ops->post_seq_start) { 470 if (ctx->c_ops->post_seq_start(ctx)) 471 mfc_err("post_seq_start() failed\n"); 472 } else { 473 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, 474 dev); 475 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 476 dev); 477 478 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); 479 480 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 481 dev); 482 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, 483 dev); 484 if (ctx->img_width == 0 || ctx->img_height == 0) 485 ctx->state = MFCINST_ERROR; 486 else 487 ctx->state = MFCINST_HEAD_PARSED; 488 489 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 490 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && 491 !list_empty(&ctx->src_queue)) { 492 struct s5p_mfc_buf *src_buf; 493 src_buf = list_entry(ctx->src_queue.next, 494 struct s5p_mfc_buf, list); 495 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, 496 dev) < 497 src_buf->b->v4l2_planes[0].bytesused) 498 ctx->head_processed = 0; 499 else 500 ctx->head_processed = 1; 501 } else { 502 ctx->head_processed = 1; 503 } 504 } 505 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 506 clear_work_bit(ctx); 507 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 508 BUG(); 509 s5p_mfc_clock_off(); 510 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 511 wake_up_ctx(ctx, reason, err); 512} 513 514/* Header parsing interrupt handling */ 515static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, 516 unsigned int reason, unsigned int err) 517{ 518 struct s5p_mfc_buf *src_buf; 519 struct s5p_mfc_dev *dev; 520 unsigned long flags; 521 522 if (ctx == NULL) 523 return; 524 dev = ctx->dev; 525 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 526 ctx->int_type = reason; 527 ctx->int_err = err; 528 ctx->int_cond = 1; 529 clear_work_bit(ctx); 530 if (err == 0) { 531 ctx->state = MFCINST_RUNNING; 532 if (!ctx->dpb_flush_flag && ctx->head_processed) { 533 spin_lock_irqsave(&dev->irqlock, flags); 534 if (!list_empty(&ctx->src_queue)) { 535 src_buf = list_entry(ctx->src_queue.next, 536 struct s5p_mfc_buf, list); 537 list_del(&src_buf->list); 538 ctx->src_queue_cnt--; 539 vb2_buffer_done(src_buf->b, 540 VB2_BUF_STATE_DONE); 541 } 542 spin_unlock_irqrestore(&dev->irqlock, flags); 543 } else { 544 ctx->dpb_flush_flag = 0; 545 } 546 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 547 BUG(); 548 549 s5p_mfc_clock_off(); 550 551 wake_up(&ctx->queue); 552 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 553 } else { 554 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 555 BUG(); 556 557 s5p_mfc_clock_off(); 558 559 wake_up(&ctx->queue); 560 } 561} 562 563static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, 564 unsigned int reason, unsigned int err) 565{ 566 struct s5p_mfc_dev *dev = ctx->dev; 567 struct s5p_mfc_buf *mb_entry; 568 569 mfc_debug(2, "Stream completed\n"); 570 571 s5p_mfc_clear_int_flags(dev); 572 ctx->int_type = reason; 573 ctx->int_err = err; 574 ctx->state = MFCINST_FINISHED; 575 576 spin_lock(&dev->irqlock); 577 if (!list_empty(&ctx->dst_queue)) { 578 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, 579 list); 580 list_del(&mb_entry->list); 581 ctx->dst_queue_cnt--; 582 vb2_set_plane_payload(mb_entry->b, 0, 0); 583 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE); 584 } 585 spin_unlock(&dev->irqlock); 586 587 clear_work_bit(ctx); 588 589 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); 590 591 s5p_mfc_clock_off(); 592 wake_up(&ctx->queue); 593 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 594} 595 596/* Interrupt processing */ 597static irqreturn_t s5p_mfc_irq(int irq, void *priv) 598{ 599 struct s5p_mfc_dev *dev = priv; 600 struct s5p_mfc_ctx *ctx; 601 unsigned int reason; 602 unsigned int err; 603 604 mfc_debug_enter(); 605 /* Reset the timeout watchdog */ 606 atomic_set(&dev->watchdog_cnt, 0); 607 ctx = dev->ctx[dev->curr_ctx]; 608 /* Get the reason of interrupt and the error code */ 609 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); 610 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); 611 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); 612 switch (reason) { 613 case S5P_MFC_R2H_CMD_ERR_RET: 614 /* An error has occured */ 615 if (ctx->state == MFCINST_RUNNING && 616 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= 617 dev->warn_start) 618 s5p_mfc_handle_frame(ctx, reason, err); 619 else 620 s5p_mfc_handle_error(dev, ctx, reason, err); 621 clear_bit(0, &dev->enter_suspend); 622 break; 623 624 case S5P_MFC_R2H_CMD_SLICE_DONE_RET: 625 case S5P_MFC_R2H_CMD_FIELD_DONE_RET: 626 case S5P_MFC_R2H_CMD_FRAME_DONE_RET: 627 if (ctx->c_ops->post_frame_start) { 628 if (ctx->c_ops->post_frame_start(ctx)) 629 mfc_err("post_frame_start() failed\n"); 630 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 631 wake_up_ctx(ctx, reason, err); 632 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 633 BUG(); 634 s5p_mfc_clock_off(); 635 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 636 } else { 637 s5p_mfc_handle_frame(ctx, reason, err); 638 } 639 break; 640 641 case S5P_MFC_R2H_CMD_SEQ_DONE_RET: 642 s5p_mfc_handle_seq_done(ctx, reason, err); 643 break; 644 645 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: 646 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); 647 ctx->state = MFCINST_GOT_INST; 648 clear_work_bit(ctx); 649 wake_up(&ctx->queue); 650 goto irq_cleanup_hw; 651 652 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: 653 clear_work_bit(ctx); 654 ctx->state = MFCINST_FREE; 655 wake_up(&ctx->queue); 656 goto irq_cleanup_hw; 657 658 case S5P_MFC_R2H_CMD_SYS_INIT_RET: 659 case S5P_MFC_R2H_CMD_FW_STATUS_RET: 660 case S5P_MFC_R2H_CMD_SLEEP_RET: 661 case S5P_MFC_R2H_CMD_WAKEUP_RET: 662 if (ctx) 663 clear_work_bit(ctx); 664 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 665 wake_up_dev(dev, reason, err); 666 clear_bit(0, &dev->hw_lock); 667 clear_bit(0, &dev->enter_suspend); 668 break; 669 670 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: 671 s5p_mfc_handle_init_buffers(ctx, reason, err); 672 break; 673 674 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: 675 s5p_mfc_handle_stream_complete(ctx, reason, err); 676 break; 677 678 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET: 679 clear_work_bit(ctx); 680 ctx->state = MFCINST_RUNNING; 681 wake_up(&ctx->queue); 682 goto irq_cleanup_hw; 683 684 default: 685 mfc_debug(2, "Unknown int reason\n"); 686 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 687 } 688 mfc_debug_leave(); 689 return IRQ_HANDLED; 690irq_cleanup_hw: 691 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 692 ctx->int_type = reason; 693 ctx->int_err = err; 694 ctx->int_cond = 1; 695 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 696 mfc_err("Failed to unlock hw\n"); 697 698 s5p_mfc_clock_off(); 699 700 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 701 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 702 return IRQ_HANDLED; 703} 704 705/* Open an MFC node */ 706static int s5p_mfc_open(struct file *file) 707{ 708 struct s5p_mfc_dev *dev = video_drvdata(file); 709 struct s5p_mfc_ctx *ctx = NULL; 710 struct vb2_queue *q; 711 int ret = 0; 712 713 mfc_debug_enter(); 714 if (mutex_lock_interruptible(&dev->mfc_mutex)) 715 return -ERESTARTSYS; 716 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ 717 /* Allocate memory for context */ 718 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 719 if (!ctx) { 720 mfc_err("Not enough memory\n"); 721 ret = -ENOMEM; 722 goto err_alloc; 723 } 724 v4l2_fh_init(&ctx->fh, video_devdata(file)); 725 file->private_data = &ctx->fh; 726 v4l2_fh_add(&ctx->fh); 727 ctx->dev = dev; 728 INIT_LIST_HEAD(&ctx->src_queue); 729 INIT_LIST_HEAD(&ctx->dst_queue); 730 ctx->src_queue_cnt = 0; 731 ctx->dst_queue_cnt = 0; 732 /* Get context number */ 733 ctx->num = 0; 734 while (dev->ctx[ctx->num]) { 735 ctx->num++; 736 if (ctx->num >= MFC_NUM_CONTEXTS) { 737 mfc_err("Too many open contexts\n"); 738 ret = -EBUSY; 739 goto err_no_ctx; 740 } 741 } 742 /* Mark context as idle */ 743 clear_work_bit_irqsave(ctx); 744 dev->ctx[ctx->num] = ctx; 745 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 746 ctx->type = MFCINST_DECODER; 747 ctx->c_ops = get_dec_codec_ops(); 748 s5p_mfc_dec_init(ctx); 749 /* Setup ctrl handler */ 750 ret = s5p_mfc_dec_ctrls_setup(ctx); 751 if (ret) { 752 mfc_err("Failed to setup mfc controls\n"); 753 goto err_ctrls_setup; 754 } 755 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 756 ctx->type = MFCINST_ENCODER; 757 ctx->c_ops = get_enc_codec_ops(); 758 /* only for encoder */ 759 INIT_LIST_HEAD(&ctx->ref_queue); 760 ctx->ref_queue_cnt = 0; 761 s5p_mfc_enc_init(ctx); 762 /* Setup ctrl handler */ 763 ret = s5p_mfc_enc_ctrls_setup(ctx); 764 if (ret) { 765 mfc_err("Failed to setup mfc controls\n"); 766 goto err_ctrls_setup; 767 } 768 } else { 769 ret = -ENOENT; 770 goto err_bad_node; 771 } 772 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 773 ctx->inst_no = -1; 774 /* Load firmware if this is the first instance */ 775 if (dev->num_inst == 1) { 776 dev->watchdog_timer.expires = jiffies + 777 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 778 add_timer(&dev->watchdog_timer); 779 ret = s5p_mfc_power_on(); 780 if (ret < 0) { 781 mfc_err("power on failed\n"); 782 goto err_pwr_enable; 783 } 784 s5p_mfc_clock_on(); 785 ret = s5p_mfc_load_firmware(dev); 786 if (ret) { 787 s5p_mfc_clock_off(); 788 goto err_load_fw; 789 } 790 /* Init the FW */ 791 ret = s5p_mfc_init_hw(dev); 792 s5p_mfc_clock_off(); 793 if (ret) 794 goto err_init_hw; 795 } 796 /* Init videobuf2 queue for CAPTURE */ 797 q = &ctx->vq_dst; 798 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 799 q->drv_priv = &ctx->fh; 800 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 801 q->io_modes = VB2_MMAP; 802 q->ops = get_dec_queue_ops(); 803 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 804 q->io_modes = VB2_MMAP | VB2_USERPTR; 805 q->ops = get_enc_queue_ops(); 806 } else { 807 ret = -ENOENT; 808 goto err_queue_init; 809 } 810 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 811 q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; 812 ret = vb2_queue_init(q); 813 if (ret) { 814 mfc_err("Failed to initialize videobuf2 queue(capture)\n"); 815 goto err_queue_init; 816 } 817 /* Init videobuf2 queue for OUTPUT */ 818 q = &ctx->vq_src; 819 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 820 q->io_modes = VB2_MMAP; 821 q->drv_priv = &ctx->fh; 822 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 823 q->io_modes = VB2_MMAP; 824 q->ops = get_dec_queue_ops(); 825 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 826 q->io_modes = VB2_MMAP | VB2_USERPTR; 827 q->ops = get_enc_queue_ops(); 828 } else { 829 ret = -ENOENT; 830 goto err_queue_init; 831 } 832 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 833 q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; 834 ret = vb2_queue_init(q); 835 if (ret) { 836 mfc_err("Failed to initialize videobuf2 queue(output)\n"); 837 goto err_queue_init; 838 } 839 init_waitqueue_head(&ctx->queue); 840 mutex_unlock(&dev->mfc_mutex); 841 mfc_debug_leave(); 842 return ret; 843 /* Deinit when failure occured */ 844err_queue_init: 845 if (dev->num_inst == 1) 846 s5p_mfc_deinit_hw(dev); 847err_init_hw: 848err_load_fw: 849err_pwr_enable: 850 if (dev->num_inst == 1) { 851 if (s5p_mfc_power_off() < 0) 852 mfc_err("power off failed\n"); 853 del_timer_sync(&dev->watchdog_timer); 854 } 855err_ctrls_setup: 856 s5p_mfc_dec_ctrls_delete(ctx); 857err_bad_node: 858 dev->ctx[ctx->num] = NULL; 859err_no_ctx: 860 v4l2_fh_del(&ctx->fh); 861 v4l2_fh_exit(&ctx->fh); 862 kfree(ctx); 863err_alloc: 864 dev->num_inst--; 865 mutex_unlock(&dev->mfc_mutex); 866 mfc_debug_leave(); 867 return ret; 868} 869 870/* Release MFC context */ 871static int s5p_mfc_release(struct file *file) 872{ 873 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 874 struct s5p_mfc_dev *dev = ctx->dev; 875 876 mfc_debug_enter(); 877 mutex_lock(&dev->mfc_mutex); 878 s5p_mfc_clock_on(); 879 vb2_queue_release(&ctx->vq_src); 880 vb2_queue_release(&ctx->vq_dst); 881 /* Mark context as idle */ 882 clear_work_bit_irqsave(ctx); 883 /* If instance was initialised then 884 * return instance and free reosurces */ 885 if (ctx->inst_no != MFC_NO_INSTANCE_SET) { 886 mfc_debug(2, "Has to free instance\n"); 887 ctx->state = MFCINST_RETURN_INST; 888 set_work_bit_irqsave(ctx); 889 s5p_mfc_clean_ctx_int_flags(ctx); 890 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 891 /* Wait until instance is returned or timeout occured */ 892 if (s5p_mfc_wait_for_done_ctx 893 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) { 894 s5p_mfc_clock_off(); 895 mfc_err("Err returning instance\n"); 896 } 897 mfc_debug(2, "After free instance\n"); 898 /* Free resources */ 899 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); 900 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); 901 if (ctx->type == MFCINST_DECODER) 902 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, 903 ctx); 904 905 ctx->inst_no = MFC_NO_INSTANCE_SET; 906 } 907 /* hardware locking scheme */ 908 if (dev->curr_ctx == ctx->num) 909 clear_bit(0, &dev->hw_lock); 910 dev->num_inst--; 911 if (dev->num_inst == 0) { 912 mfc_debug(2, "Last instance\n"); 913 s5p_mfc_deinit_hw(dev); 914 del_timer_sync(&dev->watchdog_timer); 915 if (s5p_mfc_power_off() < 0) 916 mfc_err("Power off failed\n"); 917 } 918 mfc_debug(2, "Shutting down clock\n"); 919 s5p_mfc_clock_off(); 920 dev->ctx[ctx->num] = NULL; 921 s5p_mfc_dec_ctrls_delete(ctx); 922 v4l2_fh_del(&ctx->fh); 923 v4l2_fh_exit(&ctx->fh); 924 kfree(ctx); 925 mfc_debug_leave(); 926 mutex_unlock(&dev->mfc_mutex); 927 return 0; 928} 929 930/* Poll */ 931static unsigned int s5p_mfc_poll(struct file *file, 932 struct poll_table_struct *wait) 933{ 934 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 935 struct s5p_mfc_dev *dev = ctx->dev; 936 struct vb2_queue *src_q, *dst_q; 937 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; 938 unsigned int rc = 0; 939 unsigned long flags; 940 941 mutex_lock(&dev->mfc_mutex); 942 src_q = &ctx->vq_src; 943 dst_q = &ctx->vq_dst; 944 /* 945 * There has to be at least one buffer queued on each queued_list, which 946 * means either in driver already or waiting for driver to claim it 947 * and start processing. 948 */ 949 if ((!src_q->streaming || list_empty(&src_q->queued_list)) 950 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { 951 rc = POLLERR; 952 goto end; 953 } 954 mutex_unlock(&dev->mfc_mutex); 955 poll_wait(file, &ctx->fh.wait, wait); 956 poll_wait(file, &src_q->done_wq, wait); 957 poll_wait(file, &dst_q->done_wq, wait); 958 mutex_lock(&dev->mfc_mutex); 959 if (v4l2_event_pending(&ctx->fh)) 960 rc |= POLLPRI; 961 spin_lock_irqsave(&src_q->done_lock, flags); 962 if (!list_empty(&src_q->done_list)) 963 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, 964 done_entry); 965 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE 966 || src_vb->state == VB2_BUF_STATE_ERROR)) 967 rc |= POLLOUT | POLLWRNORM; 968 spin_unlock_irqrestore(&src_q->done_lock, flags); 969 spin_lock_irqsave(&dst_q->done_lock, flags); 970 if (!list_empty(&dst_q->done_list)) 971 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, 972 done_entry); 973 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE 974 || dst_vb->state == VB2_BUF_STATE_ERROR)) 975 rc |= POLLIN | POLLRDNORM; 976 spin_unlock_irqrestore(&dst_q->done_lock, flags); 977end: 978 mutex_unlock(&dev->mfc_mutex); 979 return rc; 980} 981 982/* Mmap */ 983static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) 984{ 985 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 986 struct s5p_mfc_dev *dev = ctx->dev; 987 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 988 int ret; 989 990 if (mutex_lock_interruptible(&dev->mfc_mutex)) 991 return -ERESTARTSYS; 992 if (offset < DST_QUEUE_OFF_BASE) { 993 mfc_debug(2, "mmaping source\n"); 994 ret = vb2_mmap(&ctx->vq_src, vma); 995 } else { /* capture */ 996 mfc_debug(2, "mmaping destination\n"); 997 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); 998 ret = vb2_mmap(&ctx->vq_dst, vma); 999 } 1000 mutex_unlock(&dev->mfc_mutex); 1001 return ret; 1002} 1003 1004/* v4l2 ops */ 1005static const struct v4l2_file_operations s5p_mfc_fops = { 1006 .owner = THIS_MODULE, 1007 .open = s5p_mfc_open, 1008 .release = s5p_mfc_release, 1009 .poll = s5p_mfc_poll, 1010 .unlocked_ioctl = video_ioctl2, 1011 .mmap = s5p_mfc_mmap, 1012}; 1013 1014static int match_child(struct device *dev, void *data) 1015{ 1016 if (!dev_name(dev)) 1017 return 0; 1018 return !strcmp(dev_name(dev), (char *)data); 1019} 1020 1021static void *mfc_get_drv_data(struct platform_device *pdev); 1022 1023static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev) 1024{ 1025 unsigned int mem_info[2] = { }; 1026 1027 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev, 1028 sizeof(struct device), GFP_KERNEL); 1029 if (!dev->mem_dev_l) { 1030 mfc_err("Not enough memory\n"); 1031 return -ENOMEM; 1032 } 1033 device_initialize(dev->mem_dev_l); 1034 of_property_read_u32_array(dev->plat_dev->dev.of_node, 1035 "samsung,mfc-l", mem_info, 2); 1036 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0], 1037 mem_info[0], mem_info[1], 1038 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1039 mfc_err("Failed to declare coherent memory for\n" 1040 "MFC device\n"); 1041 return -ENOMEM; 1042 } 1043 1044 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev, 1045 sizeof(struct device), GFP_KERNEL); 1046 if (!dev->mem_dev_r) { 1047 mfc_err("Not enough memory\n"); 1048 return -ENOMEM; 1049 } 1050 device_initialize(dev->mem_dev_r); 1051 of_property_read_u32_array(dev->plat_dev->dev.of_node, 1052 "samsung,mfc-r", mem_info, 2); 1053 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0], 1054 mem_info[0], mem_info[1], 1055 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1056 pr_err("Failed to declare coherent memory for\n" 1057 "MFC device\n"); 1058 return -ENOMEM; 1059 } 1060 return 0; 1061} 1062 1063/* MFC probe function */ 1064static int s5p_mfc_probe(struct platform_device *pdev) 1065{ 1066 struct s5p_mfc_dev *dev; 1067 struct video_device *vfd; 1068 struct resource *res; 1069 int ret; 1070 1071 pr_debug("%s++\n", __func__); 1072 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1073 if (!dev) { 1074 dev_err(&pdev->dev, "Not enough memory for MFC device\n"); 1075 return -ENOMEM; 1076 } 1077 1078 spin_lock_init(&dev->irqlock); 1079 spin_lock_init(&dev->condlock); 1080 dev->plat_dev = pdev; 1081 if (!dev->plat_dev) { 1082 dev_err(&pdev->dev, "No platform data specified\n"); 1083 return -ENODEV; 1084 } 1085 1086 dev->variant = mfc_get_drv_data(pdev); 1087 1088 ret = s5p_mfc_init_pm(dev); 1089 if (ret < 0) { 1090 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 1091 return ret; 1092 } 1093 1094 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1095 1096 dev->regs_base = devm_ioremap_resource(&pdev->dev, res); 1097 if (IS_ERR(dev->regs_base)) 1098 return PTR_ERR(dev->regs_base); 1099 1100 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1101 if (res == NULL) { 1102 dev_err(&pdev->dev, "failed to get irq resource\n"); 1103 ret = -ENOENT; 1104 goto err_res; 1105 } 1106 dev->irq = res->start; 1107 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, 1108 0, pdev->name, dev); 1109 if (ret) { 1110 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); 1111 goto err_res; 1112 } 1113 1114 if (pdev->dev.of_node) { 1115 ret = s5p_mfc_alloc_memdevs(dev); 1116 if (ret < 0) 1117 goto err_res; 1118 } else { 1119 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, 1120 "s5p-mfc-l", match_child); 1121 if (!dev->mem_dev_l) { 1122 mfc_err("Mem child (L) device get failed\n"); 1123 ret = -ENODEV; 1124 goto err_res; 1125 } 1126 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, 1127 "s5p-mfc-r", match_child); 1128 if (!dev->mem_dev_r) { 1129 mfc_err("Mem child (R) device get failed\n"); 1130 ret = -ENODEV; 1131 goto err_res; 1132 } 1133 } 1134 1135 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); 1136 if (IS_ERR(dev->alloc_ctx[0])) { 1137 ret = PTR_ERR(dev->alloc_ctx[0]); 1138 goto err_res; 1139 } 1140 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); 1141 if (IS_ERR(dev->alloc_ctx[1])) { 1142 ret = PTR_ERR(dev->alloc_ctx[1]); 1143 goto err_mem_init_ctx_1; 1144 } 1145 1146 mutex_init(&dev->mfc_mutex); 1147 1148 ret = s5p_mfc_alloc_firmware(dev); 1149 if (ret) 1150 goto err_alloc_fw; 1151 1152 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 1153 if (ret) 1154 goto err_v4l2_dev_reg; 1155 init_waitqueue_head(&dev->queue); 1156 1157 /* decoder */ 1158 vfd = video_device_alloc(); 1159 if (!vfd) { 1160 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1161 ret = -ENOMEM; 1162 goto err_dec_alloc; 1163 } 1164 vfd->fops = &s5p_mfc_fops, 1165 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); 1166 vfd->release = video_device_release, 1167 vfd->lock = &dev->mfc_mutex; 1168 vfd->v4l2_dev = &dev->v4l2_dev; 1169 vfd->vfl_dir = VFL_DIR_M2M; 1170 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); 1171 dev->vfd_dec = vfd; 1172 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1173 if (ret) { 1174 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1175 video_device_release(vfd); 1176 goto err_dec_reg; 1177 } 1178 v4l2_info(&dev->v4l2_dev, 1179 "decoder registered as /dev/video%d\n", vfd->num); 1180 video_set_drvdata(vfd, dev); 1181 1182 /* encoder */ 1183 vfd = video_device_alloc(); 1184 if (!vfd) { 1185 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1186 ret = -ENOMEM; 1187 goto err_enc_alloc; 1188 } 1189 vfd->fops = &s5p_mfc_fops, 1190 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); 1191 vfd->release = video_device_release, 1192 vfd->lock = &dev->mfc_mutex; 1193 vfd->v4l2_dev = &dev->v4l2_dev; 1194 vfd->vfl_dir = VFL_DIR_M2M; 1195 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); 1196 dev->vfd_enc = vfd; 1197 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1198 if (ret) { 1199 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1200 video_device_release(vfd); 1201 goto err_enc_reg; 1202 } 1203 v4l2_info(&dev->v4l2_dev, 1204 "encoder registered as /dev/video%d\n", vfd->num); 1205 video_set_drvdata(vfd, dev); 1206 platform_set_drvdata(pdev, dev); 1207 1208 dev->hw_lock = 0; 1209 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); 1210 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); 1211 atomic_set(&dev->watchdog_cnt, 0); 1212 init_timer(&dev->watchdog_timer); 1213 dev->watchdog_timer.data = (unsigned long)dev; 1214 dev->watchdog_timer.function = s5p_mfc_watchdog; 1215 1216 /* Initialize HW ops and commands based on MFC version */ 1217 s5p_mfc_init_hw_ops(dev); 1218 s5p_mfc_init_hw_cmds(dev); 1219 1220 pr_debug("%s--\n", __func__); 1221 return 0; 1222 1223/* Deinit MFC if probe had failed */ 1224err_enc_reg: 1225 video_device_release(dev->vfd_enc); 1226err_enc_alloc: 1227 video_unregister_device(dev->vfd_dec); 1228err_dec_reg: 1229 video_device_release(dev->vfd_dec); 1230err_dec_alloc: 1231 v4l2_device_unregister(&dev->v4l2_dev); 1232err_v4l2_dev_reg: 1233 s5p_mfc_release_firmware(dev); 1234err_alloc_fw: 1235 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1236err_mem_init_ctx_1: 1237 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1238err_res: 1239 s5p_mfc_final_pm(dev); 1240 1241 pr_debug("%s-- with error\n", __func__); 1242 return ret; 1243 1244} 1245 1246/* Remove the driver */ 1247static int s5p_mfc_remove(struct platform_device *pdev) 1248{ 1249 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); 1250 1251 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); 1252 1253 del_timer_sync(&dev->watchdog_timer); 1254 flush_workqueue(dev->watchdog_workqueue); 1255 destroy_workqueue(dev->watchdog_workqueue); 1256 1257 video_unregister_device(dev->vfd_enc); 1258 video_unregister_device(dev->vfd_dec); 1259 v4l2_device_unregister(&dev->v4l2_dev); 1260 s5p_mfc_release_firmware(dev); 1261 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1262 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1263 if (pdev->dev.of_node) { 1264 put_device(dev->mem_dev_l); 1265 put_device(dev->mem_dev_r); 1266 } 1267 1268 s5p_mfc_final_pm(dev); 1269 return 0; 1270} 1271 1272#ifdef CONFIG_PM_SLEEP 1273 1274static int s5p_mfc_suspend(struct device *dev) 1275{ 1276 struct platform_device *pdev = to_platform_device(dev); 1277 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1278 int ret; 1279 1280 if (m_dev->num_inst == 0) 1281 return 0; 1282 1283 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { 1284 mfc_err("Error: going to suspend for a second time\n"); 1285 return -EIO; 1286 } 1287 1288 /* Check if we're processing then wait if it necessary. */ 1289 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { 1290 /* Try and lock the HW */ 1291 /* Wait on the interrupt waitqueue */ 1292 ret = wait_event_interruptible_timeout(m_dev->queue, 1293 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT)); 1294 if (ret == 0) { 1295 mfc_err("Waiting for hardware to finish timed out\n"); 1296 return -EIO; 1297 } 1298 } 1299 1300 return s5p_mfc_sleep(m_dev); 1301} 1302 1303static int s5p_mfc_resume(struct device *dev) 1304{ 1305 struct platform_device *pdev = to_platform_device(dev); 1306 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1307 1308 if (m_dev->num_inst == 0) 1309 return 0; 1310 return s5p_mfc_wakeup(m_dev); 1311} 1312#endif 1313 1314#ifdef CONFIG_PM_RUNTIME 1315static int s5p_mfc_runtime_suspend(struct device *dev) 1316{ 1317 struct platform_device *pdev = to_platform_device(dev); 1318 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1319 1320 atomic_set(&m_dev->pm.power, 0); 1321 return 0; 1322} 1323 1324static int s5p_mfc_runtime_resume(struct device *dev) 1325{ 1326 struct platform_device *pdev = to_platform_device(dev); 1327 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1328 int pre_power; 1329 1330 if (!m_dev->alloc_ctx) 1331 return 0; 1332 pre_power = atomic_read(&m_dev->pm.power); 1333 atomic_set(&m_dev->pm.power, 1); 1334 return 0; 1335} 1336#endif 1337 1338/* Power management */ 1339static const struct dev_pm_ops s5p_mfc_pm_ops = { 1340 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) 1341 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, 1342 NULL) 1343}; 1344 1345struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { 1346 .h264_ctx = MFC_H264_CTX_BUF_SIZE, 1347 .non_h264_ctx = MFC_CTX_BUF_SIZE, 1348 .dsc = DESC_BUF_SIZE, 1349 .shm = SHARED_BUF_SIZE, 1350}; 1351 1352struct s5p_mfc_buf_size buf_size_v5 = { 1353 .fw = MAX_FW_SIZE, 1354 .cpb = MAX_CPB_SIZE, 1355 .priv = &mfc_buf_size_v5, 1356}; 1357 1358struct s5p_mfc_buf_align mfc_buf_align_v5 = { 1359 .base = MFC_BASE_ALIGN_ORDER, 1360}; 1361 1362static struct s5p_mfc_variant mfc_drvdata_v5 = { 1363 .version = MFC_VERSION, 1364 .port_num = MFC_NUM_PORTS, 1365 .buf_size = &buf_size_v5, 1366 .buf_align = &mfc_buf_align_v5, 1367 .fw_name = "s5p-mfc.fw", 1368}; 1369 1370struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { 1371 .dev_ctx = MFC_CTX_BUF_SIZE_V6, 1372 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, 1373 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, 1374 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, 1375 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, 1376}; 1377 1378struct s5p_mfc_buf_size buf_size_v6 = { 1379 .fw = MAX_FW_SIZE_V6, 1380 .cpb = MAX_CPB_SIZE_V6, 1381 .priv = &mfc_buf_size_v6, 1382}; 1383 1384struct s5p_mfc_buf_align mfc_buf_align_v6 = { 1385 .base = 0, 1386}; 1387 1388static struct s5p_mfc_variant mfc_drvdata_v6 = { 1389 .version = MFC_VERSION_V6, 1390 .port_num = MFC_NUM_PORTS_V6, 1391 .buf_size = &buf_size_v6, 1392 .buf_align = &mfc_buf_align_v6, 1393 .fw_name = "s5p-mfc-v6.fw", 1394}; 1395 1396struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = { 1397 .dev_ctx = MFC_CTX_BUF_SIZE_V7, 1398 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7, 1399 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7, 1400 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7, 1401 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7, 1402}; 1403 1404struct s5p_mfc_buf_size buf_size_v7 = { 1405 .fw = MAX_FW_SIZE_V7, 1406 .cpb = MAX_CPB_SIZE_V7, 1407 .priv = &mfc_buf_size_v7, 1408}; 1409 1410struct s5p_mfc_buf_align mfc_buf_align_v7 = { 1411 .base = 0, 1412}; 1413 1414static struct s5p_mfc_variant mfc_drvdata_v7 = { 1415 .version = MFC_VERSION_V7, 1416 .port_num = MFC_NUM_PORTS_V7, 1417 .buf_size = &buf_size_v7, 1418 .buf_align = &mfc_buf_align_v7, 1419 .fw_name = "s5p-mfc-v7.fw", 1420}; 1421 1422static struct platform_device_id mfc_driver_ids[] = { 1423 { 1424 .name = "s5p-mfc", 1425 .driver_data = (unsigned long)&mfc_drvdata_v5, 1426 }, { 1427 .name = "s5p-mfc-v5", 1428 .driver_data = (unsigned long)&mfc_drvdata_v5, 1429 }, { 1430 .name = "s5p-mfc-v6", 1431 .driver_data = (unsigned long)&mfc_drvdata_v6, 1432 }, { 1433 .name = "s5p-mfc-v7", 1434 .driver_data = (unsigned long)&mfc_drvdata_v7, 1435 }, 1436 {}, 1437}; 1438MODULE_DEVICE_TABLE(platform, mfc_driver_ids); 1439 1440static const struct of_device_id exynos_mfc_match[] = { 1441 { 1442 .compatible = "samsung,mfc-v5", 1443 .data = &mfc_drvdata_v5, 1444 }, { 1445 .compatible = "samsung,mfc-v6", 1446 .data = &mfc_drvdata_v6, 1447 }, { 1448 .compatible = "samsung,mfc-v7", 1449 .data = &mfc_drvdata_v7, 1450 }, 1451 {}, 1452}; 1453MODULE_DEVICE_TABLE(of, exynos_mfc_match); 1454 1455static void *mfc_get_drv_data(struct platform_device *pdev) 1456{ 1457 struct s5p_mfc_variant *driver_data = NULL; 1458 1459 if (pdev->dev.of_node) { 1460 const struct of_device_id *match; 1461 match = of_match_node(exynos_mfc_match, 1462 pdev->dev.of_node); 1463 if (match) 1464 driver_data = (struct s5p_mfc_variant *)match->data; 1465 } else { 1466 driver_data = (struct s5p_mfc_variant *) 1467 platform_get_device_id(pdev)->driver_data; 1468 } 1469 return driver_data; 1470} 1471 1472static struct platform_driver s5p_mfc_driver = { 1473 .probe = s5p_mfc_probe, 1474 .remove = s5p_mfc_remove, 1475 .id_table = mfc_driver_ids, 1476 .driver = { 1477 .name = S5P_MFC_NAME, 1478 .owner = THIS_MODULE, 1479 .pm = &s5p_mfc_pm_ops, 1480 .of_match_table = exynos_mfc_match, 1481 }, 1482}; 1483 1484module_platform_driver(s5p_mfc_driver); 1485 1486MODULE_LICENSE("GPL"); 1487MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); 1488MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); 1489 1490