s5p_mfc.c revision 43a1ea1f90382a6a8fcf5ed94835b8518ebdefc8
1/* 2 * Samsung S5P Multi Format Codec v 5.1 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Kamil Debski, <k.debski@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22#include <media/v4l2-event.h> 23#include <linux/workqueue.h> 24#include <media/videobuf2-core.h> 25#include "s5p_mfc_common.h" 26#include "s5p_mfc_ctrl.h" 27#include "s5p_mfc_debug.h" 28#include "s5p_mfc_dec.h" 29#include "s5p_mfc_enc.h" 30#include "s5p_mfc_intr.h" 31#include "s5p_mfc_opr.h" 32#include "s5p_mfc_cmd.h" 33#include "s5p_mfc_pm.h" 34 35#define S5P_MFC_NAME "s5p-mfc" 36#define S5P_MFC_DEC_NAME "s5p-mfc-dec" 37#define S5P_MFC_ENC_NAME "s5p-mfc-enc" 38 39int debug; 40module_param(debug, int, S_IRUGO | S_IWUSR); 41MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); 42 43/* Helper functions for interrupt processing */ 44 45/* Remove from hw execution round robin */ 46void clear_work_bit(struct s5p_mfc_ctx *ctx) 47{ 48 struct s5p_mfc_dev *dev = ctx->dev; 49 50 spin_lock(&dev->condlock); 51 __clear_bit(ctx->num, &dev->ctx_work_bits); 52 spin_unlock(&dev->condlock); 53} 54 55/* Add to hw execution round robin */ 56void set_work_bit(struct s5p_mfc_ctx *ctx) 57{ 58 struct s5p_mfc_dev *dev = ctx->dev; 59 60 spin_lock(&dev->condlock); 61 __set_bit(ctx->num, &dev->ctx_work_bits); 62 spin_unlock(&dev->condlock); 63} 64 65/* Remove from hw execution round robin */ 66void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 67{ 68 struct s5p_mfc_dev *dev = ctx->dev; 69 unsigned long flags; 70 71 spin_lock_irqsave(&dev->condlock, flags); 72 __clear_bit(ctx->num, &dev->ctx_work_bits); 73 spin_unlock_irqrestore(&dev->condlock, flags); 74} 75 76/* Add to hw execution round robin */ 77void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 78{ 79 struct s5p_mfc_dev *dev = ctx->dev; 80 unsigned long flags; 81 82 spin_lock_irqsave(&dev->condlock, flags); 83 __set_bit(ctx->num, &dev->ctx_work_bits); 84 spin_unlock_irqrestore(&dev->condlock, flags); 85} 86 87/* Wake up context wait_queue */ 88static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, 89 unsigned int err) 90{ 91 ctx->int_cond = 1; 92 ctx->int_type = reason; 93 ctx->int_err = err; 94 wake_up(&ctx->queue); 95} 96 97/* Wake up device wait_queue */ 98static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, 99 unsigned int err) 100{ 101 dev->int_cond = 1; 102 dev->int_type = reason; 103 dev->int_err = err; 104 wake_up(&dev->queue); 105} 106 107static void s5p_mfc_watchdog(unsigned long arg) 108{ 109 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; 110 111 if (test_bit(0, &dev->hw_lock)) 112 atomic_inc(&dev->watchdog_cnt); 113 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { 114 /* This means that hw is busy and no interrupts were 115 * generated by hw for the Nth time of running this 116 * watchdog timer. This usually means a serious hw 117 * error. Now it is time to kill all instances and 118 * reset the MFC. */ 119 mfc_err("Time out during waiting for HW\n"); 120 queue_work(dev->watchdog_workqueue, &dev->watchdog_work); 121 } 122 dev->watchdog_timer.expires = jiffies + 123 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 124 add_timer(&dev->watchdog_timer); 125} 126 127static void s5p_mfc_watchdog_worker(struct work_struct *work) 128{ 129 struct s5p_mfc_dev *dev; 130 struct s5p_mfc_ctx *ctx; 131 unsigned long flags; 132 int mutex_locked; 133 int i, ret; 134 135 dev = container_of(work, struct s5p_mfc_dev, watchdog_work); 136 137 mfc_err("Driver timeout error handling\n"); 138 /* Lock the mutex that protects open and release. 139 * This is necessary as they may load and unload firmware. */ 140 mutex_locked = mutex_trylock(&dev->mfc_mutex); 141 if (!mutex_locked) 142 mfc_err("Error: some instance may be closing/opening\n"); 143 spin_lock_irqsave(&dev->irqlock, flags); 144 145 s5p_mfc_clock_off(); 146 147 for (i = 0; i < MFC_NUM_CONTEXTS; i++) { 148 ctx = dev->ctx[i]; 149 if (!ctx) 150 continue; 151 ctx->state = MFCINST_ERROR; 152 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 153 &ctx->vq_dst); 154 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 155 &ctx->vq_src); 156 clear_work_bit(ctx); 157 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); 158 } 159 clear_bit(0, &dev->hw_lock); 160 spin_unlock_irqrestore(&dev->irqlock, flags); 161 /* Double check if there is at least one instance running. 162 * If no instance is in memory than no firmware should be present */ 163 if (dev->num_inst > 0) { 164 ret = s5p_mfc_reload_firmware(dev); 165 if (ret) { 166 mfc_err("Failed to reload FW\n"); 167 goto unlock; 168 } 169 s5p_mfc_clock_on(); 170 ret = s5p_mfc_init_hw(dev); 171 if (ret) 172 mfc_err("Failed to reinit FW\n"); 173 } 174unlock: 175 if (mutex_locked) 176 mutex_unlock(&dev->mfc_mutex); 177} 178 179static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file) 180{ 181 struct video_device *vdev = video_devdata(file); 182 183 if (!vdev) { 184 mfc_err("failed to get video_device"); 185 return MFCNODE_INVALID; 186 } 187 if (vdev->index == 0) 188 return MFCNODE_DECODER; 189 else if (vdev->index == 1) 190 return MFCNODE_ENCODER; 191 return MFCNODE_INVALID; 192} 193 194static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) 195{ 196 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 197 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 198 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 199} 200 201static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) 202{ 203 struct s5p_mfc_buf *dst_buf; 204 struct s5p_mfc_dev *dev = ctx->dev; 205 206 ctx->state = MFCINST_FINISHED; 207 ctx->sequence++; 208 while (!list_empty(&ctx->dst_queue)) { 209 dst_buf = list_entry(ctx->dst_queue.next, 210 struct s5p_mfc_buf, list); 211 mfc_debug(2, "Cleaning up buffer: %d\n", 212 dst_buf->b->v4l2_buf.index); 213 vb2_set_plane_payload(dst_buf->b, 0, 0); 214 vb2_set_plane_payload(dst_buf->b, 1, 0); 215 list_del(&dst_buf->list); 216 ctx->dst_queue_cnt--; 217 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); 218 219 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == 220 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) 221 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 222 else 223 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; 224 225 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); 226 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); 227 } 228} 229 230static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) 231{ 232 struct s5p_mfc_dev *dev = ctx->dev; 233 struct s5p_mfc_buf *dst_buf, *src_buf; 234 size_t dec_y_addr; 235 unsigned int frame_type; 236 237 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); 238 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 239 240 /* Copy timestamp / timecode from decoded src to dst and set 241 appropraite flags */ 242 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 243 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 244 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { 245 memcpy(&dst_buf->b->v4l2_buf.timecode, 246 &src_buf->b->v4l2_buf.timecode, 247 sizeof(struct v4l2_timecode)); 248 memcpy(&dst_buf->b->v4l2_buf.timestamp, 249 &src_buf->b->v4l2_buf.timestamp, 250 sizeof(struct timeval)); 251 switch (frame_type) { 252 case S5P_FIMV_DECODE_FRAME_I_FRAME: 253 dst_buf->b->v4l2_buf.flags |= 254 V4L2_BUF_FLAG_KEYFRAME; 255 break; 256 case S5P_FIMV_DECODE_FRAME_P_FRAME: 257 dst_buf->b->v4l2_buf.flags |= 258 V4L2_BUF_FLAG_PFRAME; 259 break; 260 case S5P_FIMV_DECODE_FRAME_B_FRAME: 261 dst_buf->b->v4l2_buf.flags |= 262 V4L2_BUF_FLAG_BFRAME; 263 break; 264 } 265 break; 266 } 267 } 268} 269 270static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) 271{ 272 struct s5p_mfc_dev *dev = ctx->dev; 273 struct s5p_mfc_buf *dst_buf; 274 size_t dspl_y_addr; 275 unsigned int frame_type; 276 unsigned int index; 277 278 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); 279 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 280 281 /* If frame is same as previous then skip and do not dequeue */ 282 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { 283 if (!ctx->after_packed_pb) 284 ctx->sequence++; 285 ctx->after_packed_pb = 0; 286 return; 287 } 288 ctx->sequence++; 289 /* The MFC returns address of the buffer, now we have to 290 * check which videobuf does it correspond to */ 291 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 292 /* Check if this is the buffer we're looking for */ 293 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { 294 list_del(&dst_buf->list); 295 ctx->dst_queue_cnt--; 296 dst_buf->b->v4l2_buf.sequence = ctx->sequence; 297 if (s5p_mfc_hw_call(dev->mfc_ops, 298 get_pic_type_top, ctx) == 299 s5p_mfc_hw_call(dev->mfc_ops, 300 get_pic_type_bot, ctx)) 301 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 302 else 303 dst_buf->b->v4l2_buf.field = 304 V4L2_FIELD_INTERLACED; 305 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); 306 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); 307 clear_bit(dst_buf->b->v4l2_buf.index, 308 &ctx->dec_dst_flag); 309 310 vb2_buffer_done(dst_buf->b, 311 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 312 313 index = dst_buf->b->v4l2_buf.index; 314 break; 315 } 316 } 317} 318 319/* Handle frame decoding interrupt */ 320static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, 321 unsigned int reason, unsigned int err) 322{ 323 struct s5p_mfc_dev *dev = ctx->dev; 324 unsigned int dst_frame_status; 325 struct s5p_mfc_buf *src_buf; 326 unsigned long flags; 327 unsigned int res_change; 328 329 unsigned int index; 330 331 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 332 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 333 res_change = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 334 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK; 335 mfc_debug(2, "Frame Status: %x\n", dst_frame_status); 336 if (ctx->state == MFCINST_RES_CHANGE_INIT) 337 ctx->state = MFCINST_RES_CHANGE_FLUSH; 338 if (res_change) { 339 ctx->state = MFCINST_RES_CHANGE_INIT; 340 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 341 wake_up_ctx(ctx, reason, err); 342 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 343 BUG(); 344 s5p_mfc_clock_off(); 345 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 346 return; 347 } 348 if (ctx->dpb_flush_flag) 349 ctx->dpb_flush_flag = 0; 350 351 spin_lock_irqsave(&dev->irqlock, flags); 352 /* All frames remaining in the buffer have been extracted */ 353 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { 354 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { 355 s5p_mfc_handle_frame_all_extracted(ctx); 356 ctx->state = MFCINST_RES_CHANGE_END; 357 goto leave_handle_frame; 358 } else { 359 s5p_mfc_handle_frame_all_extracted(ctx); 360 } 361 } 362 363 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY || 364 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) 365 s5p_mfc_handle_frame_copy_time(ctx); 366 367 /* A frame has been decoded and is in the buffer */ 368 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || 369 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { 370 s5p_mfc_handle_frame_new(ctx, err); 371 } else { 372 mfc_debug(2, "No frame decode\n"); 373 } 374 /* Mark source buffer as complete */ 375 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 376 && !list_empty(&ctx->src_queue)) { 377 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 378 list); 379 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, 380 get_consumed_stream, dev); 381 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && 382 s5p_mfc_hw_call(dev->mfc_ops, 383 get_dec_frame_type, dev) == 384 S5P_FIMV_DECODE_FRAME_P_FRAME 385 && ctx->consumed_stream + STUFF_BYTE < 386 src_buf->b->v4l2_planes[0].bytesused) { 387 /* Run MFC again on the same buffer */ 388 mfc_debug(2, "Running again the same buffer\n"); 389 ctx->after_packed_pb = 1; 390 } else { 391 index = src_buf->b->v4l2_buf.index; 392 mfc_debug(2, "MFC needs next buffer\n"); 393 ctx->consumed_stream = 0; 394 list_del(&src_buf->list); 395 ctx->src_queue_cnt--; 396 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) 397 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); 398 else 399 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); 400 } 401 } 402leave_handle_frame: 403 spin_unlock_irqrestore(&dev->irqlock, flags); 404 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 405 || ctx->dst_queue_cnt < ctx->dpb_count) 406 clear_work_bit(ctx); 407 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 408 wake_up_ctx(ctx, reason, err); 409 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 410 BUG(); 411 s5p_mfc_clock_off(); 412 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 413} 414 415/* Error handling for interrupt */ 416static void s5p_mfc_handle_error(struct s5p_mfc_ctx *ctx, 417 unsigned int reason, unsigned int err) 418{ 419 struct s5p_mfc_dev *dev; 420 unsigned long flags; 421 422 /* If no context is available then all necessary 423 * processing has been done. */ 424 if (ctx == NULL) 425 return; 426 427 dev = ctx->dev; 428 mfc_err("Interrupt Error: %08x\n", err); 429 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 430 wake_up_dev(dev, reason, err); 431 432 /* Error recovery is dependent on the state of context */ 433 switch (ctx->state) { 434 case MFCINST_INIT: 435 /* This error had to happen while acquireing instance */ 436 case MFCINST_GOT_INST: 437 /* This error had to happen while parsing the header */ 438 case MFCINST_HEAD_PARSED: 439 /* This error had to happen while setting dst buffers */ 440 case MFCINST_RETURN_INST: 441 /* This error had to happen while releasing instance */ 442 clear_work_bit(ctx); 443 wake_up_ctx(ctx, reason, err); 444 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 445 BUG(); 446 s5p_mfc_clock_off(); 447 ctx->state = MFCINST_ERROR; 448 break; 449 case MFCINST_FINISHING: 450 case MFCINST_FINISHED: 451 case MFCINST_RUNNING: 452 /* It is higly probable that an error occured 453 * while decoding a frame */ 454 clear_work_bit(ctx); 455 ctx->state = MFCINST_ERROR; 456 /* Mark all dst buffers as having an error */ 457 spin_lock_irqsave(&dev->irqlock, flags); 458 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 459 &ctx->vq_dst); 460 /* Mark all src buffers as having an error */ 461 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 462 &ctx->vq_src); 463 spin_unlock_irqrestore(&dev->irqlock, flags); 464 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 465 BUG(); 466 s5p_mfc_clock_off(); 467 break; 468 default: 469 mfc_err("Encountered an error interrupt which had not been handled\n"); 470 break; 471 } 472 return; 473} 474 475/* Header parsing interrupt handling */ 476static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 477 unsigned int reason, unsigned int err) 478{ 479 struct s5p_mfc_dev *dev; 480 unsigned int guard_width, guard_height; 481 482 if (ctx == NULL) 483 return; 484 dev = ctx->dev; 485 if (ctx->c_ops->post_seq_start) { 486 if (ctx->c_ops->post_seq_start(ctx)) 487 mfc_err("post_seq_start() failed\n"); 488 } else { 489 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, 490 dev); 491 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 492 dev); 493 494 ctx->buf_width = ALIGN(ctx->img_width, 495 S5P_FIMV_NV12MT_HALIGN); 496 ctx->buf_height = ALIGN(ctx->img_height, 497 S5P_FIMV_NV12MT_VALIGN); 498 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d, " 499 "buffer dimensions: %dx%d\n", ctx->img_width, 500 ctx->img_height, ctx->buf_width, 501 ctx->buf_height); 502 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC) { 503 ctx->luma_size = ALIGN(ctx->buf_width * 504 ctx->buf_height, S5P_FIMV_DEC_BUF_ALIGN); 505 ctx->chroma_size = ALIGN(ctx->buf_width * 506 ALIGN((ctx->img_height >> 1), 507 S5P_FIMV_NV12MT_VALIGN), 508 S5P_FIMV_DEC_BUF_ALIGN); 509 ctx->mv_size = ALIGN(ctx->buf_width * 510 ALIGN((ctx->buf_height >> 2), 511 S5P_FIMV_NV12MT_VALIGN), 512 S5P_FIMV_DEC_BUF_ALIGN); 513 } else { 514 guard_width = ALIGN(ctx->img_width + 24, 515 S5P_FIMV_NV12MT_HALIGN); 516 guard_height = ALIGN(ctx->img_height + 16, 517 S5P_FIMV_NV12MT_VALIGN); 518 ctx->luma_size = ALIGN(guard_width * 519 guard_height, S5P_FIMV_DEC_BUF_ALIGN); 520 guard_width = ALIGN(ctx->img_width + 16, 521 S5P_FIMV_NV12MT_HALIGN); 522 guard_height = ALIGN((ctx->img_height >> 1) + 4, 523 S5P_FIMV_NV12MT_VALIGN); 524 ctx->chroma_size = ALIGN(guard_width * 525 guard_height, S5P_FIMV_DEC_BUF_ALIGN); 526 ctx->mv_size = 0; 527 } 528 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 529 dev); 530 if (ctx->img_width == 0 || ctx->img_height == 0) 531 ctx->state = MFCINST_ERROR; 532 else 533 ctx->state = MFCINST_HEAD_PARSED; 534 } 535 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 536 clear_work_bit(ctx); 537 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 538 BUG(); 539 s5p_mfc_clock_off(); 540 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 541 wake_up_ctx(ctx, reason, err); 542} 543 544/* Header parsing interrupt handling */ 545static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, 546 unsigned int reason, unsigned int err) 547{ 548 struct s5p_mfc_buf *src_buf; 549 struct s5p_mfc_dev *dev; 550 unsigned long flags; 551 552 if (ctx == NULL) 553 return; 554 dev = ctx->dev; 555 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 556 ctx->int_type = reason; 557 ctx->int_err = err; 558 ctx->int_cond = 1; 559 clear_work_bit(ctx); 560 if (err == 0) { 561 ctx->state = MFCINST_RUNNING; 562 if (!ctx->dpb_flush_flag) { 563 spin_lock_irqsave(&dev->irqlock, flags); 564 if (!list_empty(&ctx->src_queue)) { 565 src_buf = list_entry(ctx->src_queue.next, 566 struct s5p_mfc_buf, list); 567 list_del(&src_buf->list); 568 ctx->src_queue_cnt--; 569 vb2_buffer_done(src_buf->b, 570 VB2_BUF_STATE_DONE); 571 } 572 spin_unlock_irqrestore(&dev->irqlock, flags); 573 } else { 574 ctx->dpb_flush_flag = 0; 575 } 576 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 577 BUG(); 578 579 s5p_mfc_clock_off(); 580 581 wake_up(&ctx->queue); 582 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 583 } else { 584 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 585 BUG(); 586 587 s5p_mfc_clock_off(); 588 589 wake_up(&ctx->queue); 590 } 591} 592 593static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, 594 unsigned int reason, unsigned int err) 595{ 596 struct s5p_mfc_dev *dev = ctx->dev; 597 struct s5p_mfc_buf *mb_entry; 598 599 mfc_debug(2, "Stream completed"); 600 601 s5p_mfc_clear_int_flags(dev); 602 ctx->int_type = reason; 603 ctx->int_err = err; 604 ctx->state = MFCINST_FINISHED; 605 606 spin_lock(&dev->irqlock); 607 if (!list_empty(&ctx->dst_queue)) { 608 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, 609 list); 610 list_del(&mb_entry->list); 611 ctx->dst_queue_cnt--; 612 vb2_set_plane_payload(mb_entry->b, 0, 0); 613 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE); 614 } 615 spin_unlock(&dev->irqlock); 616 617 clear_work_bit(ctx); 618 619 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 620 WARN_ON(1); 621 622 s5p_mfc_clock_off(); 623 wake_up(&ctx->queue); 624 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 625} 626 627/* Interrupt processing */ 628static irqreturn_t s5p_mfc_irq(int irq, void *priv) 629{ 630 struct s5p_mfc_dev *dev = priv; 631 struct s5p_mfc_ctx *ctx; 632 unsigned int reason; 633 unsigned int err; 634 635 mfc_debug_enter(); 636 /* Reset the timeout watchdog */ 637 atomic_set(&dev->watchdog_cnt, 0); 638 ctx = dev->ctx[dev->curr_ctx]; 639 /* Get the reason of interrupt and the error code */ 640 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); 641 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); 642 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); 643 switch (reason) { 644 case S5P_MFC_R2H_CMD_ERR_RET: 645 /* An error has occured */ 646 if (ctx->state == MFCINST_RUNNING && 647 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= 648 dev->warn_start) 649 s5p_mfc_handle_frame(ctx, reason, err); 650 else 651 s5p_mfc_handle_error(ctx, reason, err); 652 clear_bit(0, &dev->enter_suspend); 653 break; 654 655 case S5P_MFC_R2H_CMD_SLICE_DONE_RET: 656 case S5P_MFC_R2H_CMD_FIELD_DONE_RET: 657 case S5P_MFC_R2H_CMD_FRAME_DONE_RET: 658 if (ctx->c_ops->post_frame_start) { 659 if (ctx->c_ops->post_frame_start(ctx)) 660 mfc_err("post_frame_start() failed\n"); 661 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 662 wake_up_ctx(ctx, reason, err); 663 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 664 BUG(); 665 s5p_mfc_clock_off(); 666 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 667 } else { 668 s5p_mfc_handle_frame(ctx, reason, err); 669 } 670 break; 671 672 case S5P_MFC_R2H_CMD_SEQ_DONE_RET: 673 s5p_mfc_handle_seq_done(ctx, reason, err); 674 break; 675 676 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: 677 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); 678 ctx->state = MFCINST_GOT_INST; 679 clear_work_bit(ctx); 680 wake_up(&ctx->queue); 681 goto irq_cleanup_hw; 682 683 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: 684 clear_work_bit(ctx); 685 ctx->state = MFCINST_FREE; 686 wake_up(&ctx->queue); 687 goto irq_cleanup_hw; 688 689 case S5P_MFC_R2H_CMD_SYS_INIT_RET: 690 case S5P_MFC_R2H_CMD_FW_STATUS_RET: 691 case S5P_MFC_R2H_CMD_SLEEP_RET: 692 case S5P_MFC_R2H_CMD_WAKEUP_RET: 693 if (ctx) 694 clear_work_bit(ctx); 695 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 696 wake_up_dev(dev, reason, err); 697 clear_bit(0, &dev->hw_lock); 698 clear_bit(0, &dev->enter_suspend); 699 break; 700 701 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: 702 s5p_mfc_handle_init_buffers(ctx, reason, err); 703 break; 704 705 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: 706 s5p_mfc_handle_stream_complete(ctx, reason, err); 707 break; 708 709 default: 710 mfc_debug(2, "Unknown int reason\n"); 711 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 712 } 713 mfc_debug_leave(); 714 return IRQ_HANDLED; 715irq_cleanup_hw: 716 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 717 ctx->int_type = reason; 718 ctx->int_err = err; 719 ctx->int_cond = 1; 720 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 721 mfc_err("Failed to unlock hw\n"); 722 723 s5p_mfc_clock_off(); 724 725 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 726 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 727 return IRQ_HANDLED; 728} 729 730/* Open an MFC node */ 731static int s5p_mfc_open(struct file *file) 732{ 733 struct s5p_mfc_dev *dev = video_drvdata(file); 734 struct s5p_mfc_ctx *ctx = NULL; 735 struct vb2_queue *q; 736 int ret = 0; 737 738 mfc_debug_enter(); 739 if (mutex_lock_interruptible(&dev->mfc_mutex)) 740 return -ERESTARTSYS; 741 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ 742 /* Allocate memory for context */ 743 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 744 if (!ctx) { 745 mfc_err("Not enough memory\n"); 746 ret = -ENOMEM; 747 goto err_alloc; 748 } 749 v4l2_fh_init(&ctx->fh, video_devdata(file)); 750 file->private_data = &ctx->fh; 751 v4l2_fh_add(&ctx->fh); 752 ctx->dev = dev; 753 INIT_LIST_HEAD(&ctx->src_queue); 754 INIT_LIST_HEAD(&ctx->dst_queue); 755 ctx->src_queue_cnt = 0; 756 ctx->dst_queue_cnt = 0; 757 /* Get context number */ 758 ctx->num = 0; 759 while (dev->ctx[ctx->num]) { 760 ctx->num++; 761 if (ctx->num >= MFC_NUM_CONTEXTS) { 762 mfc_err("Too many open contexts\n"); 763 ret = -EBUSY; 764 goto err_no_ctx; 765 } 766 } 767 /* Mark context as idle */ 768 clear_work_bit_irqsave(ctx); 769 dev->ctx[ctx->num] = ctx; 770 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 771 ctx->type = MFCINST_DECODER; 772 ctx->c_ops = get_dec_codec_ops(); 773 s5p_mfc_dec_init(ctx); 774 /* Setup ctrl handler */ 775 ret = s5p_mfc_dec_ctrls_setup(ctx); 776 if (ret) { 777 mfc_err("Failed to setup mfc controls\n"); 778 goto err_ctrls_setup; 779 } 780 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 781 ctx->type = MFCINST_ENCODER; 782 ctx->c_ops = get_enc_codec_ops(); 783 /* only for encoder */ 784 INIT_LIST_HEAD(&ctx->ref_queue); 785 ctx->ref_queue_cnt = 0; 786 s5p_mfc_enc_init(ctx); 787 /* Setup ctrl handler */ 788 ret = s5p_mfc_enc_ctrls_setup(ctx); 789 if (ret) { 790 mfc_err("Failed to setup mfc controls\n"); 791 goto err_ctrls_setup; 792 } 793 } else { 794 ret = -ENOENT; 795 goto err_bad_node; 796 } 797 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 798 ctx->inst_no = -1; 799 /* Load firmware if this is the first instance */ 800 if (dev->num_inst == 1) { 801 dev->watchdog_timer.expires = jiffies + 802 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 803 add_timer(&dev->watchdog_timer); 804 ret = s5p_mfc_power_on(); 805 if (ret < 0) { 806 mfc_err("power on failed\n"); 807 goto err_pwr_enable; 808 } 809 s5p_mfc_clock_on(); 810 ret = s5p_mfc_alloc_and_load_firmware(dev); 811 if (ret) 812 goto err_alloc_fw; 813 /* Init the FW */ 814 ret = s5p_mfc_init_hw(dev); 815 if (ret) 816 goto err_init_hw; 817 s5p_mfc_clock_off(); 818 } 819 /* Init videobuf2 queue for CAPTURE */ 820 q = &ctx->vq_dst; 821 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 822 q->drv_priv = &ctx->fh; 823 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 824 q->io_modes = VB2_MMAP; 825 q->ops = get_dec_queue_ops(); 826 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 827 q->io_modes = VB2_MMAP | VB2_USERPTR; 828 q->ops = get_enc_queue_ops(); 829 } else { 830 ret = -ENOENT; 831 goto err_queue_init; 832 } 833 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 834 ret = vb2_queue_init(q); 835 if (ret) { 836 mfc_err("Failed to initialize videobuf2 queue(capture)\n"); 837 goto err_queue_init; 838 } 839 /* Init videobuf2 queue for OUTPUT */ 840 q = &ctx->vq_src; 841 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 842 q->io_modes = VB2_MMAP; 843 q->drv_priv = &ctx->fh; 844 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 845 q->io_modes = VB2_MMAP; 846 q->ops = get_dec_queue_ops(); 847 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 848 q->io_modes = VB2_MMAP | VB2_USERPTR; 849 q->ops = get_enc_queue_ops(); 850 } else { 851 ret = -ENOENT; 852 goto err_queue_init; 853 } 854 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 855 ret = vb2_queue_init(q); 856 if (ret) { 857 mfc_err("Failed to initialize videobuf2 queue(output)\n"); 858 goto err_queue_init; 859 } 860 init_waitqueue_head(&ctx->queue); 861 mutex_unlock(&dev->mfc_mutex); 862 mfc_debug_leave(); 863 return ret; 864 /* Deinit when failure occured */ 865err_queue_init: 866err_init_hw: 867 s5p_mfc_release_firmware(dev); 868err_alloc_fw: 869 dev->ctx[ctx->num] = NULL; 870 del_timer_sync(&dev->watchdog_timer); 871 s5p_mfc_clock_off(); 872err_pwr_enable: 873 if (dev->num_inst == 1) { 874 if (s5p_mfc_power_off() < 0) 875 mfc_err("power off failed\n"); 876 s5p_mfc_release_firmware(dev); 877 } 878err_ctrls_setup: 879 s5p_mfc_dec_ctrls_delete(ctx); 880err_bad_node: 881err_no_ctx: 882 v4l2_fh_del(&ctx->fh); 883 v4l2_fh_exit(&ctx->fh); 884 kfree(ctx); 885err_alloc: 886 dev->num_inst--; 887 mutex_unlock(&dev->mfc_mutex); 888 mfc_debug_leave(); 889 return ret; 890} 891 892/* Release MFC context */ 893static int s5p_mfc_release(struct file *file) 894{ 895 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 896 struct s5p_mfc_dev *dev = ctx->dev; 897 898 mfc_debug_enter(); 899 mutex_lock(&dev->mfc_mutex); 900 s5p_mfc_clock_on(); 901 vb2_queue_release(&ctx->vq_src); 902 vb2_queue_release(&ctx->vq_dst); 903 /* Mark context as idle */ 904 clear_work_bit_irqsave(ctx); 905 /* If instance was initialised then 906 * return instance and free reosurces */ 907 if (ctx->inst_no != MFC_NO_INSTANCE_SET) { 908 mfc_debug(2, "Has to free instance\n"); 909 ctx->state = MFCINST_RETURN_INST; 910 set_work_bit_irqsave(ctx); 911 s5p_mfc_clean_ctx_int_flags(ctx); 912 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 913 /* Wait until instance is returned or timeout occured */ 914 if (s5p_mfc_wait_for_done_ctx 915 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) { 916 s5p_mfc_clock_off(); 917 mfc_err("Err returning instance\n"); 918 } 919 mfc_debug(2, "After free instance\n"); 920 /* Free resources */ 921 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); 922 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); 923 if (ctx->type == MFCINST_DECODER) 924 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, 925 ctx); 926 927 ctx->inst_no = MFC_NO_INSTANCE_SET; 928 } 929 /* hardware locking scheme */ 930 if (dev->curr_ctx == ctx->num) 931 clear_bit(0, &dev->hw_lock); 932 dev->num_inst--; 933 if (dev->num_inst == 0) { 934 mfc_debug(2, "Last instance - release firmware\n"); 935 /* reset <-> F/W release */ 936 s5p_mfc_reset(dev); 937 s5p_mfc_deinit_hw(dev); 938 s5p_mfc_release_firmware(dev); 939 del_timer_sync(&dev->watchdog_timer); 940 if (s5p_mfc_power_off() < 0) 941 mfc_err("Power off failed\n"); 942 } 943 mfc_debug(2, "Shutting down clock\n"); 944 s5p_mfc_clock_off(); 945 dev->ctx[ctx->num] = NULL; 946 s5p_mfc_dec_ctrls_delete(ctx); 947 v4l2_fh_del(&ctx->fh); 948 v4l2_fh_exit(&ctx->fh); 949 kfree(ctx); 950 mfc_debug_leave(); 951 mutex_unlock(&dev->mfc_mutex); 952 return 0; 953} 954 955/* Poll */ 956static unsigned int s5p_mfc_poll(struct file *file, 957 struct poll_table_struct *wait) 958{ 959 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 960 struct s5p_mfc_dev *dev = ctx->dev; 961 struct vb2_queue *src_q, *dst_q; 962 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; 963 unsigned int rc = 0; 964 unsigned long flags; 965 966 mutex_lock(&dev->mfc_mutex); 967 src_q = &ctx->vq_src; 968 dst_q = &ctx->vq_dst; 969 /* 970 * There has to be at least one buffer queued on each queued_list, which 971 * means either in driver already or waiting for driver to claim it 972 * and start processing. 973 */ 974 if ((!src_q->streaming || list_empty(&src_q->queued_list)) 975 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { 976 rc = POLLERR; 977 goto end; 978 } 979 mutex_unlock(&dev->mfc_mutex); 980 poll_wait(file, &ctx->fh.wait, wait); 981 poll_wait(file, &src_q->done_wq, wait); 982 poll_wait(file, &dst_q->done_wq, wait); 983 mutex_lock(&dev->mfc_mutex); 984 if (v4l2_event_pending(&ctx->fh)) 985 rc |= POLLPRI; 986 spin_lock_irqsave(&src_q->done_lock, flags); 987 if (!list_empty(&src_q->done_list)) 988 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, 989 done_entry); 990 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE 991 || src_vb->state == VB2_BUF_STATE_ERROR)) 992 rc |= POLLOUT | POLLWRNORM; 993 spin_unlock_irqrestore(&src_q->done_lock, flags); 994 spin_lock_irqsave(&dst_q->done_lock, flags); 995 if (!list_empty(&dst_q->done_list)) 996 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, 997 done_entry); 998 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE 999 || dst_vb->state == VB2_BUF_STATE_ERROR)) 1000 rc |= POLLIN | POLLRDNORM; 1001 spin_unlock_irqrestore(&dst_q->done_lock, flags); 1002end: 1003 mutex_unlock(&dev->mfc_mutex); 1004 return rc; 1005} 1006 1007/* Mmap */ 1008static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) 1009{ 1010 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 1011 struct s5p_mfc_dev *dev = ctx->dev; 1012 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 1013 int ret; 1014 1015 if (mutex_lock_interruptible(&dev->mfc_mutex)) 1016 return -ERESTARTSYS; 1017 if (offset < DST_QUEUE_OFF_BASE) { 1018 mfc_debug(2, "mmaping source\n"); 1019 ret = vb2_mmap(&ctx->vq_src, vma); 1020 } else { /* capture */ 1021 mfc_debug(2, "mmaping destination\n"); 1022 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); 1023 ret = vb2_mmap(&ctx->vq_dst, vma); 1024 } 1025 mutex_unlock(&dev->mfc_mutex); 1026 return ret; 1027} 1028 1029/* v4l2 ops */ 1030static const struct v4l2_file_operations s5p_mfc_fops = { 1031 .owner = THIS_MODULE, 1032 .open = s5p_mfc_open, 1033 .release = s5p_mfc_release, 1034 .poll = s5p_mfc_poll, 1035 .unlocked_ioctl = video_ioctl2, 1036 .mmap = s5p_mfc_mmap, 1037}; 1038 1039static int match_child(struct device *dev, void *data) 1040{ 1041 if (!dev_name(dev)) 1042 return 0; 1043 return !strcmp(dev_name(dev), (char *)data); 1044} 1045 1046/* MFC probe function */ 1047static int s5p_mfc_probe(struct platform_device *pdev) 1048{ 1049 struct s5p_mfc_dev *dev; 1050 struct video_device *vfd; 1051 struct resource *res; 1052 int ret; 1053 1054 pr_debug("%s++\n", __func__); 1055 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1056 if (!dev) { 1057 dev_err(&pdev->dev, "Not enough memory for MFC device\n"); 1058 return -ENOMEM; 1059 } 1060 1061 spin_lock_init(&dev->irqlock); 1062 spin_lock_init(&dev->condlock); 1063 dev->plat_dev = pdev; 1064 if (!dev->plat_dev) { 1065 dev_err(&pdev->dev, "No platform data specified\n"); 1066 return -ENODEV; 1067 } 1068 1069 ret = s5p_mfc_init_pm(dev); 1070 if (ret < 0) { 1071 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 1072 return ret; 1073 } 1074 1075 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1076 1077 dev->regs_base = devm_request_and_ioremap(&pdev->dev, res); 1078 if (dev->regs_base == NULL) { 1079 dev_err(&pdev->dev, "Failed to obtain io memory\n"); 1080 return -ENOENT; 1081 } 1082 1083 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1084 if (res == NULL) { 1085 dev_err(&pdev->dev, "failed to get irq resource\n"); 1086 ret = -ENOENT; 1087 goto err_res; 1088 } 1089 dev->irq = res->start; 1090 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, 1091 IRQF_DISABLED, pdev->name, dev); 1092 if (ret) { 1093 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); 1094 goto err_res; 1095 } 1096 1097 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, "s5p-mfc-l", 1098 match_child); 1099 if (!dev->mem_dev_l) { 1100 mfc_err("Mem child (L) device get failed\n"); 1101 ret = -ENODEV; 1102 goto err_res; 1103 } 1104 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, "s5p-mfc-r", 1105 match_child); 1106 if (!dev->mem_dev_r) { 1107 mfc_err("Mem child (R) device get failed\n"); 1108 ret = -ENODEV; 1109 goto err_res; 1110 } 1111 1112 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); 1113 if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) { 1114 ret = PTR_ERR(dev->alloc_ctx[0]); 1115 goto err_res; 1116 } 1117 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); 1118 if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) { 1119 ret = PTR_ERR(dev->alloc_ctx[1]); 1120 goto err_mem_init_ctx_1; 1121 } 1122 1123 mutex_init(&dev->mfc_mutex); 1124 1125 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 1126 if (ret) 1127 goto err_v4l2_dev_reg; 1128 init_waitqueue_head(&dev->queue); 1129 1130 /* decoder */ 1131 vfd = video_device_alloc(); 1132 if (!vfd) { 1133 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1134 ret = -ENOMEM; 1135 goto err_dec_alloc; 1136 } 1137 vfd->fops = &s5p_mfc_fops, 1138 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); 1139 vfd->release = video_device_release, 1140 vfd->lock = &dev->mfc_mutex; 1141 vfd->v4l2_dev = &dev->v4l2_dev; 1142 vfd->vfl_dir = VFL_DIR_M2M; 1143 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); 1144 dev->vfd_dec = vfd; 1145 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1146 if (ret) { 1147 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1148 video_device_release(vfd); 1149 goto err_dec_reg; 1150 } 1151 v4l2_info(&dev->v4l2_dev, 1152 "decoder registered as /dev/video%d\n", vfd->num); 1153 video_set_drvdata(vfd, dev); 1154 1155 /* encoder */ 1156 vfd = video_device_alloc(); 1157 if (!vfd) { 1158 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1159 ret = -ENOMEM; 1160 goto err_enc_alloc; 1161 } 1162 vfd->fops = &s5p_mfc_fops, 1163 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); 1164 vfd->release = video_device_release, 1165 vfd->lock = &dev->mfc_mutex; 1166 vfd->v4l2_dev = &dev->v4l2_dev; 1167 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); 1168 dev->vfd_enc = vfd; 1169 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1170 if (ret) { 1171 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1172 video_device_release(vfd); 1173 goto err_enc_reg; 1174 } 1175 v4l2_info(&dev->v4l2_dev, 1176 "encoder registered as /dev/video%d\n", vfd->num); 1177 video_set_drvdata(vfd, dev); 1178 platform_set_drvdata(pdev, dev); 1179 1180 dev->hw_lock = 0; 1181 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); 1182 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); 1183 atomic_set(&dev->watchdog_cnt, 0); 1184 init_timer(&dev->watchdog_timer); 1185 dev->watchdog_timer.data = (unsigned long)dev; 1186 dev->watchdog_timer.function = s5p_mfc_watchdog; 1187 1188 /* Initialize HW ops and commands based on MFC version */ 1189 s5p_mfc_init_hw_ops(dev); 1190 s5p_mfc_init_hw_cmds(dev); 1191 1192 pr_debug("%s--\n", __func__); 1193 return 0; 1194 1195/* Deinit MFC if probe had failed */ 1196err_enc_reg: 1197 video_device_release(dev->vfd_enc); 1198err_enc_alloc: 1199 video_unregister_device(dev->vfd_dec); 1200err_dec_reg: 1201 video_device_release(dev->vfd_dec); 1202err_dec_alloc: 1203 v4l2_device_unregister(&dev->v4l2_dev); 1204err_v4l2_dev_reg: 1205 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1206err_mem_init_ctx_1: 1207 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1208err_res: 1209 s5p_mfc_final_pm(dev); 1210 1211 pr_debug("%s-- with error\n", __func__); 1212 return ret; 1213 1214} 1215 1216/* Remove the driver */ 1217static int __devexit s5p_mfc_remove(struct platform_device *pdev) 1218{ 1219 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); 1220 1221 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); 1222 1223 del_timer_sync(&dev->watchdog_timer); 1224 flush_workqueue(dev->watchdog_workqueue); 1225 destroy_workqueue(dev->watchdog_workqueue); 1226 1227 video_unregister_device(dev->vfd_enc); 1228 video_unregister_device(dev->vfd_dec); 1229 v4l2_device_unregister(&dev->v4l2_dev); 1230 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1231 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1232 1233 s5p_mfc_final_pm(dev); 1234 return 0; 1235} 1236 1237#ifdef CONFIG_PM_SLEEP 1238 1239static int s5p_mfc_suspend(struct device *dev) 1240{ 1241 struct platform_device *pdev = to_platform_device(dev); 1242 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1243 int ret; 1244 1245 if (m_dev->num_inst == 0) 1246 return 0; 1247 1248 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { 1249 mfc_err("Error: going to suspend for a second time\n"); 1250 return -EIO; 1251 } 1252 1253 /* Check if we're processing then wait if it necessary. */ 1254 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { 1255 /* Try and lock the HW */ 1256 /* Wait on the interrupt waitqueue */ 1257 ret = wait_event_interruptible_timeout(m_dev->queue, 1258 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond, 1259 msecs_to_jiffies(MFC_INT_TIMEOUT)); 1260 1261 if (ret == 0) { 1262 mfc_err("Waiting for hardware to finish timed out\n"); 1263 return -EIO; 1264 } 1265 } 1266 1267 return s5p_mfc_sleep(m_dev); 1268} 1269 1270static int s5p_mfc_resume(struct device *dev) 1271{ 1272 struct platform_device *pdev = to_platform_device(dev); 1273 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1274 1275 if (m_dev->num_inst == 0) 1276 return 0; 1277 return s5p_mfc_wakeup(m_dev); 1278} 1279#endif 1280 1281#ifdef CONFIG_PM_RUNTIME 1282static int s5p_mfc_runtime_suspend(struct device *dev) 1283{ 1284 struct platform_device *pdev = to_platform_device(dev); 1285 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1286 1287 atomic_set(&m_dev->pm.power, 0); 1288 return 0; 1289} 1290 1291static int s5p_mfc_runtime_resume(struct device *dev) 1292{ 1293 struct platform_device *pdev = to_platform_device(dev); 1294 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1295 int pre_power; 1296 1297 if (!m_dev->alloc_ctx) 1298 return 0; 1299 pre_power = atomic_read(&m_dev->pm.power); 1300 atomic_set(&m_dev->pm.power, 1); 1301 return 0; 1302} 1303#endif 1304 1305/* Power management */ 1306static const struct dev_pm_ops s5p_mfc_pm_ops = { 1307 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) 1308 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, 1309 NULL) 1310}; 1311 1312static struct platform_driver s5p_mfc_driver = { 1313 .probe = s5p_mfc_probe, 1314 .remove = __devexit_p(s5p_mfc_remove), 1315 .driver = { 1316 .name = S5P_MFC_NAME, 1317 .owner = THIS_MODULE, 1318 .pm = &s5p_mfc_pm_ops 1319 }, 1320}; 1321 1322module_platform_driver(s5p_mfc_driver); 1323 1324MODULE_LICENSE("GPL"); 1325MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); 1326MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); 1327 1328