s5p_mfc.c revision 6a9c6f681257985468e4835bf9f911ec56482f02
1/* 2 * Samsung S5P Multi Format Codec v 5.1 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Kamil Debski, <k.debski@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22#include <media/v4l2-event.h> 23#include <linux/workqueue.h> 24#include <linux/of.h> 25#include <media/videobuf2-core.h> 26#include "s5p_mfc_common.h" 27#include "s5p_mfc_ctrl.h" 28#include "s5p_mfc_debug.h" 29#include "s5p_mfc_dec.h" 30#include "s5p_mfc_enc.h" 31#include "s5p_mfc_intr.h" 32#include "s5p_mfc_opr.h" 33#include "s5p_mfc_cmd.h" 34#include "s5p_mfc_pm.h" 35 36#define S5P_MFC_NAME "s5p-mfc" 37#define S5P_MFC_DEC_NAME "s5p-mfc-dec" 38#define S5P_MFC_ENC_NAME "s5p-mfc-enc" 39 40int debug; 41module_param(debug, int, S_IRUGO | S_IWUSR); 42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); 43 44/* Helper functions for interrupt processing */ 45 46/* Remove from hw execution round robin */ 47void clear_work_bit(struct s5p_mfc_ctx *ctx) 48{ 49 struct s5p_mfc_dev *dev = ctx->dev; 50 51 spin_lock(&dev->condlock); 52 __clear_bit(ctx->num, &dev->ctx_work_bits); 53 spin_unlock(&dev->condlock); 54} 55 56/* Add to hw execution round robin */ 57void set_work_bit(struct s5p_mfc_ctx *ctx) 58{ 59 struct s5p_mfc_dev *dev = ctx->dev; 60 61 spin_lock(&dev->condlock); 62 __set_bit(ctx->num, &dev->ctx_work_bits); 63 spin_unlock(&dev->condlock); 64} 65 66/* Remove from hw execution round robin */ 67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 68{ 69 struct s5p_mfc_dev *dev = ctx->dev; 70 unsigned long flags; 71 72 spin_lock_irqsave(&dev->condlock, flags); 73 __clear_bit(ctx->num, &dev->ctx_work_bits); 74 spin_unlock_irqrestore(&dev->condlock, flags); 75} 76 77/* Add to hw execution round robin */ 78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 79{ 80 struct s5p_mfc_dev *dev = ctx->dev; 81 unsigned long flags; 82 83 spin_lock_irqsave(&dev->condlock, flags); 84 __set_bit(ctx->num, &dev->ctx_work_bits); 85 spin_unlock_irqrestore(&dev->condlock, flags); 86} 87 88/* Wake up context wait_queue */ 89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, 90 unsigned int err) 91{ 92 ctx->int_cond = 1; 93 ctx->int_type = reason; 94 ctx->int_err = err; 95 wake_up(&ctx->queue); 96} 97 98/* Wake up device wait_queue */ 99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, 100 unsigned int err) 101{ 102 dev->int_cond = 1; 103 dev->int_type = reason; 104 dev->int_err = err; 105 wake_up(&dev->queue); 106} 107 108static void s5p_mfc_watchdog(unsigned long arg) 109{ 110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; 111 112 if (test_bit(0, &dev->hw_lock)) 113 atomic_inc(&dev->watchdog_cnt); 114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { 115 /* This means that hw is busy and no interrupts were 116 * generated by hw for the Nth time of running this 117 * watchdog timer. This usually means a serious hw 118 * error. Now it is time to kill all instances and 119 * reset the MFC. */ 120 mfc_err("Time out during waiting for HW\n"); 121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work); 122 } 123 dev->watchdog_timer.expires = jiffies + 124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 125 add_timer(&dev->watchdog_timer); 126} 127 128static void s5p_mfc_watchdog_worker(struct work_struct *work) 129{ 130 struct s5p_mfc_dev *dev; 131 struct s5p_mfc_ctx *ctx; 132 unsigned long flags; 133 int mutex_locked; 134 int i, ret; 135 136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work); 137 138 mfc_err("Driver timeout error handling\n"); 139 /* Lock the mutex that protects open and release. 140 * This is necessary as they may load and unload firmware. */ 141 mutex_locked = mutex_trylock(&dev->mfc_mutex); 142 if (!mutex_locked) 143 mfc_err("Error: some instance may be closing/opening\n"); 144 spin_lock_irqsave(&dev->irqlock, flags); 145 146 s5p_mfc_clock_off(); 147 148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) { 149 ctx = dev->ctx[i]; 150 if (!ctx) 151 continue; 152 ctx->state = MFCINST_ERROR; 153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 154 &ctx->vq_dst); 155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 156 &ctx->vq_src); 157 clear_work_bit(ctx); 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); 159 } 160 clear_bit(0, &dev->hw_lock); 161 spin_unlock_irqrestore(&dev->irqlock, flags); 162 /* Double check if there is at least one instance running. 163 * If no instance is in memory than no firmware should be present */ 164 if (dev->num_inst > 0) { 165 ret = s5p_mfc_reload_firmware(dev); 166 if (ret) { 167 mfc_err("Failed to reload FW\n"); 168 goto unlock; 169 } 170 s5p_mfc_clock_on(); 171 ret = s5p_mfc_init_hw(dev); 172 if (ret) 173 mfc_err("Failed to reinit FW\n"); 174 } 175unlock: 176 if (mutex_locked) 177 mutex_unlock(&dev->mfc_mutex); 178} 179 180static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) 181{ 182 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 183 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 184 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 185} 186 187static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) 188{ 189 struct s5p_mfc_buf *dst_buf; 190 struct s5p_mfc_dev *dev = ctx->dev; 191 192 ctx->state = MFCINST_FINISHED; 193 ctx->sequence++; 194 while (!list_empty(&ctx->dst_queue)) { 195 dst_buf = list_entry(ctx->dst_queue.next, 196 struct s5p_mfc_buf, list); 197 mfc_debug(2, "Cleaning up buffer: %d\n", 198 dst_buf->b->v4l2_buf.index); 199 vb2_set_plane_payload(dst_buf->b, 0, 0); 200 vb2_set_plane_payload(dst_buf->b, 1, 0); 201 list_del(&dst_buf->list); 202 ctx->dst_queue_cnt--; 203 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); 204 205 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == 206 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) 207 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 208 else 209 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; 210 211 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); 212 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); 213 } 214} 215 216static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) 217{ 218 struct s5p_mfc_dev *dev = ctx->dev; 219 struct s5p_mfc_buf *dst_buf, *src_buf; 220 size_t dec_y_addr; 221 unsigned int frame_type; 222 223 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); 224 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 225 226 /* Copy timestamp / timecode from decoded src to dst and set 227 appropriate flags */ 228 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 229 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 230 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { 231 dst_buf->b->v4l2_buf.timecode = 232 src_buf->b->v4l2_buf.timecode; 233 dst_buf->b->v4l2_buf.timestamp = 234 src_buf->b->v4l2_buf.timestamp; 235 dst_buf->b->v4l2_buf.flags &= 236 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; 237 dst_buf->b->v4l2_buf.flags |= 238 src_buf->b->v4l2_buf.flags 239 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; 240 switch (frame_type) { 241 case S5P_FIMV_DECODE_FRAME_I_FRAME: 242 dst_buf->b->v4l2_buf.flags |= 243 V4L2_BUF_FLAG_KEYFRAME; 244 break; 245 case S5P_FIMV_DECODE_FRAME_P_FRAME: 246 dst_buf->b->v4l2_buf.flags |= 247 V4L2_BUF_FLAG_PFRAME; 248 break; 249 case S5P_FIMV_DECODE_FRAME_B_FRAME: 250 dst_buf->b->v4l2_buf.flags |= 251 V4L2_BUF_FLAG_BFRAME; 252 break; 253 } 254 break; 255 } 256 } 257} 258 259static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) 260{ 261 struct s5p_mfc_dev *dev = ctx->dev; 262 struct s5p_mfc_buf *dst_buf; 263 size_t dspl_y_addr; 264 unsigned int frame_type; 265 266 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); 267 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx); 268 269 /* If frame is same as previous then skip and do not dequeue */ 270 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { 271 if (!ctx->after_packed_pb) 272 ctx->sequence++; 273 ctx->after_packed_pb = 0; 274 return; 275 } 276 ctx->sequence++; 277 /* The MFC returns address of the buffer, now we have to 278 * check which videobuf does it correspond to */ 279 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 280 /* Check if this is the buffer we're looking for */ 281 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { 282 list_del(&dst_buf->list); 283 ctx->dst_queue_cnt--; 284 dst_buf->b->v4l2_buf.sequence = ctx->sequence; 285 if (s5p_mfc_hw_call(dev->mfc_ops, 286 get_pic_type_top, ctx) == 287 s5p_mfc_hw_call(dev->mfc_ops, 288 get_pic_type_bot, ctx)) 289 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 290 else 291 dst_buf->b->v4l2_buf.field = 292 V4L2_FIELD_INTERLACED; 293 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); 294 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); 295 clear_bit(dst_buf->b->v4l2_buf.index, 296 &ctx->dec_dst_flag); 297 298 vb2_buffer_done(dst_buf->b, 299 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 300 301 break; 302 } 303 } 304} 305 306/* Handle frame decoding interrupt */ 307static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, 308 unsigned int reason, unsigned int err) 309{ 310 struct s5p_mfc_dev *dev = ctx->dev; 311 unsigned int dst_frame_status; 312 unsigned int dec_frame_status; 313 struct s5p_mfc_buf *src_buf; 314 unsigned long flags; 315 unsigned int res_change; 316 317 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 318 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 319 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev) 320 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 321 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 322 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) 323 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; 324 mfc_debug(2, "Frame Status: %x\n", dst_frame_status); 325 if (ctx->state == MFCINST_RES_CHANGE_INIT) 326 ctx->state = MFCINST_RES_CHANGE_FLUSH; 327 if (res_change == S5P_FIMV_RES_INCREASE || 328 res_change == S5P_FIMV_RES_DECREASE) { 329 ctx->state = MFCINST_RES_CHANGE_INIT; 330 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 331 wake_up_ctx(ctx, reason, err); 332 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 333 BUG(); 334 s5p_mfc_clock_off(); 335 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 336 return; 337 } 338 if (ctx->dpb_flush_flag) 339 ctx->dpb_flush_flag = 0; 340 341 spin_lock_irqsave(&dev->irqlock, flags); 342 /* All frames remaining in the buffer have been extracted */ 343 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { 344 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { 345 s5p_mfc_handle_frame_all_extracted(ctx); 346 ctx->state = MFCINST_RES_CHANGE_END; 347 goto leave_handle_frame; 348 } else { 349 s5p_mfc_handle_frame_all_extracted(ctx); 350 } 351 } 352 353 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) 354 s5p_mfc_handle_frame_copy_time(ctx); 355 356 /* A frame has been decoded and is in the buffer */ 357 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || 358 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { 359 s5p_mfc_handle_frame_new(ctx, err); 360 } else { 361 mfc_debug(2, "No frame decode\n"); 362 } 363 /* Mark source buffer as complete */ 364 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 365 && !list_empty(&ctx->src_queue)) { 366 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 367 list); 368 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, 369 get_consumed_stream, dev); 370 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && 371 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC && 372 ctx->consumed_stream + STUFF_BYTE < 373 src_buf->b->v4l2_planes[0].bytesused) { 374 /* Run MFC again on the same buffer */ 375 mfc_debug(2, "Running again the same buffer\n"); 376 ctx->after_packed_pb = 1; 377 } else { 378 mfc_debug(2, "MFC needs next buffer\n"); 379 ctx->consumed_stream = 0; 380 if (src_buf->flags & MFC_BUF_FLAG_EOS) 381 ctx->state = MFCINST_FINISHING; 382 list_del(&src_buf->list); 383 ctx->src_queue_cnt--; 384 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) 385 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); 386 else 387 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); 388 } 389 } 390leave_handle_frame: 391 spin_unlock_irqrestore(&dev->irqlock, flags); 392 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 393 || ctx->dst_queue_cnt < ctx->pb_count) 394 clear_work_bit(ctx); 395 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 396 wake_up_ctx(ctx, reason, err); 397 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 398 BUG(); 399 s5p_mfc_clock_off(); 400 /* if suspending, wake up device and do not try_run again*/ 401 if (test_bit(0, &dev->enter_suspend)) 402 wake_up_dev(dev, reason, err); 403 else 404 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 405} 406 407/* Error handling for interrupt */ 408static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, 409 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) 410{ 411 unsigned long flags; 412 413 mfc_err("Interrupt Error: %08x\n", err); 414 415 if (ctx != NULL) { 416 /* Error recovery is dependent on the state of context */ 417 switch (ctx->state) { 418 case MFCINST_RES_CHANGE_INIT: 419 case MFCINST_RES_CHANGE_FLUSH: 420 case MFCINST_RES_CHANGE_END: 421 case MFCINST_FINISHING: 422 case MFCINST_FINISHED: 423 case MFCINST_RUNNING: 424 /* It is highly probable that an error occurred 425 * while decoding a frame */ 426 clear_work_bit(ctx); 427 ctx->state = MFCINST_ERROR; 428 /* Mark all dst buffers as having an error */ 429 spin_lock_irqsave(&dev->irqlock, flags); 430 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 431 &ctx->dst_queue, &ctx->vq_dst); 432 /* Mark all src buffers as having an error */ 433 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 434 &ctx->src_queue, &ctx->vq_src); 435 spin_unlock_irqrestore(&dev->irqlock, flags); 436 wake_up_ctx(ctx, reason, err); 437 break; 438 default: 439 clear_work_bit(ctx); 440 ctx->state = MFCINST_ERROR; 441 wake_up_ctx(ctx, reason, err); 442 break; 443 } 444 } 445 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 446 BUG(); 447 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 448 s5p_mfc_clock_off(); 449 wake_up_dev(dev, reason, err); 450 return; 451} 452 453/* Header parsing interrupt handling */ 454static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 455 unsigned int reason, unsigned int err) 456{ 457 struct s5p_mfc_dev *dev; 458 459 if (ctx == NULL) 460 return; 461 dev = ctx->dev; 462 if (ctx->c_ops->post_seq_start) { 463 if (ctx->c_ops->post_seq_start(ctx)) 464 mfc_err("post_seq_start() failed\n"); 465 } else { 466 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, 467 dev); 468 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 469 dev); 470 471 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); 472 473 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 474 dev); 475 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, 476 dev); 477 if (ctx->img_width == 0 || ctx->img_height == 0) 478 ctx->state = MFCINST_ERROR; 479 else 480 ctx->state = MFCINST_HEAD_PARSED; 481 482 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 483 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && 484 !list_empty(&ctx->src_queue)) { 485 struct s5p_mfc_buf *src_buf; 486 src_buf = list_entry(ctx->src_queue.next, 487 struct s5p_mfc_buf, list); 488 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, 489 dev) < 490 src_buf->b->v4l2_planes[0].bytesused) 491 ctx->head_processed = 0; 492 else 493 ctx->head_processed = 1; 494 } else { 495 ctx->head_processed = 1; 496 } 497 } 498 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 499 clear_work_bit(ctx); 500 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 501 BUG(); 502 s5p_mfc_clock_off(); 503 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 504 wake_up_ctx(ctx, reason, err); 505} 506 507/* Header parsing interrupt handling */ 508static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, 509 unsigned int reason, unsigned int err) 510{ 511 struct s5p_mfc_buf *src_buf; 512 struct s5p_mfc_dev *dev; 513 unsigned long flags; 514 515 if (ctx == NULL) 516 return; 517 dev = ctx->dev; 518 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 519 ctx->int_type = reason; 520 ctx->int_err = err; 521 ctx->int_cond = 1; 522 clear_work_bit(ctx); 523 if (err == 0) { 524 ctx->state = MFCINST_RUNNING; 525 if (!ctx->dpb_flush_flag && ctx->head_processed) { 526 spin_lock_irqsave(&dev->irqlock, flags); 527 if (!list_empty(&ctx->src_queue)) { 528 src_buf = list_entry(ctx->src_queue.next, 529 struct s5p_mfc_buf, list); 530 list_del(&src_buf->list); 531 ctx->src_queue_cnt--; 532 vb2_buffer_done(src_buf->b, 533 VB2_BUF_STATE_DONE); 534 } 535 spin_unlock_irqrestore(&dev->irqlock, flags); 536 } else { 537 ctx->dpb_flush_flag = 0; 538 } 539 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 540 BUG(); 541 542 s5p_mfc_clock_off(); 543 544 wake_up(&ctx->queue); 545 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 546 } else { 547 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 548 BUG(); 549 550 s5p_mfc_clock_off(); 551 552 wake_up(&ctx->queue); 553 } 554} 555 556static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, 557 unsigned int reason, unsigned int err) 558{ 559 struct s5p_mfc_dev *dev = ctx->dev; 560 struct s5p_mfc_buf *mb_entry; 561 562 mfc_debug(2, "Stream completed\n"); 563 564 s5p_mfc_clear_int_flags(dev); 565 ctx->int_type = reason; 566 ctx->int_err = err; 567 ctx->state = MFCINST_FINISHED; 568 569 spin_lock(&dev->irqlock); 570 if (!list_empty(&ctx->dst_queue)) { 571 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, 572 list); 573 list_del(&mb_entry->list); 574 ctx->dst_queue_cnt--; 575 vb2_set_plane_payload(mb_entry->b, 0, 0); 576 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE); 577 } 578 spin_unlock(&dev->irqlock); 579 580 clear_work_bit(ctx); 581 582 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); 583 584 s5p_mfc_clock_off(); 585 wake_up(&ctx->queue); 586 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 587} 588 589/* Interrupt processing */ 590static irqreturn_t s5p_mfc_irq(int irq, void *priv) 591{ 592 struct s5p_mfc_dev *dev = priv; 593 struct s5p_mfc_ctx *ctx; 594 unsigned int reason; 595 unsigned int err; 596 597 mfc_debug_enter(); 598 /* Reset the timeout watchdog */ 599 atomic_set(&dev->watchdog_cnt, 0); 600 ctx = dev->ctx[dev->curr_ctx]; 601 /* Get the reason of interrupt and the error code */ 602 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); 603 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); 604 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); 605 switch (reason) { 606 case S5P_MFC_R2H_CMD_ERR_RET: 607 /* An error has occurred */ 608 if (ctx->state == MFCINST_RUNNING && 609 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= 610 dev->warn_start) 611 s5p_mfc_handle_frame(ctx, reason, err); 612 else 613 s5p_mfc_handle_error(dev, ctx, reason, err); 614 clear_bit(0, &dev->enter_suspend); 615 break; 616 617 case S5P_MFC_R2H_CMD_SLICE_DONE_RET: 618 case S5P_MFC_R2H_CMD_FIELD_DONE_RET: 619 case S5P_MFC_R2H_CMD_FRAME_DONE_RET: 620 if (ctx->c_ops->post_frame_start) { 621 if (ctx->c_ops->post_frame_start(ctx)) 622 mfc_err("post_frame_start() failed\n"); 623 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 624 wake_up_ctx(ctx, reason, err); 625 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 626 BUG(); 627 s5p_mfc_clock_off(); 628 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 629 } else { 630 s5p_mfc_handle_frame(ctx, reason, err); 631 } 632 break; 633 634 case S5P_MFC_R2H_CMD_SEQ_DONE_RET: 635 s5p_mfc_handle_seq_done(ctx, reason, err); 636 break; 637 638 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: 639 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); 640 ctx->state = MFCINST_GOT_INST; 641 clear_work_bit(ctx); 642 wake_up(&ctx->queue); 643 goto irq_cleanup_hw; 644 645 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: 646 clear_work_bit(ctx); 647 ctx->inst_no = MFC_NO_INSTANCE_SET; 648 ctx->state = MFCINST_FREE; 649 wake_up(&ctx->queue); 650 goto irq_cleanup_hw; 651 652 case S5P_MFC_R2H_CMD_SYS_INIT_RET: 653 case S5P_MFC_R2H_CMD_FW_STATUS_RET: 654 case S5P_MFC_R2H_CMD_SLEEP_RET: 655 case S5P_MFC_R2H_CMD_WAKEUP_RET: 656 if (ctx) 657 clear_work_bit(ctx); 658 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 659 wake_up_dev(dev, reason, err); 660 clear_bit(0, &dev->hw_lock); 661 clear_bit(0, &dev->enter_suspend); 662 break; 663 664 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: 665 s5p_mfc_handle_init_buffers(ctx, reason, err); 666 break; 667 668 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: 669 s5p_mfc_handle_stream_complete(ctx, reason, err); 670 break; 671 672 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET: 673 clear_work_bit(ctx); 674 ctx->state = MFCINST_RUNNING; 675 wake_up(&ctx->queue); 676 goto irq_cleanup_hw; 677 678 default: 679 mfc_debug(2, "Unknown int reason\n"); 680 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 681 } 682 mfc_debug_leave(); 683 return IRQ_HANDLED; 684irq_cleanup_hw: 685 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 686 ctx->int_type = reason; 687 ctx->int_err = err; 688 ctx->int_cond = 1; 689 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 690 mfc_err("Failed to unlock hw\n"); 691 692 s5p_mfc_clock_off(); 693 694 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 695 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 696 return IRQ_HANDLED; 697} 698 699/* Open an MFC node */ 700static int s5p_mfc_open(struct file *file) 701{ 702 struct video_device *vdev = video_devdata(file); 703 struct s5p_mfc_dev *dev = video_drvdata(file); 704 struct s5p_mfc_ctx *ctx = NULL; 705 struct vb2_queue *q; 706 int ret = 0; 707 708 mfc_debug_enter(); 709 if (mutex_lock_interruptible(&dev->mfc_mutex)) 710 return -ERESTARTSYS; 711 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ 712 /* Allocate memory for context */ 713 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 714 if (!ctx) { 715 mfc_err("Not enough memory\n"); 716 ret = -ENOMEM; 717 goto err_alloc; 718 } 719 v4l2_fh_init(&ctx->fh, video_devdata(file)); 720 file->private_data = &ctx->fh; 721 v4l2_fh_add(&ctx->fh); 722 ctx->dev = dev; 723 INIT_LIST_HEAD(&ctx->src_queue); 724 INIT_LIST_HEAD(&ctx->dst_queue); 725 ctx->src_queue_cnt = 0; 726 ctx->dst_queue_cnt = 0; 727 /* Get context number */ 728 ctx->num = 0; 729 while (dev->ctx[ctx->num]) { 730 ctx->num++; 731 if (ctx->num >= MFC_NUM_CONTEXTS) { 732 mfc_err("Too many open contexts\n"); 733 ret = -EBUSY; 734 goto err_no_ctx; 735 } 736 } 737 /* Mark context as idle */ 738 clear_work_bit_irqsave(ctx); 739 dev->ctx[ctx->num] = ctx; 740 if (vdev == dev->vfd_dec) { 741 ctx->type = MFCINST_DECODER; 742 ctx->c_ops = get_dec_codec_ops(); 743 s5p_mfc_dec_init(ctx); 744 /* Setup ctrl handler */ 745 ret = s5p_mfc_dec_ctrls_setup(ctx); 746 if (ret) { 747 mfc_err("Failed to setup mfc controls\n"); 748 goto err_ctrls_setup; 749 } 750 } else if (vdev == dev->vfd_enc) { 751 ctx->type = MFCINST_ENCODER; 752 ctx->c_ops = get_enc_codec_ops(); 753 /* only for encoder */ 754 INIT_LIST_HEAD(&ctx->ref_queue); 755 ctx->ref_queue_cnt = 0; 756 s5p_mfc_enc_init(ctx); 757 /* Setup ctrl handler */ 758 ret = s5p_mfc_enc_ctrls_setup(ctx); 759 if (ret) { 760 mfc_err("Failed to setup mfc controls\n"); 761 goto err_ctrls_setup; 762 } 763 } else { 764 ret = -ENOENT; 765 goto err_bad_node; 766 } 767 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 768 ctx->inst_no = MFC_NO_INSTANCE_SET; 769 /* Load firmware if this is the first instance */ 770 if (dev->num_inst == 1) { 771 dev->watchdog_timer.expires = jiffies + 772 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 773 add_timer(&dev->watchdog_timer); 774 ret = s5p_mfc_power_on(); 775 if (ret < 0) { 776 mfc_err("power on failed\n"); 777 goto err_pwr_enable; 778 } 779 s5p_mfc_clock_on(); 780 ret = s5p_mfc_load_firmware(dev); 781 if (ret) { 782 s5p_mfc_clock_off(); 783 goto err_load_fw; 784 } 785 /* Init the FW */ 786 ret = s5p_mfc_init_hw(dev); 787 s5p_mfc_clock_off(); 788 if (ret) 789 goto err_init_hw; 790 } 791 /* Init videobuf2 queue for CAPTURE */ 792 q = &ctx->vq_dst; 793 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 794 q->drv_priv = &ctx->fh; 795 if (vdev == dev->vfd_dec) { 796 q->io_modes = VB2_MMAP; 797 q->ops = get_dec_queue_ops(); 798 } else if (vdev == dev->vfd_enc) { 799 q->io_modes = VB2_MMAP | VB2_USERPTR; 800 q->ops = get_enc_queue_ops(); 801 } else { 802 ret = -ENOENT; 803 goto err_queue_init; 804 } 805 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 806 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 807 ret = vb2_queue_init(q); 808 if (ret) { 809 mfc_err("Failed to initialize videobuf2 queue(capture)\n"); 810 goto err_queue_init; 811 } 812 /* Init videobuf2 queue for OUTPUT */ 813 q = &ctx->vq_src; 814 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 815 q->io_modes = VB2_MMAP; 816 q->drv_priv = &ctx->fh; 817 if (vdev == dev->vfd_dec) { 818 q->io_modes = VB2_MMAP; 819 q->ops = get_dec_queue_ops(); 820 } else if (vdev == dev->vfd_enc) { 821 q->io_modes = VB2_MMAP | VB2_USERPTR; 822 q->ops = get_enc_queue_ops(); 823 } else { 824 ret = -ENOENT; 825 goto err_queue_init; 826 } 827 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 828 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 829 ret = vb2_queue_init(q); 830 if (ret) { 831 mfc_err("Failed to initialize videobuf2 queue(output)\n"); 832 goto err_queue_init; 833 } 834 init_waitqueue_head(&ctx->queue); 835 mutex_unlock(&dev->mfc_mutex); 836 mfc_debug_leave(); 837 return ret; 838 /* Deinit when failure occurred */ 839err_queue_init: 840 if (dev->num_inst == 1) 841 s5p_mfc_deinit_hw(dev); 842err_init_hw: 843err_load_fw: 844err_pwr_enable: 845 if (dev->num_inst == 1) { 846 if (s5p_mfc_power_off() < 0) 847 mfc_err("power off failed\n"); 848 del_timer_sync(&dev->watchdog_timer); 849 } 850err_ctrls_setup: 851 s5p_mfc_dec_ctrls_delete(ctx); 852err_bad_node: 853 dev->ctx[ctx->num] = NULL; 854err_no_ctx: 855 v4l2_fh_del(&ctx->fh); 856 v4l2_fh_exit(&ctx->fh); 857 kfree(ctx); 858err_alloc: 859 dev->num_inst--; 860 mutex_unlock(&dev->mfc_mutex); 861 mfc_debug_leave(); 862 return ret; 863} 864 865/* Release MFC context */ 866static int s5p_mfc_release(struct file *file) 867{ 868 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 869 struct s5p_mfc_dev *dev = ctx->dev; 870 871 mfc_debug_enter(); 872 mutex_lock(&dev->mfc_mutex); 873 s5p_mfc_clock_on(); 874 vb2_queue_release(&ctx->vq_src); 875 vb2_queue_release(&ctx->vq_dst); 876 /* Mark context as idle */ 877 clear_work_bit_irqsave(ctx); 878 /* If instance was initialised and not yet freed, 879 * return instance and free resources */ 880 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) { 881 mfc_debug(2, "Has to free instance\n"); 882 s5p_mfc_close_mfc_inst(dev, ctx); 883 } 884 /* hardware locking scheme */ 885 if (dev->curr_ctx == ctx->num) 886 clear_bit(0, &dev->hw_lock); 887 dev->num_inst--; 888 if (dev->num_inst == 0) { 889 mfc_debug(2, "Last instance\n"); 890 s5p_mfc_deinit_hw(dev); 891 del_timer_sync(&dev->watchdog_timer); 892 if (s5p_mfc_power_off() < 0) 893 mfc_err("Power off failed\n"); 894 } 895 mfc_debug(2, "Shutting down clock\n"); 896 s5p_mfc_clock_off(); 897 dev->ctx[ctx->num] = NULL; 898 s5p_mfc_dec_ctrls_delete(ctx); 899 v4l2_fh_del(&ctx->fh); 900 v4l2_fh_exit(&ctx->fh); 901 kfree(ctx); 902 mfc_debug_leave(); 903 mutex_unlock(&dev->mfc_mutex); 904 return 0; 905} 906 907/* Poll */ 908static unsigned int s5p_mfc_poll(struct file *file, 909 struct poll_table_struct *wait) 910{ 911 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 912 struct s5p_mfc_dev *dev = ctx->dev; 913 struct vb2_queue *src_q, *dst_q; 914 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; 915 unsigned int rc = 0; 916 unsigned long flags; 917 918 mutex_lock(&dev->mfc_mutex); 919 src_q = &ctx->vq_src; 920 dst_q = &ctx->vq_dst; 921 /* 922 * There has to be at least one buffer queued on each queued_list, which 923 * means either in driver already or waiting for driver to claim it 924 * and start processing. 925 */ 926 if ((!src_q->streaming || list_empty(&src_q->queued_list)) 927 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { 928 rc = POLLERR; 929 goto end; 930 } 931 mutex_unlock(&dev->mfc_mutex); 932 poll_wait(file, &ctx->fh.wait, wait); 933 poll_wait(file, &src_q->done_wq, wait); 934 poll_wait(file, &dst_q->done_wq, wait); 935 mutex_lock(&dev->mfc_mutex); 936 if (v4l2_event_pending(&ctx->fh)) 937 rc |= POLLPRI; 938 spin_lock_irqsave(&src_q->done_lock, flags); 939 if (!list_empty(&src_q->done_list)) 940 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, 941 done_entry); 942 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE 943 || src_vb->state == VB2_BUF_STATE_ERROR)) 944 rc |= POLLOUT | POLLWRNORM; 945 spin_unlock_irqrestore(&src_q->done_lock, flags); 946 spin_lock_irqsave(&dst_q->done_lock, flags); 947 if (!list_empty(&dst_q->done_list)) 948 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, 949 done_entry); 950 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE 951 || dst_vb->state == VB2_BUF_STATE_ERROR)) 952 rc |= POLLIN | POLLRDNORM; 953 spin_unlock_irqrestore(&dst_q->done_lock, flags); 954end: 955 mutex_unlock(&dev->mfc_mutex); 956 return rc; 957} 958 959/* Mmap */ 960static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) 961{ 962 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 963 struct s5p_mfc_dev *dev = ctx->dev; 964 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 965 int ret; 966 967 if (mutex_lock_interruptible(&dev->mfc_mutex)) 968 return -ERESTARTSYS; 969 if (offset < DST_QUEUE_OFF_BASE) { 970 mfc_debug(2, "mmaping source\n"); 971 ret = vb2_mmap(&ctx->vq_src, vma); 972 } else { /* capture */ 973 mfc_debug(2, "mmaping destination\n"); 974 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); 975 ret = vb2_mmap(&ctx->vq_dst, vma); 976 } 977 mutex_unlock(&dev->mfc_mutex); 978 return ret; 979} 980 981/* v4l2 ops */ 982static const struct v4l2_file_operations s5p_mfc_fops = { 983 .owner = THIS_MODULE, 984 .open = s5p_mfc_open, 985 .release = s5p_mfc_release, 986 .poll = s5p_mfc_poll, 987 .unlocked_ioctl = video_ioctl2, 988 .mmap = s5p_mfc_mmap, 989}; 990 991static int match_child(struct device *dev, void *data) 992{ 993 if (!dev_name(dev)) 994 return 0; 995 return !strcmp(dev_name(dev), (char *)data); 996} 997 998static void *mfc_get_drv_data(struct platform_device *pdev); 999 1000static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev) 1001{ 1002 unsigned int mem_info[2] = { }; 1003 1004 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev, 1005 sizeof(struct device), GFP_KERNEL); 1006 if (!dev->mem_dev_l) { 1007 mfc_err("Not enough memory\n"); 1008 return -ENOMEM; 1009 } 1010 device_initialize(dev->mem_dev_l); 1011 of_property_read_u32_array(dev->plat_dev->dev.of_node, 1012 "samsung,mfc-l", mem_info, 2); 1013 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0], 1014 mem_info[0], mem_info[1], 1015 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1016 mfc_err("Failed to declare coherent memory for\n" 1017 "MFC device\n"); 1018 return -ENOMEM; 1019 } 1020 1021 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev, 1022 sizeof(struct device), GFP_KERNEL); 1023 if (!dev->mem_dev_r) { 1024 mfc_err("Not enough memory\n"); 1025 return -ENOMEM; 1026 } 1027 device_initialize(dev->mem_dev_r); 1028 of_property_read_u32_array(dev->plat_dev->dev.of_node, 1029 "samsung,mfc-r", mem_info, 2); 1030 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0], 1031 mem_info[0], mem_info[1], 1032 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1033 pr_err("Failed to declare coherent memory for\n" 1034 "MFC device\n"); 1035 return -ENOMEM; 1036 } 1037 return 0; 1038} 1039 1040/* MFC probe function */ 1041static int s5p_mfc_probe(struct platform_device *pdev) 1042{ 1043 struct s5p_mfc_dev *dev; 1044 struct video_device *vfd; 1045 struct resource *res; 1046 int ret; 1047 1048 pr_debug("%s++\n", __func__); 1049 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1050 if (!dev) { 1051 dev_err(&pdev->dev, "Not enough memory for MFC device\n"); 1052 return -ENOMEM; 1053 } 1054 1055 spin_lock_init(&dev->irqlock); 1056 spin_lock_init(&dev->condlock); 1057 dev->plat_dev = pdev; 1058 if (!dev->plat_dev) { 1059 dev_err(&pdev->dev, "No platform data specified\n"); 1060 return -ENODEV; 1061 } 1062 1063 dev->variant = mfc_get_drv_data(pdev); 1064 1065 ret = s5p_mfc_init_pm(dev); 1066 if (ret < 0) { 1067 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 1068 return ret; 1069 } 1070 1071 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1072 1073 dev->regs_base = devm_ioremap_resource(&pdev->dev, res); 1074 if (IS_ERR(dev->regs_base)) 1075 return PTR_ERR(dev->regs_base); 1076 1077 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1078 if (res == NULL) { 1079 dev_err(&pdev->dev, "failed to get irq resource\n"); 1080 ret = -ENOENT; 1081 goto err_res; 1082 } 1083 dev->irq = res->start; 1084 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, 1085 0, pdev->name, dev); 1086 if (ret) { 1087 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); 1088 goto err_res; 1089 } 1090 1091 if (pdev->dev.of_node) { 1092 ret = s5p_mfc_alloc_memdevs(dev); 1093 if (ret < 0) 1094 goto err_res; 1095 } else { 1096 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, 1097 "s5p-mfc-l", match_child); 1098 if (!dev->mem_dev_l) { 1099 mfc_err("Mem child (L) device get failed\n"); 1100 ret = -ENODEV; 1101 goto err_res; 1102 } 1103 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, 1104 "s5p-mfc-r", match_child); 1105 if (!dev->mem_dev_r) { 1106 mfc_err("Mem child (R) device get failed\n"); 1107 ret = -ENODEV; 1108 goto err_res; 1109 } 1110 } 1111 1112 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); 1113 if (IS_ERR(dev->alloc_ctx[0])) { 1114 ret = PTR_ERR(dev->alloc_ctx[0]); 1115 goto err_res; 1116 } 1117 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); 1118 if (IS_ERR(dev->alloc_ctx[1])) { 1119 ret = PTR_ERR(dev->alloc_ctx[1]); 1120 goto err_mem_init_ctx_1; 1121 } 1122 1123 mutex_init(&dev->mfc_mutex); 1124 1125 ret = s5p_mfc_alloc_firmware(dev); 1126 if (ret) 1127 goto err_alloc_fw; 1128 1129 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 1130 if (ret) 1131 goto err_v4l2_dev_reg; 1132 init_waitqueue_head(&dev->queue); 1133 1134 /* decoder */ 1135 vfd = video_device_alloc(); 1136 if (!vfd) { 1137 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1138 ret = -ENOMEM; 1139 goto err_dec_alloc; 1140 } 1141 vfd->fops = &s5p_mfc_fops; 1142 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); 1143 vfd->release = video_device_release; 1144 vfd->lock = &dev->mfc_mutex; 1145 vfd->v4l2_dev = &dev->v4l2_dev; 1146 vfd->vfl_dir = VFL_DIR_M2M; 1147 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); 1148 dev->vfd_dec = vfd; 1149 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1150 if (ret) { 1151 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1152 video_device_release(vfd); 1153 goto err_dec_reg; 1154 } 1155 v4l2_info(&dev->v4l2_dev, 1156 "decoder registered as /dev/video%d\n", vfd->num); 1157 video_set_drvdata(vfd, dev); 1158 1159 /* encoder */ 1160 vfd = video_device_alloc(); 1161 if (!vfd) { 1162 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1163 ret = -ENOMEM; 1164 goto err_enc_alloc; 1165 } 1166 vfd->fops = &s5p_mfc_fops; 1167 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); 1168 vfd->release = video_device_release; 1169 vfd->lock = &dev->mfc_mutex; 1170 vfd->v4l2_dev = &dev->v4l2_dev; 1171 vfd->vfl_dir = VFL_DIR_M2M; 1172 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); 1173 dev->vfd_enc = vfd; 1174 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1175 if (ret) { 1176 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1177 video_device_release(vfd); 1178 goto err_enc_reg; 1179 } 1180 v4l2_info(&dev->v4l2_dev, 1181 "encoder registered as /dev/video%d\n", vfd->num); 1182 video_set_drvdata(vfd, dev); 1183 platform_set_drvdata(pdev, dev); 1184 1185 dev->hw_lock = 0; 1186 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); 1187 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); 1188 atomic_set(&dev->watchdog_cnt, 0); 1189 init_timer(&dev->watchdog_timer); 1190 dev->watchdog_timer.data = (unsigned long)dev; 1191 dev->watchdog_timer.function = s5p_mfc_watchdog; 1192 1193 /* Initialize HW ops and commands based on MFC version */ 1194 s5p_mfc_init_hw_ops(dev); 1195 s5p_mfc_init_hw_cmds(dev); 1196 s5p_mfc_init_regs(dev); 1197 1198 pr_debug("%s--\n", __func__); 1199 return 0; 1200 1201/* Deinit MFC if probe had failed */ 1202err_enc_reg: 1203 video_device_release(dev->vfd_enc); 1204err_enc_alloc: 1205 video_unregister_device(dev->vfd_dec); 1206err_dec_reg: 1207 video_device_release(dev->vfd_dec); 1208err_dec_alloc: 1209 v4l2_device_unregister(&dev->v4l2_dev); 1210err_v4l2_dev_reg: 1211 s5p_mfc_release_firmware(dev); 1212err_alloc_fw: 1213 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1214err_mem_init_ctx_1: 1215 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1216err_res: 1217 s5p_mfc_final_pm(dev); 1218 1219 pr_debug("%s-- with error\n", __func__); 1220 return ret; 1221 1222} 1223 1224/* Remove the driver */ 1225static int s5p_mfc_remove(struct platform_device *pdev) 1226{ 1227 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); 1228 1229 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); 1230 1231 del_timer_sync(&dev->watchdog_timer); 1232 flush_workqueue(dev->watchdog_workqueue); 1233 destroy_workqueue(dev->watchdog_workqueue); 1234 1235 video_unregister_device(dev->vfd_enc); 1236 video_unregister_device(dev->vfd_dec); 1237 v4l2_device_unregister(&dev->v4l2_dev); 1238 s5p_mfc_release_firmware(dev); 1239 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1240 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1241 if (pdev->dev.of_node) { 1242 put_device(dev->mem_dev_l); 1243 put_device(dev->mem_dev_r); 1244 } 1245 1246 s5p_mfc_final_pm(dev); 1247 return 0; 1248} 1249 1250#ifdef CONFIG_PM_SLEEP 1251 1252static int s5p_mfc_suspend(struct device *dev) 1253{ 1254 struct platform_device *pdev = to_platform_device(dev); 1255 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1256 int ret; 1257 1258 if (m_dev->num_inst == 0) 1259 return 0; 1260 1261 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { 1262 mfc_err("Error: going to suspend for a second time\n"); 1263 return -EIO; 1264 } 1265 1266 /* Check if we're processing then wait if it necessary. */ 1267 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { 1268 /* Try and lock the HW */ 1269 /* Wait on the interrupt waitqueue */ 1270 ret = wait_event_interruptible_timeout(m_dev->queue, 1271 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT)); 1272 if (ret == 0) { 1273 mfc_err("Waiting for hardware to finish timed out\n"); 1274 return -EIO; 1275 } 1276 } 1277 1278 return s5p_mfc_sleep(m_dev); 1279} 1280 1281static int s5p_mfc_resume(struct device *dev) 1282{ 1283 struct platform_device *pdev = to_platform_device(dev); 1284 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1285 1286 if (m_dev->num_inst == 0) 1287 return 0; 1288 return s5p_mfc_wakeup(m_dev); 1289} 1290#endif 1291 1292#ifdef CONFIG_PM_RUNTIME 1293static int s5p_mfc_runtime_suspend(struct device *dev) 1294{ 1295 struct platform_device *pdev = to_platform_device(dev); 1296 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1297 1298 atomic_set(&m_dev->pm.power, 0); 1299 return 0; 1300} 1301 1302static int s5p_mfc_runtime_resume(struct device *dev) 1303{ 1304 struct platform_device *pdev = to_platform_device(dev); 1305 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1306 int pre_power; 1307 1308 if (!m_dev->alloc_ctx) 1309 return 0; 1310 pre_power = atomic_read(&m_dev->pm.power); 1311 atomic_set(&m_dev->pm.power, 1); 1312 return 0; 1313} 1314#endif 1315 1316/* Power management */ 1317static const struct dev_pm_ops s5p_mfc_pm_ops = { 1318 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) 1319 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, 1320 NULL) 1321}; 1322 1323struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { 1324 .h264_ctx = MFC_H264_CTX_BUF_SIZE, 1325 .non_h264_ctx = MFC_CTX_BUF_SIZE, 1326 .dsc = DESC_BUF_SIZE, 1327 .shm = SHARED_BUF_SIZE, 1328}; 1329 1330struct s5p_mfc_buf_size buf_size_v5 = { 1331 .fw = MAX_FW_SIZE, 1332 .cpb = MAX_CPB_SIZE, 1333 .priv = &mfc_buf_size_v5, 1334}; 1335 1336struct s5p_mfc_buf_align mfc_buf_align_v5 = { 1337 .base = MFC_BASE_ALIGN_ORDER, 1338}; 1339 1340static struct s5p_mfc_variant mfc_drvdata_v5 = { 1341 .version = MFC_VERSION, 1342 .port_num = MFC_NUM_PORTS, 1343 .buf_size = &buf_size_v5, 1344 .buf_align = &mfc_buf_align_v5, 1345 .fw_name = "s5p-mfc.fw", 1346}; 1347 1348struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { 1349 .dev_ctx = MFC_CTX_BUF_SIZE_V6, 1350 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, 1351 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, 1352 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, 1353 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, 1354}; 1355 1356struct s5p_mfc_buf_size buf_size_v6 = { 1357 .fw = MAX_FW_SIZE_V6, 1358 .cpb = MAX_CPB_SIZE_V6, 1359 .priv = &mfc_buf_size_v6, 1360}; 1361 1362struct s5p_mfc_buf_align mfc_buf_align_v6 = { 1363 .base = 0, 1364}; 1365 1366static struct s5p_mfc_variant mfc_drvdata_v6 = { 1367 .version = MFC_VERSION_V6, 1368 .port_num = MFC_NUM_PORTS_V6, 1369 .buf_size = &buf_size_v6, 1370 .buf_align = &mfc_buf_align_v6, 1371 .fw_name = "s5p-mfc-v6.fw", 1372}; 1373 1374struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = { 1375 .dev_ctx = MFC_CTX_BUF_SIZE_V7, 1376 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7, 1377 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7, 1378 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7, 1379 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7, 1380}; 1381 1382struct s5p_mfc_buf_size buf_size_v7 = { 1383 .fw = MAX_FW_SIZE_V7, 1384 .cpb = MAX_CPB_SIZE_V7, 1385 .priv = &mfc_buf_size_v7, 1386}; 1387 1388struct s5p_mfc_buf_align mfc_buf_align_v7 = { 1389 .base = 0, 1390}; 1391 1392static struct s5p_mfc_variant mfc_drvdata_v7 = { 1393 .version = MFC_VERSION_V7, 1394 .port_num = MFC_NUM_PORTS_V7, 1395 .buf_size = &buf_size_v7, 1396 .buf_align = &mfc_buf_align_v7, 1397 .fw_name = "s5p-mfc-v7.fw", 1398}; 1399 1400static struct platform_device_id mfc_driver_ids[] = { 1401 { 1402 .name = "s5p-mfc", 1403 .driver_data = (unsigned long)&mfc_drvdata_v5, 1404 }, { 1405 .name = "s5p-mfc-v5", 1406 .driver_data = (unsigned long)&mfc_drvdata_v5, 1407 }, { 1408 .name = "s5p-mfc-v6", 1409 .driver_data = (unsigned long)&mfc_drvdata_v6, 1410 }, { 1411 .name = "s5p-mfc-v7", 1412 .driver_data = (unsigned long)&mfc_drvdata_v7, 1413 }, 1414 {}, 1415}; 1416MODULE_DEVICE_TABLE(platform, mfc_driver_ids); 1417 1418static const struct of_device_id exynos_mfc_match[] = { 1419 { 1420 .compatible = "samsung,mfc-v5", 1421 .data = &mfc_drvdata_v5, 1422 }, { 1423 .compatible = "samsung,mfc-v6", 1424 .data = &mfc_drvdata_v6, 1425 }, { 1426 .compatible = "samsung,mfc-v7", 1427 .data = &mfc_drvdata_v7, 1428 }, 1429 {}, 1430}; 1431MODULE_DEVICE_TABLE(of, exynos_mfc_match); 1432 1433static void *mfc_get_drv_data(struct platform_device *pdev) 1434{ 1435 struct s5p_mfc_variant *driver_data = NULL; 1436 1437 if (pdev->dev.of_node) { 1438 const struct of_device_id *match; 1439 match = of_match_node(exynos_mfc_match, 1440 pdev->dev.of_node); 1441 if (match) 1442 driver_data = (struct s5p_mfc_variant *)match->data; 1443 } else { 1444 driver_data = (struct s5p_mfc_variant *) 1445 platform_get_device_id(pdev)->driver_data; 1446 } 1447 return driver_data; 1448} 1449 1450static struct platform_driver s5p_mfc_driver = { 1451 .probe = s5p_mfc_probe, 1452 .remove = s5p_mfc_remove, 1453 .id_table = mfc_driver_ids, 1454 .driver = { 1455 .name = S5P_MFC_NAME, 1456 .owner = THIS_MODULE, 1457 .pm = &s5p_mfc_pm_ops, 1458 .of_match_table = exynos_mfc_match, 1459 }, 1460}; 1461 1462module_platform_driver(s5p_mfc_driver); 1463 1464MODULE_LICENSE("GPL"); 1465MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); 1466MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); 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