s5p_mfc.c revision 7296e25f6e76bedc96cb1f16c200e9ac7a87323b
1/* 2 * Samsung S5P Multi Format Codec v 5.1 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Kamil Debski, <k.debski@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22#include <media/v4l2-event.h> 23#include <linux/workqueue.h> 24#include <media/videobuf2-core.h> 25#include "s5p_mfc_common.h" 26#include "s5p_mfc_ctrl.h" 27#include "s5p_mfc_debug.h" 28#include "s5p_mfc_dec.h" 29#include "s5p_mfc_enc.h" 30#include "s5p_mfc_intr.h" 31#include "s5p_mfc_opr.h" 32#include "s5p_mfc_cmd.h" 33#include "s5p_mfc_pm.h" 34 35#define S5P_MFC_NAME "s5p-mfc" 36#define S5P_MFC_DEC_NAME "s5p-mfc-dec" 37#define S5P_MFC_ENC_NAME "s5p-mfc-enc" 38 39int debug; 40module_param(debug, int, S_IRUGO | S_IWUSR); 41MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); 42 43/* Helper functions for interrupt processing */ 44 45/* Remove from hw execution round robin */ 46void clear_work_bit(struct s5p_mfc_ctx *ctx) 47{ 48 struct s5p_mfc_dev *dev = ctx->dev; 49 50 spin_lock(&dev->condlock); 51 __clear_bit(ctx->num, &dev->ctx_work_bits); 52 spin_unlock(&dev->condlock); 53} 54 55/* Add to hw execution round robin */ 56void set_work_bit(struct s5p_mfc_ctx *ctx) 57{ 58 struct s5p_mfc_dev *dev = ctx->dev; 59 60 spin_lock(&dev->condlock); 61 __set_bit(ctx->num, &dev->ctx_work_bits); 62 spin_unlock(&dev->condlock); 63} 64 65/* Remove from hw execution round robin */ 66void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 67{ 68 struct s5p_mfc_dev *dev = ctx->dev; 69 unsigned long flags; 70 71 spin_lock_irqsave(&dev->condlock, flags); 72 __clear_bit(ctx->num, &dev->ctx_work_bits); 73 spin_unlock_irqrestore(&dev->condlock, flags); 74} 75 76/* Add to hw execution round robin */ 77void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 78{ 79 struct s5p_mfc_dev *dev = ctx->dev; 80 unsigned long flags; 81 82 spin_lock_irqsave(&dev->condlock, flags); 83 __set_bit(ctx->num, &dev->ctx_work_bits); 84 spin_unlock_irqrestore(&dev->condlock, flags); 85} 86 87/* Wake up context wait_queue */ 88static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, 89 unsigned int err) 90{ 91 ctx->int_cond = 1; 92 ctx->int_type = reason; 93 ctx->int_err = err; 94 wake_up(&ctx->queue); 95} 96 97/* Wake up device wait_queue */ 98static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, 99 unsigned int err) 100{ 101 dev->int_cond = 1; 102 dev->int_type = reason; 103 dev->int_err = err; 104 wake_up(&dev->queue); 105} 106 107static void s5p_mfc_watchdog(unsigned long arg) 108{ 109 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; 110 111 if (test_bit(0, &dev->hw_lock)) 112 atomic_inc(&dev->watchdog_cnt); 113 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { 114 /* This means that hw is busy and no interrupts were 115 * generated by hw for the Nth time of running this 116 * watchdog timer. This usually means a serious hw 117 * error. Now it is time to kill all instances and 118 * reset the MFC. */ 119 mfc_err("Time out during waiting for HW\n"); 120 queue_work(dev->watchdog_workqueue, &dev->watchdog_work); 121 } 122 dev->watchdog_timer.expires = jiffies + 123 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 124 add_timer(&dev->watchdog_timer); 125} 126 127static void s5p_mfc_watchdog_worker(struct work_struct *work) 128{ 129 struct s5p_mfc_dev *dev; 130 struct s5p_mfc_ctx *ctx; 131 unsigned long flags; 132 int mutex_locked; 133 int i, ret; 134 135 dev = container_of(work, struct s5p_mfc_dev, watchdog_work); 136 137 mfc_err("Driver timeout error handling\n"); 138 /* Lock the mutex that protects open and release. 139 * This is necessary as they may load and unload firmware. */ 140 mutex_locked = mutex_trylock(&dev->mfc_mutex); 141 if (!mutex_locked) 142 mfc_err("Error: some instance may be closing/opening\n"); 143 spin_lock_irqsave(&dev->irqlock, flags); 144 145 s5p_mfc_clock_off(); 146 147 for (i = 0; i < MFC_NUM_CONTEXTS; i++) { 148 ctx = dev->ctx[i]; 149 if (!ctx) 150 continue; 151 ctx->state = MFCINST_ERROR; 152 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 153 &ctx->vq_dst); 154 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 155 &ctx->vq_src); 156 clear_work_bit(ctx); 157 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); 158 } 159 clear_bit(0, &dev->hw_lock); 160 spin_unlock_irqrestore(&dev->irqlock, flags); 161 /* Double check if there is at least one instance running. 162 * If no instance is in memory than no firmware should be present */ 163 if (dev->num_inst > 0) { 164 ret = s5p_mfc_reload_firmware(dev); 165 if (ret) { 166 mfc_err("Failed to reload FW\n"); 167 goto unlock; 168 } 169 s5p_mfc_clock_on(); 170 ret = s5p_mfc_init_hw(dev); 171 if (ret) 172 mfc_err("Failed to reinit FW\n"); 173 } 174unlock: 175 if (mutex_locked) 176 mutex_unlock(&dev->mfc_mutex); 177} 178 179static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file) 180{ 181 struct video_device *vdev = video_devdata(file); 182 183 if (!vdev) { 184 mfc_err("failed to get video_device"); 185 return MFCNODE_INVALID; 186 } 187 if (vdev->index == 0) 188 return MFCNODE_DECODER; 189 else if (vdev->index == 1) 190 return MFCNODE_ENCODER; 191 return MFCNODE_INVALID; 192} 193 194static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) 195{ 196 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 197 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 198 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 199} 200 201static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) 202{ 203 struct s5p_mfc_buf *dst_buf; 204 struct s5p_mfc_dev *dev = ctx->dev; 205 206 ctx->state = MFCINST_FINISHED; 207 ctx->sequence++; 208 while (!list_empty(&ctx->dst_queue)) { 209 dst_buf = list_entry(ctx->dst_queue.next, 210 struct s5p_mfc_buf, list); 211 mfc_debug(2, "Cleaning up buffer: %d\n", 212 dst_buf->b->v4l2_buf.index); 213 vb2_set_plane_payload(dst_buf->b, 0, 0); 214 vb2_set_plane_payload(dst_buf->b, 1, 0); 215 list_del(&dst_buf->list); 216 ctx->dst_queue_cnt--; 217 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); 218 219 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == 220 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) 221 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 222 else 223 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; 224 225 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); 226 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); 227 } 228} 229 230static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) 231{ 232 struct s5p_mfc_dev *dev = ctx->dev; 233 struct s5p_mfc_buf *dst_buf, *src_buf; 234 size_t dec_y_addr; 235 unsigned int frame_type; 236 237 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); 238 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 239 240 /* Copy timestamp / timecode from decoded src to dst and set 241 appropraite flags */ 242 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 243 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 244 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { 245 memcpy(&dst_buf->b->v4l2_buf.timecode, 246 &src_buf->b->v4l2_buf.timecode, 247 sizeof(struct v4l2_timecode)); 248 memcpy(&dst_buf->b->v4l2_buf.timestamp, 249 &src_buf->b->v4l2_buf.timestamp, 250 sizeof(struct timeval)); 251 switch (frame_type) { 252 case S5P_FIMV_DECODE_FRAME_I_FRAME: 253 dst_buf->b->v4l2_buf.flags |= 254 V4L2_BUF_FLAG_KEYFRAME; 255 break; 256 case S5P_FIMV_DECODE_FRAME_P_FRAME: 257 dst_buf->b->v4l2_buf.flags |= 258 V4L2_BUF_FLAG_PFRAME; 259 break; 260 case S5P_FIMV_DECODE_FRAME_B_FRAME: 261 dst_buf->b->v4l2_buf.flags |= 262 V4L2_BUF_FLAG_BFRAME; 263 break; 264 } 265 break; 266 } 267 } 268} 269 270static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) 271{ 272 struct s5p_mfc_dev *dev = ctx->dev; 273 struct s5p_mfc_buf *dst_buf; 274 size_t dspl_y_addr; 275 unsigned int frame_type; 276 unsigned int index; 277 278 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); 279 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 280 281 /* If frame is same as previous then skip and do not dequeue */ 282 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { 283 if (!ctx->after_packed_pb) 284 ctx->sequence++; 285 ctx->after_packed_pb = 0; 286 return; 287 } 288 ctx->sequence++; 289 /* The MFC returns address of the buffer, now we have to 290 * check which videobuf does it correspond to */ 291 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 292 /* Check if this is the buffer we're looking for */ 293 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { 294 list_del(&dst_buf->list); 295 ctx->dst_queue_cnt--; 296 dst_buf->b->v4l2_buf.sequence = ctx->sequence; 297 if (s5p_mfc_hw_call(dev->mfc_ops, 298 get_pic_type_top, ctx) == 299 s5p_mfc_hw_call(dev->mfc_ops, 300 get_pic_type_bot, ctx)) 301 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 302 else 303 dst_buf->b->v4l2_buf.field = 304 V4L2_FIELD_INTERLACED; 305 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); 306 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); 307 clear_bit(dst_buf->b->v4l2_buf.index, 308 &ctx->dec_dst_flag); 309 310 vb2_buffer_done(dst_buf->b, 311 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 312 313 index = dst_buf->b->v4l2_buf.index; 314 break; 315 } 316 } 317} 318 319/* Handle frame decoding interrupt */ 320static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, 321 unsigned int reason, unsigned int err) 322{ 323 struct s5p_mfc_dev *dev = ctx->dev; 324 unsigned int dst_frame_status; 325 struct s5p_mfc_buf *src_buf; 326 unsigned long flags; 327 unsigned int res_change; 328 329 unsigned int index; 330 331 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 332 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 333 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 334 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) 335 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; 336 mfc_debug(2, "Frame Status: %x\n", dst_frame_status); 337 if (ctx->state == MFCINST_RES_CHANGE_INIT) 338 ctx->state = MFCINST_RES_CHANGE_FLUSH; 339 if (res_change == S5P_FIMV_RES_INCREASE || 340 res_change == S5P_FIMV_RES_DECREASE) { 341 ctx->state = MFCINST_RES_CHANGE_INIT; 342 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 343 wake_up_ctx(ctx, reason, err); 344 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 345 BUG(); 346 s5p_mfc_clock_off(); 347 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 348 return; 349 } 350 if (ctx->dpb_flush_flag) 351 ctx->dpb_flush_flag = 0; 352 353 spin_lock_irqsave(&dev->irqlock, flags); 354 /* All frames remaining in the buffer have been extracted */ 355 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { 356 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { 357 s5p_mfc_handle_frame_all_extracted(ctx); 358 ctx->state = MFCINST_RES_CHANGE_END; 359 goto leave_handle_frame; 360 } else { 361 s5p_mfc_handle_frame_all_extracted(ctx); 362 } 363 } 364 365 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY || 366 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) 367 s5p_mfc_handle_frame_copy_time(ctx); 368 369 /* A frame has been decoded and is in the buffer */ 370 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || 371 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { 372 s5p_mfc_handle_frame_new(ctx, err); 373 } else { 374 mfc_debug(2, "No frame decode\n"); 375 } 376 /* Mark source buffer as complete */ 377 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 378 && !list_empty(&ctx->src_queue)) { 379 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 380 list); 381 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, 382 get_consumed_stream, dev); 383 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && 384 ctx->consumed_stream + STUFF_BYTE < 385 src_buf->b->v4l2_planes[0].bytesused) { 386 /* Run MFC again on the same buffer */ 387 mfc_debug(2, "Running again the same buffer\n"); 388 ctx->after_packed_pb = 1; 389 } else { 390 index = src_buf->b->v4l2_buf.index; 391 mfc_debug(2, "MFC needs next buffer\n"); 392 ctx->consumed_stream = 0; 393 list_del(&src_buf->list); 394 ctx->src_queue_cnt--; 395 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) 396 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); 397 else 398 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); 399 } 400 } 401leave_handle_frame: 402 spin_unlock_irqrestore(&dev->irqlock, flags); 403 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 404 || ctx->dst_queue_cnt < ctx->dpb_count) 405 clear_work_bit(ctx); 406 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 407 wake_up_ctx(ctx, reason, err); 408 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 409 BUG(); 410 s5p_mfc_clock_off(); 411 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 412} 413 414/* Error handling for interrupt */ 415static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, 416 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) 417{ 418 unsigned long flags; 419 420 mfc_err("Interrupt Error: %08x\n", err); 421 422 if (ctx != NULL) { 423 /* Error recovery is dependent on the state of context */ 424 switch (ctx->state) { 425 case MFCINST_RES_CHANGE_INIT: 426 case MFCINST_RES_CHANGE_FLUSH: 427 case MFCINST_RES_CHANGE_END: 428 case MFCINST_FINISHING: 429 case MFCINST_FINISHED: 430 case MFCINST_RUNNING: 431 /* It is higly probable that an error occured 432 * while decoding a frame */ 433 clear_work_bit(ctx); 434 ctx->state = MFCINST_ERROR; 435 /* Mark all dst buffers as having an error */ 436 spin_lock_irqsave(&dev->irqlock, flags); 437 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 438 &ctx->dst_queue, &ctx->vq_dst); 439 /* Mark all src buffers as having an error */ 440 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 441 &ctx->src_queue, &ctx->vq_src); 442 spin_unlock_irqrestore(&dev->irqlock, flags); 443 wake_up_ctx(ctx, reason, err); 444 break; 445 default: 446 clear_work_bit(ctx); 447 ctx->state = MFCINST_ERROR; 448 wake_up_ctx(ctx, reason, err); 449 break; 450 } 451 } 452 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 453 BUG(); 454 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 455 s5p_mfc_clock_off(); 456 wake_up_dev(dev, reason, err); 457 return; 458} 459 460/* Header parsing interrupt handling */ 461static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 462 unsigned int reason, unsigned int err) 463{ 464 struct s5p_mfc_dev *dev; 465 466 if (ctx == NULL) 467 return; 468 dev = ctx->dev; 469 if (ctx->c_ops->post_seq_start) { 470 if (ctx->c_ops->post_seq_start(ctx)) 471 mfc_err("post_seq_start() failed\n"); 472 } else { 473 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, 474 dev); 475 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 476 dev); 477 478 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); 479 480 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 481 dev); 482 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, 483 dev); 484 if (ctx->img_width == 0 || ctx->img_height == 0) 485 ctx->state = MFCINST_ERROR; 486 else 487 ctx->state = MFCINST_HEAD_PARSED; 488 489 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 490 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && 491 !list_empty(&ctx->src_queue)) { 492 struct s5p_mfc_buf *src_buf; 493 src_buf = list_entry(ctx->src_queue.next, 494 struct s5p_mfc_buf, list); 495 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, 496 dev) < 497 src_buf->b->v4l2_planes[0].bytesused) 498 ctx->head_processed = 0; 499 else 500 ctx->head_processed = 1; 501 } else { 502 ctx->head_processed = 1; 503 } 504 } 505 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 506 clear_work_bit(ctx); 507 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 508 BUG(); 509 s5p_mfc_clock_off(); 510 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 511 wake_up_ctx(ctx, reason, err); 512} 513 514/* Header parsing interrupt handling */ 515static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, 516 unsigned int reason, unsigned int err) 517{ 518 struct s5p_mfc_buf *src_buf; 519 struct s5p_mfc_dev *dev; 520 unsigned long flags; 521 522 if (ctx == NULL) 523 return; 524 dev = ctx->dev; 525 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 526 ctx->int_type = reason; 527 ctx->int_err = err; 528 ctx->int_cond = 1; 529 clear_work_bit(ctx); 530 if (err == 0) { 531 ctx->state = MFCINST_RUNNING; 532 if (!ctx->dpb_flush_flag && ctx->head_processed) { 533 spin_lock_irqsave(&dev->irqlock, flags); 534 if (!list_empty(&ctx->src_queue)) { 535 src_buf = list_entry(ctx->src_queue.next, 536 struct s5p_mfc_buf, list); 537 list_del(&src_buf->list); 538 ctx->src_queue_cnt--; 539 vb2_buffer_done(src_buf->b, 540 VB2_BUF_STATE_DONE); 541 } 542 spin_unlock_irqrestore(&dev->irqlock, flags); 543 } else { 544 ctx->dpb_flush_flag = 0; 545 } 546 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 547 BUG(); 548 549 s5p_mfc_clock_off(); 550 551 wake_up(&ctx->queue); 552 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 553 } else { 554 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 555 BUG(); 556 557 s5p_mfc_clock_off(); 558 559 wake_up(&ctx->queue); 560 } 561} 562 563static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, 564 unsigned int reason, unsigned int err) 565{ 566 struct s5p_mfc_dev *dev = ctx->dev; 567 struct s5p_mfc_buf *mb_entry; 568 569 mfc_debug(2, "Stream completed"); 570 571 s5p_mfc_clear_int_flags(dev); 572 ctx->int_type = reason; 573 ctx->int_err = err; 574 ctx->state = MFCINST_FINISHED; 575 576 spin_lock(&dev->irqlock); 577 if (!list_empty(&ctx->dst_queue)) { 578 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, 579 list); 580 list_del(&mb_entry->list); 581 ctx->dst_queue_cnt--; 582 vb2_set_plane_payload(mb_entry->b, 0, 0); 583 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE); 584 } 585 spin_unlock(&dev->irqlock); 586 587 clear_work_bit(ctx); 588 589 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 590 WARN_ON(1); 591 592 s5p_mfc_clock_off(); 593 wake_up(&ctx->queue); 594 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 595} 596 597/* Interrupt processing */ 598static irqreturn_t s5p_mfc_irq(int irq, void *priv) 599{ 600 struct s5p_mfc_dev *dev = priv; 601 struct s5p_mfc_ctx *ctx; 602 unsigned int reason; 603 unsigned int err; 604 605 mfc_debug_enter(); 606 /* Reset the timeout watchdog */ 607 atomic_set(&dev->watchdog_cnt, 0); 608 ctx = dev->ctx[dev->curr_ctx]; 609 /* Get the reason of interrupt and the error code */ 610 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); 611 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); 612 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); 613 switch (reason) { 614 case S5P_MFC_R2H_CMD_ERR_RET: 615 /* An error has occured */ 616 if (ctx->state == MFCINST_RUNNING && 617 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= 618 dev->warn_start) 619 s5p_mfc_handle_frame(ctx, reason, err); 620 else 621 s5p_mfc_handle_error(dev, ctx, reason, err); 622 clear_bit(0, &dev->enter_suspend); 623 break; 624 625 case S5P_MFC_R2H_CMD_SLICE_DONE_RET: 626 case S5P_MFC_R2H_CMD_FIELD_DONE_RET: 627 case S5P_MFC_R2H_CMD_FRAME_DONE_RET: 628 if (ctx->c_ops->post_frame_start) { 629 if (ctx->c_ops->post_frame_start(ctx)) 630 mfc_err("post_frame_start() failed\n"); 631 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 632 wake_up_ctx(ctx, reason, err); 633 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 634 BUG(); 635 s5p_mfc_clock_off(); 636 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 637 } else { 638 s5p_mfc_handle_frame(ctx, reason, err); 639 } 640 break; 641 642 case S5P_MFC_R2H_CMD_SEQ_DONE_RET: 643 s5p_mfc_handle_seq_done(ctx, reason, err); 644 break; 645 646 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: 647 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); 648 ctx->state = MFCINST_GOT_INST; 649 clear_work_bit(ctx); 650 wake_up(&ctx->queue); 651 goto irq_cleanup_hw; 652 653 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: 654 clear_work_bit(ctx); 655 ctx->state = MFCINST_FREE; 656 wake_up(&ctx->queue); 657 goto irq_cleanup_hw; 658 659 case S5P_MFC_R2H_CMD_SYS_INIT_RET: 660 case S5P_MFC_R2H_CMD_FW_STATUS_RET: 661 case S5P_MFC_R2H_CMD_SLEEP_RET: 662 case S5P_MFC_R2H_CMD_WAKEUP_RET: 663 if (ctx) 664 clear_work_bit(ctx); 665 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 666 wake_up_dev(dev, reason, err); 667 clear_bit(0, &dev->hw_lock); 668 clear_bit(0, &dev->enter_suspend); 669 break; 670 671 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: 672 s5p_mfc_handle_init_buffers(ctx, reason, err); 673 break; 674 675 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: 676 s5p_mfc_handle_stream_complete(ctx, reason, err); 677 break; 678 679 default: 680 mfc_debug(2, "Unknown int reason\n"); 681 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 682 } 683 mfc_debug_leave(); 684 return IRQ_HANDLED; 685irq_cleanup_hw: 686 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 687 ctx->int_type = reason; 688 ctx->int_err = err; 689 ctx->int_cond = 1; 690 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 691 mfc_err("Failed to unlock hw\n"); 692 693 s5p_mfc_clock_off(); 694 695 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 696 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 697 return IRQ_HANDLED; 698} 699 700/* Open an MFC node */ 701static int s5p_mfc_open(struct file *file) 702{ 703 struct s5p_mfc_dev *dev = video_drvdata(file); 704 struct s5p_mfc_ctx *ctx = NULL; 705 struct vb2_queue *q; 706 int ret = 0; 707 708 mfc_debug_enter(); 709 if (mutex_lock_interruptible(&dev->mfc_mutex)) 710 return -ERESTARTSYS; 711 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ 712 /* Allocate memory for context */ 713 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 714 if (!ctx) { 715 mfc_err("Not enough memory\n"); 716 ret = -ENOMEM; 717 goto err_alloc; 718 } 719 v4l2_fh_init(&ctx->fh, video_devdata(file)); 720 file->private_data = &ctx->fh; 721 v4l2_fh_add(&ctx->fh); 722 ctx->dev = dev; 723 INIT_LIST_HEAD(&ctx->src_queue); 724 INIT_LIST_HEAD(&ctx->dst_queue); 725 ctx->src_queue_cnt = 0; 726 ctx->dst_queue_cnt = 0; 727 /* Get context number */ 728 ctx->num = 0; 729 while (dev->ctx[ctx->num]) { 730 ctx->num++; 731 if (ctx->num >= MFC_NUM_CONTEXTS) { 732 mfc_err("Too many open contexts\n"); 733 ret = -EBUSY; 734 goto err_no_ctx; 735 } 736 } 737 /* Mark context as idle */ 738 clear_work_bit_irqsave(ctx); 739 dev->ctx[ctx->num] = ctx; 740 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 741 ctx->type = MFCINST_DECODER; 742 ctx->c_ops = get_dec_codec_ops(); 743 s5p_mfc_dec_init(ctx); 744 /* Setup ctrl handler */ 745 ret = s5p_mfc_dec_ctrls_setup(ctx); 746 if (ret) { 747 mfc_err("Failed to setup mfc controls\n"); 748 goto err_ctrls_setup; 749 } 750 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 751 ctx->type = MFCINST_ENCODER; 752 ctx->c_ops = get_enc_codec_ops(); 753 /* only for encoder */ 754 INIT_LIST_HEAD(&ctx->ref_queue); 755 ctx->ref_queue_cnt = 0; 756 s5p_mfc_enc_init(ctx); 757 /* Setup ctrl handler */ 758 ret = s5p_mfc_enc_ctrls_setup(ctx); 759 if (ret) { 760 mfc_err("Failed to setup mfc controls\n"); 761 goto err_ctrls_setup; 762 } 763 } else { 764 ret = -ENOENT; 765 goto err_bad_node; 766 } 767 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 768 ctx->inst_no = -1; 769 /* Load firmware if this is the first instance */ 770 if (dev->num_inst == 1) { 771 dev->watchdog_timer.expires = jiffies + 772 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 773 add_timer(&dev->watchdog_timer); 774 ret = s5p_mfc_power_on(); 775 if (ret < 0) { 776 mfc_err("power on failed\n"); 777 goto err_pwr_enable; 778 } 779 s5p_mfc_clock_on(); 780 ret = s5p_mfc_alloc_and_load_firmware(dev); 781 if (ret) 782 goto err_alloc_fw; 783 /* Init the FW */ 784 ret = s5p_mfc_init_hw(dev); 785 if (ret) 786 goto err_init_hw; 787 s5p_mfc_clock_off(); 788 } 789 /* Init videobuf2 queue for CAPTURE */ 790 q = &ctx->vq_dst; 791 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 792 q->drv_priv = &ctx->fh; 793 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 794 q->io_modes = VB2_MMAP; 795 q->ops = get_dec_queue_ops(); 796 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 797 q->io_modes = VB2_MMAP | VB2_USERPTR; 798 q->ops = get_enc_queue_ops(); 799 } else { 800 ret = -ENOENT; 801 goto err_queue_init; 802 } 803 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 804 ret = vb2_queue_init(q); 805 if (ret) { 806 mfc_err("Failed to initialize videobuf2 queue(capture)\n"); 807 goto err_queue_init; 808 } 809 /* Init videobuf2 queue for OUTPUT */ 810 q = &ctx->vq_src; 811 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 812 q->io_modes = VB2_MMAP; 813 q->drv_priv = &ctx->fh; 814 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 815 q->io_modes = VB2_MMAP; 816 q->ops = get_dec_queue_ops(); 817 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 818 q->io_modes = VB2_MMAP | VB2_USERPTR; 819 q->ops = get_enc_queue_ops(); 820 } else { 821 ret = -ENOENT; 822 goto err_queue_init; 823 } 824 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 825 ret = vb2_queue_init(q); 826 if (ret) { 827 mfc_err("Failed to initialize videobuf2 queue(output)\n"); 828 goto err_queue_init; 829 } 830 init_waitqueue_head(&ctx->queue); 831 mutex_unlock(&dev->mfc_mutex); 832 mfc_debug_leave(); 833 return ret; 834 /* Deinit when failure occured */ 835err_queue_init: 836err_init_hw: 837 s5p_mfc_release_firmware(dev); 838err_alloc_fw: 839 dev->ctx[ctx->num] = NULL; 840 del_timer_sync(&dev->watchdog_timer); 841 s5p_mfc_clock_off(); 842err_pwr_enable: 843 if (dev->num_inst == 1) { 844 if (s5p_mfc_power_off() < 0) 845 mfc_err("power off failed\n"); 846 s5p_mfc_release_firmware(dev); 847 } 848err_ctrls_setup: 849 s5p_mfc_dec_ctrls_delete(ctx); 850err_bad_node: 851err_no_ctx: 852 v4l2_fh_del(&ctx->fh); 853 v4l2_fh_exit(&ctx->fh); 854 kfree(ctx); 855err_alloc: 856 dev->num_inst--; 857 mutex_unlock(&dev->mfc_mutex); 858 mfc_debug_leave(); 859 return ret; 860} 861 862/* Release MFC context */ 863static int s5p_mfc_release(struct file *file) 864{ 865 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 866 struct s5p_mfc_dev *dev = ctx->dev; 867 868 mfc_debug_enter(); 869 mutex_lock(&dev->mfc_mutex); 870 s5p_mfc_clock_on(); 871 vb2_queue_release(&ctx->vq_src); 872 vb2_queue_release(&ctx->vq_dst); 873 /* Mark context as idle */ 874 clear_work_bit_irqsave(ctx); 875 /* If instance was initialised then 876 * return instance and free reosurces */ 877 if (ctx->inst_no != MFC_NO_INSTANCE_SET) { 878 mfc_debug(2, "Has to free instance\n"); 879 ctx->state = MFCINST_RETURN_INST; 880 set_work_bit_irqsave(ctx); 881 s5p_mfc_clean_ctx_int_flags(ctx); 882 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 883 /* Wait until instance is returned or timeout occured */ 884 if (s5p_mfc_wait_for_done_ctx 885 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) { 886 s5p_mfc_clock_off(); 887 mfc_err("Err returning instance\n"); 888 } 889 mfc_debug(2, "After free instance\n"); 890 /* Free resources */ 891 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); 892 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); 893 if (ctx->type == MFCINST_DECODER) 894 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, 895 ctx); 896 897 ctx->inst_no = MFC_NO_INSTANCE_SET; 898 } 899 /* hardware locking scheme */ 900 if (dev->curr_ctx == ctx->num) 901 clear_bit(0, &dev->hw_lock); 902 dev->num_inst--; 903 if (dev->num_inst == 0) { 904 mfc_debug(2, "Last instance - release firmware\n"); 905 /* reset <-> F/W release */ 906 s5p_mfc_reset(dev); 907 s5p_mfc_deinit_hw(dev); 908 s5p_mfc_release_firmware(dev); 909 del_timer_sync(&dev->watchdog_timer); 910 if (s5p_mfc_power_off() < 0) 911 mfc_err("Power off failed\n"); 912 } 913 mfc_debug(2, "Shutting down clock\n"); 914 s5p_mfc_clock_off(); 915 dev->ctx[ctx->num] = NULL; 916 s5p_mfc_dec_ctrls_delete(ctx); 917 v4l2_fh_del(&ctx->fh); 918 v4l2_fh_exit(&ctx->fh); 919 kfree(ctx); 920 mfc_debug_leave(); 921 mutex_unlock(&dev->mfc_mutex); 922 return 0; 923} 924 925/* Poll */ 926static unsigned int s5p_mfc_poll(struct file *file, 927 struct poll_table_struct *wait) 928{ 929 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 930 struct s5p_mfc_dev *dev = ctx->dev; 931 struct vb2_queue *src_q, *dst_q; 932 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; 933 unsigned int rc = 0; 934 unsigned long flags; 935 936 mutex_lock(&dev->mfc_mutex); 937 src_q = &ctx->vq_src; 938 dst_q = &ctx->vq_dst; 939 /* 940 * There has to be at least one buffer queued on each queued_list, which 941 * means either in driver already or waiting for driver to claim it 942 * and start processing. 943 */ 944 if ((!src_q->streaming || list_empty(&src_q->queued_list)) 945 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { 946 rc = POLLERR; 947 goto end; 948 } 949 mutex_unlock(&dev->mfc_mutex); 950 poll_wait(file, &ctx->fh.wait, wait); 951 poll_wait(file, &src_q->done_wq, wait); 952 poll_wait(file, &dst_q->done_wq, wait); 953 mutex_lock(&dev->mfc_mutex); 954 if (v4l2_event_pending(&ctx->fh)) 955 rc |= POLLPRI; 956 spin_lock_irqsave(&src_q->done_lock, flags); 957 if (!list_empty(&src_q->done_list)) 958 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, 959 done_entry); 960 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE 961 || src_vb->state == VB2_BUF_STATE_ERROR)) 962 rc |= POLLOUT | POLLWRNORM; 963 spin_unlock_irqrestore(&src_q->done_lock, flags); 964 spin_lock_irqsave(&dst_q->done_lock, flags); 965 if (!list_empty(&dst_q->done_list)) 966 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, 967 done_entry); 968 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE 969 || dst_vb->state == VB2_BUF_STATE_ERROR)) 970 rc |= POLLIN | POLLRDNORM; 971 spin_unlock_irqrestore(&dst_q->done_lock, flags); 972end: 973 mutex_unlock(&dev->mfc_mutex); 974 return rc; 975} 976 977/* Mmap */ 978static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) 979{ 980 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 981 struct s5p_mfc_dev *dev = ctx->dev; 982 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 983 int ret; 984 985 if (mutex_lock_interruptible(&dev->mfc_mutex)) 986 return -ERESTARTSYS; 987 if (offset < DST_QUEUE_OFF_BASE) { 988 mfc_debug(2, "mmaping source\n"); 989 ret = vb2_mmap(&ctx->vq_src, vma); 990 } else { /* capture */ 991 mfc_debug(2, "mmaping destination\n"); 992 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); 993 ret = vb2_mmap(&ctx->vq_dst, vma); 994 } 995 mutex_unlock(&dev->mfc_mutex); 996 return ret; 997} 998 999/* v4l2 ops */ 1000static const struct v4l2_file_operations s5p_mfc_fops = { 1001 .owner = THIS_MODULE, 1002 .open = s5p_mfc_open, 1003 .release = s5p_mfc_release, 1004 .poll = s5p_mfc_poll, 1005 .unlocked_ioctl = video_ioctl2, 1006 .mmap = s5p_mfc_mmap, 1007}; 1008 1009static int match_child(struct device *dev, void *data) 1010{ 1011 if (!dev_name(dev)) 1012 return 0; 1013 return !strcmp(dev_name(dev), (char *)data); 1014} 1015 1016/* MFC probe function */ 1017static int s5p_mfc_probe(struct platform_device *pdev) 1018{ 1019 struct s5p_mfc_dev *dev; 1020 struct video_device *vfd; 1021 struct resource *res; 1022 int ret; 1023 1024 pr_debug("%s++\n", __func__); 1025 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1026 if (!dev) { 1027 dev_err(&pdev->dev, "Not enough memory for MFC device\n"); 1028 return -ENOMEM; 1029 } 1030 1031 spin_lock_init(&dev->irqlock); 1032 spin_lock_init(&dev->condlock); 1033 dev->plat_dev = pdev; 1034 if (!dev->plat_dev) { 1035 dev_err(&pdev->dev, "No platform data specified\n"); 1036 return -ENODEV; 1037 } 1038 1039 dev->variant = (struct s5p_mfc_variant *) 1040 platform_get_device_id(pdev)->driver_data; 1041 1042 ret = s5p_mfc_init_pm(dev); 1043 if (ret < 0) { 1044 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 1045 return ret; 1046 } 1047 1048 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1049 1050 dev->regs_base = devm_request_and_ioremap(&pdev->dev, res); 1051 if (dev->regs_base == NULL) { 1052 dev_err(&pdev->dev, "Failed to obtain io memory\n"); 1053 return -ENOENT; 1054 } 1055 1056 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1057 if (res == NULL) { 1058 dev_err(&pdev->dev, "failed to get irq resource\n"); 1059 ret = -ENOENT; 1060 goto err_res; 1061 } 1062 dev->irq = res->start; 1063 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, 1064 IRQF_DISABLED, pdev->name, dev); 1065 if (ret) { 1066 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); 1067 goto err_res; 1068 } 1069 1070 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, "s5p-mfc-l", 1071 match_child); 1072 if (!dev->mem_dev_l) { 1073 mfc_err("Mem child (L) device get failed\n"); 1074 ret = -ENODEV; 1075 goto err_res; 1076 } 1077 1078 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, "s5p-mfc-r", 1079 match_child); 1080 if (!dev->mem_dev_r) { 1081 mfc_err("Mem child (R) device get failed\n"); 1082 ret = -ENODEV; 1083 goto err_res; 1084 } 1085 1086 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); 1087 if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) { 1088 ret = PTR_ERR(dev->alloc_ctx[0]); 1089 goto err_res; 1090 } 1091 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); 1092 if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) { 1093 ret = PTR_ERR(dev->alloc_ctx[1]); 1094 goto err_mem_init_ctx_1; 1095 } 1096 1097 mutex_init(&dev->mfc_mutex); 1098 1099 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 1100 if (ret) 1101 goto err_v4l2_dev_reg; 1102 init_waitqueue_head(&dev->queue); 1103 1104 /* decoder */ 1105 vfd = video_device_alloc(); 1106 if (!vfd) { 1107 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1108 ret = -ENOMEM; 1109 goto err_dec_alloc; 1110 } 1111 vfd->fops = &s5p_mfc_fops, 1112 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); 1113 vfd->release = video_device_release, 1114 vfd->lock = &dev->mfc_mutex; 1115 vfd->v4l2_dev = &dev->v4l2_dev; 1116 vfd->vfl_dir = VFL_DIR_M2M; 1117 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); 1118 dev->vfd_dec = vfd; 1119 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1120 if (ret) { 1121 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1122 video_device_release(vfd); 1123 goto err_dec_reg; 1124 } 1125 v4l2_info(&dev->v4l2_dev, 1126 "decoder registered as /dev/video%d\n", vfd->num); 1127 video_set_drvdata(vfd, dev); 1128 1129 /* encoder */ 1130 vfd = video_device_alloc(); 1131 if (!vfd) { 1132 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1133 ret = -ENOMEM; 1134 goto err_enc_alloc; 1135 } 1136 vfd->fops = &s5p_mfc_fops, 1137 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); 1138 vfd->release = video_device_release, 1139 vfd->lock = &dev->mfc_mutex; 1140 vfd->v4l2_dev = &dev->v4l2_dev; 1141 vfd->vfl_dir = VFL_DIR_M2M; 1142 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); 1143 dev->vfd_enc = vfd; 1144 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1145 if (ret) { 1146 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1147 video_device_release(vfd); 1148 goto err_enc_reg; 1149 } 1150 v4l2_info(&dev->v4l2_dev, 1151 "encoder registered as /dev/video%d\n", vfd->num); 1152 video_set_drvdata(vfd, dev); 1153 platform_set_drvdata(pdev, dev); 1154 1155 dev->hw_lock = 0; 1156 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); 1157 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); 1158 atomic_set(&dev->watchdog_cnt, 0); 1159 init_timer(&dev->watchdog_timer); 1160 dev->watchdog_timer.data = (unsigned long)dev; 1161 dev->watchdog_timer.function = s5p_mfc_watchdog; 1162 1163 /* Initialize HW ops and commands based on MFC version */ 1164 s5p_mfc_init_hw_ops(dev); 1165 s5p_mfc_init_hw_cmds(dev); 1166 1167 pr_debug("%s--\n", __func__); 1168 return 0; 1169 1170/* Deinit MFC if probe had failed */ 1171err_enc_reg: 1172 video_device_release(dev->vfd_enc); 1173err_enc_alloc: 1174 video_unregister_device(dev->vfd_dec); 1175err_dec_reg: 1176 video_device_release(dev->vfd_dec); 1177err_dec_alloc: 1178 v4l2_device_unregister(&dev->v4l2_dev); 1179err_v4l2_dev_reg: 1180 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1181err_mem_init_ctx_1: 1182 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1183err_res: 1184 s5p_mfc_final_pm(dev); 1185 1186 pr_debug("%s-- with error\n", __func__); 1187 return ret; 1188 1189} 1190 1191/* Remove the driver */ 1192static int __devexit s5p_mfc_remove(struct platform_device *pdev) 1193{ 1194 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); 1195 1196 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); 1197 1198 del_timer_sync(&dev->watchdog_timer); 1199 flush_workqueue(dev->watchdog_workqueue); 1200 destroy_workqueue(dev->watchdog_workqueue); 1201 1202 video_unregister_device(dev->vfd_enc); 1203 video_unregister_device(dev->vfd_dec); 1204 v4l2_device_unregister(&dev->v4l2_dev); 1205 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1206 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1207 1208 s5p_mfc_final_pm(dev); 1209 return 0; 1210} 1211 1212#ifdef CONFIG_PM_SLEEP 1213 1214static int s5p_mfc_suspend(struct device *dev) 1215{ 1216 struct platform_device *pdev = to_platform_device(dev); 1217 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1218 int ret; 1219 1220 if (m_dev->num_inst == 0) 1221 return 0; 1222 1223 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { 1224 mfc_err("Error: going to suspend for a second time\n"); 1225 return -EIO; 1226 } 1227 1228 /* Check if we're processing then wait if it necessary. */ 1229 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { 1230 /* Try and lock the HW */ 1231 /* Wait on the interrupt waitqueue */ 1232 ret = wait_event_interruptible_timeout(m_dev->queue, 1233 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond, 1234 msecs_to_jiffies(MFC_INT_TIMEOUT)); 1235 1236 if (ret == 0) { 1237 mfc_err("Waiting for hardware to finish timed out\n"); 1238 return -EIO; 1239 } 1240 } 1241 1242 return s5p_mfc_sleep(m_dev); 1243} 1244 1245static int s5p_mfc_resume(struct device *dev) 1246{ 1247 struct platform_device *pdev = to_platform_device(dev); 1248 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1249 1250 if (m_dev->num_inst == 0) 1251 return 0; 1252 return s5p_mfc_wakeup(m_dev); 1253} 1254#endif 1255 1256#ifdef CONFIG_PM_RUNTIME 1257static int s5p_mfc_runtime_suspend(struct device *dev) 1258{ 1259 struct platform_device *pdev = to_platform_device(dev); 1260 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1261 1262 atomic_set(&m_dev->pm.power, 0); 1263 return 0; 1264} 1265 1266static int s5p_mfc_runtime_resume(struct device *dev) 1267{ 1268 struct platform_device *pdev = to_platform_device(dev); 1269 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1270 int pre_power; 1271 1272 if (!m_dev->alloc_ctx) 1273 return 0; 1274 pre_power = atomic_read(&m_dev->pm.power); 1275 atomic_set(&m_dev->pm.power, 1); 1276 return 0; 1277} 1278#endif 1279 1280/* Power management */ 1281static const struct dev_pm_ops s5p_mfc_pm_ops = { 1282 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) 1283 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, 1284 NULL) 1285}; 1286 1287struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { 1288 .h264_ctx = MFC_H264_CTX_BUF_SIZE, 1289 .non_h264_ctx = MFC_CTX_BUF_SIZE, 1290 .dsc = DESC_BUF_SIZE, 1291 .shm = SHARED_BUF_SIZE, 1292}; 1293 1294struct s5p_mfc_buf_size buf_size_v5 = { 1295 .fw = MAX_FW_SIZE, 1296 .cpb = MAX_CPB_SIZE, 1297 .priv = &mfc_buf_size_v5, 1298}; 1299 1300struct s5p_mfc_buf_align mfc_buf_align_v5 = { 1301 .base = MFC_BASE_ALIGN_ORDER, 1302}; 1303 1304static struct s5p_mfc_variant mfc_drvdata_v5 = { 1305 .version = MFC_VERSION, 1306 .port_num = MFC_NUM_PORTS, 1307 .buf_size = &buf_size_v5, 1308 .buf_align = &mfc_buf_align_v5, 1309 .mclk_name = "sclk_mfc", 1310 .fw_name = "s5p-mfc.fw", 1311}; 1312 1313struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { 1314 .dev_ctx = MFC_CTX_BUF_SIZE_V6, 1315 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, 1316 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, 1317 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, 1318 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, 1319}; 1320 1321struct s5p_mfc_buf_size buf_size_v6 = { 1322 .fw = MAX_FW_SIZE_V6, 1323 .cpb = MAX_CPB_SIZE_V6, 1324 .priv = &mfc_buf_size_v6, 1325}; 1326 1327struct s5p_mfc_buf_align mfc_buf_align_v6 = { 1328 .base = 0, 1329}; 1330 1331static struct s5p_mfc_variant mfc_drvdata_v6 = { 1332 .version = MFC_VERSION_V6, 1333 .port_num = MFC_NUM_PORTS_V6, 1334 .buf_size = &buf_size_v6, 1335 .buf_align = &mfc_buf_align_v6, 1336 .mclk_name = "aclk_333", 1337 .fw_name = "s5p-mfc-v6.fw", 1338}; 1339 1340static struct platform_device_id mfc_driver_ids[] = { 1341 { 1342 .name = "s5p-mfc", 1343 .driver_data = (unsigned long)&mfc_drvdata_v5, 1344 }, { 1345 .name = "s5p-mfc-v5", 1346 .driver_data = (unsigned long)&mfc_drvdata_v5, 1347 }, { 1348 .name = "s5p-mfc-v6", 1349 .driver_data = (unsigned long)&mfc_drvdata_v6, 1350 }, 1351 {}, 1352}; 1353MODULE_DEVICE_TABLE(platform, mfc_driver_ids); 1354 1355static struct platform_driver s5p_mfc_driver = { 1356 .probe = s5p_mfc_probe, 1357 .remove = __devexit_p(s5p_mfc_remove), 1358 .id_table = mfc_driver_ids, 1359 .driver = { 1360 .name = S5P_MFC_NAME, 1361 .owner = THIS_MODULE, 1362 .pm = &s5p_mfc_pm_ops 1363 }, 1364}; 1365 1366module_platform_driver(s5p_mfc_driver); 1367 1368MODULE_LICENSE("GPL"); 1369MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); 1370MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); 1371 1372