s5p_mfc.c revision 8f23cc0222a9fe9c43f679dcb3d38604b30cf7c8
1/* 2 * Samsung S5P Multi Format Codec v 5.1 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Kamil Debski, <k.debski@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22#include <media/v4l2-event.h> 23#include <linux/workqueue.h> 24#include <linux/of.h> 25#include <media/videobuf2-core.h> 26#include "s5p_mfc_common.h" 27#include "s5p_mfc_ctrl.h" 28#include "s5p_mfc_debug.h" 29#include "s5p_mfc_dec.h" 30#include "s5p_mfc_enc.h" 31#include "s5p_mfc_intr.h" 32#include "s5p_mfc_opr.h" 33#include "s5p_mfc_cmd.h" 34#include "s5p_mfc_pm.h" 35 36#define S5P_MFC_NAME "s5p-mfc" 37#define S5P_MFC_DEC_NAME "s5p-mfc-dec" 38#define S5P_MFC_ENC_NAME "s5p-mfc-enc" 39 40int debug; 41module_param(debug, int, S_IRUGO | S_IWUSR); 42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); 43 44/* Helper functions for interrupt processing */ 45 46/* Remove from hw execution round robin */ 47void clear_work_bit(struct s5p_mfc_ctx *ctx) 48{ 49 struct s5p_mfc_dev *dev = ctx->dev; 50 51 spin_lock(&dev->condlock); 52 __clear_bit(ctx->num, &dev->ctx_work_bits); 53 spin_unlock(&dev->condlock); 54} 55 56/* Add to hw execution round robin */ 57void set_work_bit(struct s5p_mfc_ctx *ctx) 58{ 59 struct s5p_mfc_dev *dev = ctx->dev; 60 61 spin_lock(&dev->condlock); 62 __set_bit(ctx->num, &dev->ctx_work_bits); 63 spin_unlock(&dev->condlock); 64} 65 66/* Remove from hw execution round robin */ 67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 68{ 69 struct s5p_mfc_dev *dev = ctx->dev; 70 unsigned long flags; 71 72 spin_lock_irqsave(&dev->condlock, flags); 73 __clear_bit(ctx->num, &dev->ctx_work_bits); 74 spin_unlock_irqrestore(&dev->condlock, flags); 75} 76 77/* Add to hw execution round robin */ 78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 79{ 80 struct s5p_mfc_dev *dev = ctx->dev; 81 unsigned long flags; 82 83 spin_lock_irqsave(&dev->condlock, flags); 84 __set_bit(ctx->num, &dev->ctx_work_bits); 85 spin_unlock_irqrestore(&dev->condlock, flags); 86} 87 88/* Wake up context wait_queue */ 89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, 90 unsigned int err) 91{ 92 ctx->int_cond = 1; 93 ctx->int_type = reason; 94 ctx->int_err = err; 95 wake_up(&ctx->queue); 96} 97 98/* Wake up device wait_queue */ 99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, 100 unsigned int err) 101{ 102 dev->int_cond = 1; 103 dev->int_type = reason; 104 dev->int_err = err; 105 wake_up(&dev->queue); 106} 107 108static void s5p_mfc_watchdog(unsigned long arg) 109{ 110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; 111 112 if (test_bit(0, &dev->hw_lock)) 113 atomic_inc(&dev->watchdog_cnt); 114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { 115 /* This means that hw is busy and no interrupts were 116 * generated by hw for the Nth time of running this 117 * watchdog timer. This usually means a serious hw 118 * error. Now it is time to kill all instances and 119 * reset the MFC. */ 120 mfc_err("Time out during waiting for HW\n"); 121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work); 122 } 123 dev->watchdog_timer.expires = jiffies + 124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 125 add_timer(&dev->watchdog_timer); 126} 127 128static void s5p_mfc_watchdog_worker(struct work_struct *work) 129{ 130 struct s5p_mfc_dev *dev; 131 struct s5p_mfc_ctx *ctx; 132 unsigned long flags; 133 int mutex_locked; 134 int i, ret; 135 136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work); 137 138 mfc_err("Driver timeout error handling\n"); 139 /* Lock the mutex that protects open and release. 140 * This is necessary as they may load and unload firmware. */ 141 mutex_locked = mutex_trylock(&dev->mfc_mutex); 142 if (!mutex_locked) 143 mfc_err("Error: some instance may be closing/opening\n"); 144 spin_lock_irqsave(&dev->irqlock, flags); 145 146 s5p_mfc_clock_off(); 147 148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) { 149 ctx = dev->ctx[i]; 150 if (!ctx) 151 continue; 152 ctx->state = MFCINST_ERROR; 153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 154 &ctx->vq_dst); 155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 156 &ctx->vq_src); 157 clear_work_bit(ctx); 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); 159 } 160 clear_bit(0, &dev->hw_lock); 161 spin_unlock_irqrestore(&dev->irqlock, flags); 162 /* Double check if there is at least one instance running. 163 * If no instance is in memory than no firmware should be present */ 164 if (dev->num_inst > 0) { 165 ret = s5p_mfc_reload_firmware(dev); 166 if (ret) { 167 mfc_err("Failed to reload FW\n"); 168 goto unlock; 169 } 170 s5p_mfc_clock_on(); 171 ret = s5p_mfc_init_hw(dev); 172 if (ret) 173 mfc_err("Failed to reinit FW\n"); 174 } 175unlock: 176 if (mutex_locked) 177 mutex_unlock(&dev->mfc_mutex); 178} 179 180static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file) 181{ 182 struct video_device *vdev = video_devdata(file); 183 184 if (!vdev) { 185 mfc_err("failed to get video_device"); 186 return MFCNODE_INVALID; 187 } 188 if (vdev->index == 0) 189 return MFCNODE_DECODER; 190 else if (vdev->index == 1) 191 return MFCNODE_ENCODER; 192 return MFCNODE_INVALID; 193} 194 195static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) 196{ 197 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 198 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 199 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 200} 201 202static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) 203{ 204 struct s5p_mfc_buf *dst_buf; 205 struct s5p_mfc_dev *dev = ctx->dev; 206 207 ctx->state = MFCINST_FINISHED; 208 ctx->sequence++; 209 while (!list_empty(&ctx->dst_queue)) { 210 dst_buf = list_entry(ctx->dst_queue.next, 211 struct s5p_mfc_buf, list); 212 mfc_debug(2, "Cleaning up buffer: %d\n", 213 dst_buf->b->v4l2_buf.index); 214 vb2_set_plane_payload(dst_buf->b, 0, 0); 215 vb2_set_plane_payload(dst_buf->b, 1, 0); 216 list_del(&dst_buf->list); 217 ctx->dst_queue_cnt--; 218 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); 219 220 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == 221 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) 222 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 223 else 224 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; 225 226 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); 227 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); 228 } 229} 230 231static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) 232{ 233 struct s5p_mfc_dev *dev = ctx->dev; 234 struct s5p_mfc_buf *dst_buf, *src_buf; 235 size_t dec_y_addr; 236 unsigned int frame_type; 237 238 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); 239 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 240 241 /* Copy timestamp / timecode from decoded src to dst and set 242 appropraite flags */ 243 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 244 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 245 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { 246 memcpy(&dst_buf->b->v4l2_buf.timecode, 247 &src_buf->b->v4l2_buf.timecode, 248 sizeof(struct v4l2_timecode)); 249 memcpy(&dst_buf->b->v4l2_buf.timestamp, 250 &src_buf->b->v4l2_buf.timestamp, 251 sizeof(struct timeval)); 252 switch (frame_type) { 253 case S5P_FIMV_DECODE_FRAME_I_FRAME: 254 dst_buf->b->v4l2_buf.flags |= 255 V4L2_BUF_FLAG_KEYFRAME; 256 break; 257 case S5P_FIMV_DECODE_FRAME_P_FRAME: 258 dst_buf->b->v4l2_buf.flags |= 259 V4L2_BUF_FLAG_PFRAME; 260 break; 261 case S5P_FIMV_DECODE_FRAME_B_FRAME: 262 dst_buf->b->v4l2_buf.flags |= 263 V4L2_BUF_FLAG_BFRAME; 264 break; 265 } 266 break; 267 } 268 } 269} 270 271static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) 272{ 273 struct s5p_mfc_dev *dev = ctx->dev; 274 struct s5p_mfc_buf *dst_buf; 275 size_t dspl_y_addr; 276 unsigned int frame_type; 277 278 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); 279 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 280 281 /* If frame is same as previous then skip and do not dequeue */ 282 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { 283 if (!ctx->after_packed_pb) 284 ctx->sequence++; 285 ctx->after_packed_pb = 0; 286 return; 287 } 288 ctx->sequence++; 289 /* The MFC returns address of the buffer, now we have to 290 * check which videobuf does it correspond to */ 291 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 292 /* Check if this is the buffer we're looking for */ 293 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { 294 list_del(&dst_buf->list); 295 ctx->dst_queue_cnt--; 296 dst_buf->b->v4l2_buf.sequence = ctx->sequence; 297 if (s5p_mfc_hw_call(dev->mfc_ops, 298 get_pic_type_top, ctx) == 299 s5p_mfc_hw_call(dev->mfc_ops, 300 get_pic_type_bot, ctx)) 301 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 302 else 303 dst_buf->b->v4l2_buf.field = 304 V4L2_FIELD_INTERLACED; 305 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); 306 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); 307 clear_bit(dst_buf->b->v4l2_buf.index, 308 &ctx->dec_dst_flag); 309 310 vb2_buffer_done(dst_buf->b, 311 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 312 313 break; 314 } 315 } 316} 317 318/* Handle frame decoding interrupt */ 319static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, 320 unsigned int reason, unsigned int err) 321{ 322 struct s5p_mfc_dev *dev = ctx->dev; 323 unsigned int dst_frame_status; 324 struct s5p_mfc_buf *src_buf; 325 unsigned long flags; 326 unsigned int res_change; 327 328 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 329 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 330 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 331 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) 332 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; 333 mfc_debug(2, "Frame Status: %x\n", dst_frame_status); 334 if (ctx->state == MFCINST_RES_CHANGE_INIT) 335 ctx->state = MFCINST_RES_CHANGE_FLUSH; 336 if (res_change == S5P_FIMV_RES_INCREASE || 337 res_change == S5P_FIMV_RES_DECREASE) { 338 ctx->state = MFCINST_RES_CHANGE_INIT; 339 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 340 wake_up_ctx(ctx, reason, err); 341 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 342 BUG(); 343 s5p_mfc_clock_off(); 344 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 345 return; 346 } 347 if (ctx->dpb_flush_flag) 348 ctx->dpb_flush_flag = 0; 349 350 spin_lock_irqsave(&dev->irqlock, flags); 351 /* All frames remaining in the buffer have been extracted */ 352 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { 353 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { 354 s5p_mfc_handle_frame_all_extracted(ctx); 355 ctx->state = MFCINST_RES_CHANGE_END; 356 goto leave_handle_frame; 357 } else { 358 s5p_mfc_handle_frame_all_extracted(ctx); 359 } 360 } 361 362 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY || 363 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) 364 s5p_mfc_handle_frame_copy_time(ctx); 365 366 /* A frame has been decoded and is in the buffer */ 367 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || 368 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { 369 s5p_mfc_handle_frame_new(ctx, err); 370 } else { 371 mfc_debug(2, "No frame decode\n"); 372 } 373 /* Mark source buffer as complete */ 374 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 375 && !list_empty(&ctx->src_queue)) { 376 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 377 list); 378 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, 379 get_consumed_stream, dev); 380 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && 381 ctx->consumed_stream + STUFF_BYTE < 382 src_buf->b->v4l2_planes[0].bytesused) { 383 /* Run MFC again on the same buffer */ 384 mfc_debug(2, "Running again the same buffer\n"); 385 ctx->after_packed_pb = 1; 386 } else { 387 mfc_debug(2, "MFC needs next buffer\n"); 388 ctx->consumed_stream = 0; 389 list_del(&src_buf->list); 390 ctx->src_queue_cnt--; 391 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) 392 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); 393 else 394 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); 395 } 396 } 397leave_handle_frame: 398 spin_unlock_irqrestore(&dev->irqlock, flags); 399 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 400 || ctx->dst_queue_cnt < ctx->dpb_count) 401 clear_work_bit(ctx); 402 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 403 wake_up_ctx(ctx, reason, err); 404 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 405 BUG(); 406 s5p_mfc_clock_off(); 407 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 408} 409 410/* Error handling for interrupt */ 411static void s5p_mfc_handle_error(struct s5p_mfc_ctx *ctx, 412 unsigned int reason, unsigned int err) 413{ 414 struct s5p_mfc_dev *dev; 415 unsigned long flags; 416 417 /* If no context is available then all necessary 418 * processing has been done. */ 419 if (ctx == NULL) 420 return; 421 422 dev = ctx->dev; 423 mfc_err("Interrupt Error: %08x\n", err); 424 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 425 wake_up_dev(dev, reason, err); 426 427 /* Error recovery is dependent on the state of context */ 428 switch (ctx->state) { 429 case MFCINST_INIT: 430 /* This error had to happen while acquireing instance */ 431 case MFCINST_GOT_INST: 432 /* This error had to happen while parsing the header */ 433 case MFCINST_HEAD_PARSED: 434 /* This error had to happen while setting dst buffers */ 435 case MFCINST_RETURN_INST: 436 /* This error had to happen while releasing instance */ 437 clear_work_bit(ctx); 438 wake_up_ctx(ctx, reason, err); 439 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 440 BUG(); 441 s5p_mfc_clock_off(); 442 ctx->state = MFCINST_ERROR; 443 break; 444 case MFCINST_FINISHING: 445 case MFCINST_FINISHED: 446 case MFCINST_RUNNING: 447 /* It is higly probable that an error occured 448 * while decoding a frame */ 449 clear_work_bit(ctx); 450 ctx->state = MFCINST_ERROR; 451 /* Mark all dst buffers as having an error */ 452 spin_lock_irqsave(&dev->irqlock, flags); 453 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 454 &ctx->vq_dst); 455 /* Mark all src buffers as having an error */ 456 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 457 &ctx->vq_src); 458 spin_unlock_irqrestore(&dev->irqlock, flags); 459 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 460 BUG(); 461 s5p_mfc_clock_off(); 462 break; 463 default: 464 mfc_err("Encountered an error interrupt which had not been handled\n"); 465 break; 466 } 467 return; 468} 469 470/* Header parsing interrupt handling */ 471static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 472 unsigned int reason, unsigned int err) 473{ 474 struct s5p_mfc_dev *dev; 475 476 if (ctx == NULL) 477 return; 478 dev = ctx->dev; 479 if (ctx->c_ops->post_seq_start) { 480 if (ctx->c_ops->post_seq_start(ctx)) 481 mfc_err("post_seq_start() failed\n"); 482 } else { 483 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, 484 dev); 485 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 486 dev); 487 488 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); 489 490 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 491 dev); 492 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, 493 dev); 494 if (ctx->img_width == 0 || ctx->img_height == 0) 495 ctx->state = MFCINST_ERROR; 496 else 497 ctx->state = MFCINST_HEAD_PARSED; 498 499 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 500 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && 501 !list_empty(&ctx->src_queue)) { 502 struct s5p_mfc_buf *src_buf; 503 src_buf = list_entry(ctx->src_queue.next, 504 struct s5p_mfc_buf, list); 505 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, 506 dev) < 507 src_buf->b->v4l2_planes[0].bytesused) 508 ctx->head_processed = 0; 509 else 510 ctx->head_processed = 1; 511 } else { 512 ctx->head_processed = 1; 513 } 514 } 515 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 516 clear_work_bit(ctx); 517 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 518 BUG(); 519 s5p_mfc_clock_off(); 520 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 521 wake_up_ctx(ctx, reason, err); 522} 523 524/* Header parsing interrupt handling */ 525static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, 526 unsigned int reason, unsigned int err) 527{ 528 struct s5p_mfc_buf *src_buf; 529 struct s5p_mfc_dev *dev; 530 unsigned long flags; 531 532 if (ctx == NULL) 533 return; 534 dev = ctx->dev; 535 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 536 ctx->int_type = reason; 537 ctx->int_err = err; 538 ctx->int_cond = 1; 539 clear_work_bit(ctx); 540 if (err == 0) { 541 ctx->state = MFCINST_RUNNING; 542 if (!ctx->dpb_flush_flag && ctx->head_processed) { 543 spin_lock_irqsave(&dev->irqlock, flags); 544 if (!list_empty(&ctx->src_queue)) { 545 src_buf = list_entry(ctx->src_queue.next, 546 struct s5p_mfc_buf, list); 547 list_del(&src_buf->list); 548 ctx->src_queue_cnt--; 549 vb2_buffer_done(src_buf->b, 550 VB2_BUF_STATE_DONE); 551 } 552 spin_unlock_irqrestore(&dev->irqlock, flags); 553 } else { 554 ctx->dpb_flush_flag = 0; 555 } 556 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 557 BUG(); 558 559 s5p_mfc_clock_off(); 560 561 wake_up(&ctx->queue); 562 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 563 } else { 564 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 565 BUG(); 566 567 s5p_mfc_clock_off(); 568 569 wake_up(&ctx->queue); 570 } 571} 572 573static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, 574 unsigned int reason, unsigned int err) 575{ 576 struct s5p_mfc_dev *dev = ctx->dev; 577 struct s5p_mfc_buf *mb_entry; 578 579 mfc_debug(2, "Stream completed"); 580 581 s5p_mfc_clear_int_flags(dev); 582 ctx->int_type = reason; 583 ctx->int_err = err; 584 ctx->state = MFCINST_FINISHED; 585 586 spin_lock(&dev->irqlock); 587 if (!list_empty(&ctx->dst_queue)) { 588 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, 589 list); 590 list_del(&mb_entry->list); 591 ctx->dst_queue_cnt--; 592 vb2_set_plane_payload(mb_entry->b, 0, 0); 593 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE); 594 } 595 spin_unlock(&dev->irqlock); 596 597 clear_work_bit(ctx); 598 599 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 600 WARN_ON(1); 601 602 s5p_mfc_clock_off(); 603 wake_up(&ctx->queue); 604 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 605} 606 607/* Interrupt processing */ 608static irqreturn_t s5p_mfc_irq(int irq, void *priv) 609{ 610 struct s5p_mfc_dev *dev = priv; 611 struct s5p_mfc_ctx *ctx; 612 unsigned int reason; 613 unsigned int err; 614 615 mfc_debug_enter(); 616 /* Reset the timeout watchdog */ 617 atomic_set(&dev->watchdog_cnt, 0); 618 ctx = dev->ctx[dev->curr_ctx]; 619 /* Get the reason of interrupt and the error code */ 620 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); 621 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); 622 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); 623 switch (reason) { 624 case S5P_MFC_R2H_CMD_ERR_RET: 625 /* An error has occured */ 626 if (ctx->state == MFCINST_RUNNING && 627 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= 628 dev->warn_start) 629 s5p_mfc_handle_frame(ctx, reason, err); 630 else 631 s5p_mfc_handle_error(ctx, reason, err); 632 clear_bit(0, &dev->enter_suspend); 633 break; 634 635 case S5P_MFC_R2H_CMD_SLICE_DONE_RET: 636 case S5P_MFC_R2H_CMD_FIELD_DONE_RET: 637 case S5P_MFC_R2H_CMD_FRAME_DONE_RET: 638 if (ctx->c_ops->post_frame_start) { 639 if (ctx->c_ops->post_frame_start(ctx)) 640 mfc_err("post_frame_start() failed\n"); 641 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 642 wake_up_ctx(ctx, reason, err); 643 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 644 BUG(); 645 s5p_mfc_clock_off(); 646 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 647 } else { 648 s5p_mfc_handle_frame(ctx, reason, err); 649 } 650 break; 651 652 case S5P_MFC_R2H_CMD_SEQ_DONE_RET: 653 s5p_mfc_handle_seq_done(ctx, reason, err); 654 break; 655 656 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: 657 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); 658 ctx->state = MFCINST_GOT_INST; 659 clear_work_bit(ctx); 660 wake_up(&ctx->queue); 661 goto irq_cleanup_hw; 662 663 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: 664 clear_work_bit(ctx); 665 ctx->state = MFCINST_FREE; 666 wake_up(&ctx->queue); 667 goto irq_cleanup_hw; 668 669 case S5P_MFC_R2H_CMD_SYS_INIT_RET: 670 case S5P_MFC_R2H_CMD_FW_STATUS_RET: 671 case S5P_MFC_R2H_CMD_SLEEP_RET: 672 case S5P_MFC_R2H_CMD_WAKEUP_RET: 673 if (ctx) 674 clear_work_bit(ctx); 675 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 676 wake_up_dev(dev, reason, err); 677 clear_bit(0, &dev->hw_lock); 678 clear_bit(0, &dev->enter_suspend); 679 break; 680 681 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: 682 s5p_mfc_handle_init_buffers(ctx, reason, err); 683 break; 684 685 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: 686 s5p_mfc_handle_stream_complete(ctx, reason, err); 687 break; 688 689 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET: 690 clear_work_bit(ctx); 691 ctx->state = MFCINST_RUNNING; 692 wake_up(&ctx->queue); 693 goto irq_cleanup_hw; 694 695 default: 696 mfc_debug(2, "Unknown int reason\n"); 697 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 698 } 699 mfc_debug_leave(); 700 return IRQ_HANDLED; 701irq_cleanup_hw: 702 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 703 ctx->int_type = reason; 704 ctx->int_err = err; 705 ctx->int_cond = 1; 706 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 707 mfc_err("Failed to unlock hw\n"); 708 709 s5p_mfc_clock_off(); 710 711 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 712 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 713 return IRQ_HANDLED; 714} 715 716/* Open an MFC node */ 717static int s5p_mfc_open(struct file *file) 718{ 719 struct s5p_mfc_dev *dev = video_drvdata(file); 720 struct s5p_mfc_ctx *ctx = NULL; 721 struct vb2_queue *q; 722 int ret = 0; 723 724 mfc_debug_enter(); 725 if (mutex_lock_interruptible(&dev->mfc_mutex)) 726 return -ERESTARTSYS; 727 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ 728 /* Allocate memory for context */ 729 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 730 if (!ctx) { 731 mfc_err("Not enough memory\n"); 732 ret = -ENOMEM; 733 goto err_alloc; 734 } 735 v4l2_fh_init(&ctx->fh, video_devdata(file)); 736 file->private_data = &ctx->fh; 737 v4l2_fh_add(&ctx->fh); 738 ctx->dev = dev; 739 INIT_LIST_HEAD(&ctx->src_queue); 740 INIT_LIST_HEAD(&ctx->dst_queue); 741 ctx->src_queue_cnt = 0; 742 ctx->dst_queue_cnt = 0; 743 /* Get context number */ 744 ctx->num = 0; 745 while (dev->ctx[ctx->num]) { 746 ctx->num++; 747 if (ctx->num >= MFC_NUM_CONTEXTS) { 748 mfc_err("Too many open contexts\n"); 749 ret = -EBUSY; 750 goto err_no_ctx; 751 } 752 } 753 /* Mark context as idle */ 754 clear_work_bit_irqsave(ctx); 755 dev->ctx[ctx->num] = ctx; 756 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 757 ctx->type = MFCINST_DECODER; 758 ctx->c_ops = get_dec_codec_ops(); 759 s5p_mfc_dec_init(ctx); 760 /* Setup ctrl handler */ 761 ret = s5p_mfc_dec_ctrls_setup(ctx); 762 if (ret) { 763 mfc_err("Failed to setup mfc controls\n"); 764 goto err_ctrls_setup; 765 } 766 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 767 ctx->type = MFCINST_ENCODER; 768 ctx->c_ops = get_enc_codec_ops(); 769 /* only for encoder */ 770 INIT_LIST_HEAD(&ctx->ref_queue); 771 ctx->ref_queue_cnt = 0; 772 s5p_mfc_enc_init(ctx); 773 /* Setup ctrl handler */ 774 ret = s5p_mfc_enc_ctrls_setup(ctx); 775 if (ret) { 776 mfc_err("Failed to setup mfc controls\n"); 777 goto err_ctrls_setup; 778 } 779 } else { 780 ret = -ENOENT; 781 goto err_bad_node; 782 } 783 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 784 ctx->inst_no = -1; 785 /* Load firmware if this is the first instance */ 786 if (dev->num_inst == 1) { 787 dev->watchdog_timer.expires = jiffies + 788 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 789 add_timer(&dev->watchdog_timer); 790 ret = s5p_mfc_power_on(); 791 if (ret < 0) { 792 mfc_err("power on failed\n"); 793 goto err_pwr_enable; 794 } 795 s5p_mfc_clock_on(); 796 ret = s5p_mfc_alloc_and_load_firmware(dev); 797 if (ret) 798 goto err_alloc_fw; 799 /* Init the FW */ 800 ret = s5p_mfc_init_hw(dev); 801 if (ret) 802 goto err_init_hw; 803 s5p_mfc_clock_off(); 804 } 805 /* Init videobuf2 queue for CAPTURE */ 806 q = &ctx->vq_dst; 807 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 808 q->drv_priv = &ctx->fh; 809 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 810 q->io_modes = VB2_MMAP; 811 q->ops = get_dec_queue_ops(); 812 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 813 q->io_modes = VB2_MMAP | VB2_USERPTR; 814 q->ops = get_enc_queue_ops(); 815 } else { 816 ret = -ENOENT; 817 goto err_queue_init; 818 } 819 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 820 ret = vb2_queue_init(q); 821 if (ret) { 822 mfc_err("Failed to initialize videobuf2 queue(capture)\n"); 823 goto err_queue_init; 824 } 825 /* Init videobuf2 queue for OUTPUT */ 826 q = &ctx->vq_src; 827 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 828 q->io_modes = VB2_MMAP; 829 q->drv_priv = &ctx->fh; 830 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 831 q->io_modes = VB2_MMAP; 832 q->ops = get_dec_queue_ops(); 833 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 834 q->io_modes = VB2_MMAP | VB2_USERPTR; 835 q->ops = get_enc_queue_ops(); 836 } else { 837 ret = -ENOENT; 838 goto err_queue_init; 839 } 840 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 841 ret = vb2_queue_init(q); 842 if (ret) { 843 mfc_err("Failed to initialize videobuf2 queue(output)\n"); 844 goto err_queue_init; 845 } 846 init_waitqueue_head(&ctx->queue); 847 mutex_unlock(&dev->mfc_mutex); 848 mfc_debug_leave(); 849 return ret; 850 /* Deinit when failure occured */ 851err_queue_init: 852err_init_hw: 853 s5p_mfc_release_firmware(dev); 854err_alloc_fw: 855 dev->ctx[ctx->num] = NULL; 856 del_timer_sync(&dev->watchdog_timer); 857 s5p_mfc_clock_off(); 858err_pwr_enable: 859 if (dev->num_inst == 1) { 860 if (s5p_mfc_power_off() < 0) 861 mfc_err("power off failed\n"); 862 s5p_mfc_release_firmware(dev); 863 } 864err_ctrls_setup: 865 s5p_mfc_dec_ctrls_delete(ctx); 866err_bad_node: 867err_no_ctx: 868 v4l2_fh_del(&ctx->fh); 869 v4l2_fh_exit(&ctx->fh); 870 kfree(ctx); 871err_alloc: 872 dev->num_inst--; 873 mutex_unlock(&dev->mfc_mutex); 874 mfc_debug_leave(); 875 return ret; 876} 877 878/* Release MFC context */ 879static int s5p_mfc_release(struct file *file) 880{ 881 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 882 struct s5p_mfc_dev *dev = ctx->dev; 883 884 mfc_debug_enter(); 885 mutex_lock(&dev->mfc_mutex); 886 s5p_mfc_clock_on(); 887 vb2_queue_release(&ctx->vq_src); 888 vb2_queue_release(&ctx->vq_dst); 889 /* Mark context as idle */ 890 clear_work_bit_irqsave(ctx); 891 /* If instance was initialised then 892 * return instance and free reosurces */ 893 if (ctx->inst_no != MFC_NO_INSTANCE_SET) { 894 mfc_debug(2, "Has to free instance\n"); 895 ctx->state = MFCINST_RETURN_INST; 896 set_work_bit_irqsave(ctx); 897 s5p_mfc_clean_ctx_int_flags(ctx); 898 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 899 /* Wait until instance is returned or timeout occured */ 900 if (s5p_mfc_wait_for_done_ctx 901 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) { 902 s5p_mfc_clock_off(); 903 mfc_err("Err returning instance\n"); 904 } 905 mfc_debug(2, "After free instance\n"); 906 /* Free resources */ 907 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); 908 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); 909 if (ctx->type == MFCINST_DECODER) 910 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, 911 ctx); 912 913 ctx->inst_no = MFC_NO_INSTANCE_SET; 914 } 915 /* hardware locking scheme */ 916 if (dev->curr_ctx == ctx->num) 917 clear_bit(0, &dev->hw_lock); 918 dev->num_inst--; 919 if (dev->num_inst == 0) { 920 mfc_debug(2, "Last instance - release firmware\n"); 921 /* reset <-> F/W release */ 922 s5p_mfc_reset(dev); 923 s5p_mfc_deinit_hw(dev); 924 s5p_mfc_release_firmware(dev); 925 del_timer_sync(&dev->watchdog_timer); 926 if (s5p_mfc_power_off() < 0) 927 mfc_err("Power off failed\n"); 928 } 929 mfc_debug(2, "Shutting down clock\n"); 930 s5p_mfc_clock_off(); 931 dev->ctx[ctx->num] = NULL; 932 s5p_mfc_dec_ctrls_delete(ctx); 933 v4l2_fh_del(&ctx->fh); 934 v4l2_fh_exit(&ctx->fh); 935 kfree(ctx); 936 mfc_debug_leave(); 937 mutex_unlock(&dev->mfc_mutex); 938 return 0; 939} 940 941/* Poll */ 942static unsigned int s5p_mfc_poll(struct file *file, 943 struct poll_table_struct *wait) 944{ 945 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 946 struct s5p_mfc_dev *dev = ctx->dev; 947 struct vb2_queue *src_q, *dst_q; 948 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; 949 unsigned int rc = 0; 950 unsigned long flags; 951 952 mutex_lock(&dev->mfc_mutex); 953 src_q = &ctx->vq_src; 954 dst_q = &ctx->vq_dst; 955 /* 956 * There has to be at least one buffer queued on each queued_list, which 957 * means either in driver already or waiting for driver to claim it 958 * and start processing. 959 */ 960 if ((!src_q->streaming || list_empty(&src_q->queued_list)) 961 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { 962 rc = POLLERR; 963 goto end; 964 } 965 mutex_unlock(&dev->mfc_mutex); 966 poll_wait(file, &ctx->fh.wait, wait); 967 poll_wait(file, &src_q->done_wq, wait); 968 poll_wait(file, &dst_q->done_wq, wait); 969 mutex_lock(&dev->mfc_mutex); 970 if (v4l2_event_pending(&ctx->fh)) 971 rc |= POLLPRI; 972 spin_lock_irqsave(&src_q->done_lock, flags); 973 if (!list_empty(&src_q->done_list)) 974 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, 975 done_entry); 976 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE 977 || src_vb->state == VB2_BUF_STATE_ERROR)) 978 rc |= POLLOUT | POLLWRNORM; 979 spin_unlock_irqrestore(&src_q->done_lock, flags); 980 spin_lock_irqsave(&dst_q->done_lock, flags); 981 if (!list_empty(&dst_q->done_list)) 982 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, 983 done_entry); 984 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE 985 || dst_vb->state == VB2_BUF_STATE_ERROR)) 986 rc |= POLLIN | POLLRDNORM; 987 spin_unlock_irqrestore(&dst_q->done_lock, flags); 988end: 989 mutex_unlock(&dev->mfc_mutex); 990 return rc; 991} 992 993/* Mmap */ 994static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) 995{ 996 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 997 struct s5p_mfc_dev *dev = ctx->dev; 998 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 999 int ret; 1000 1001 if (mutex_lock_interruptible(&dev->mfc_mutex)) 1002 return -ERESTARTSYS; 1003 if (offset < DST_QUEUE_OFF_BASE) { 1004 mfc_debug(2, "mmaping source\n"); 1005 ret = vb2_mmap(&ctx->vq_src, vma); 1006 } else { /* capture */ 1007 mfc_debug(2, "mmaping destination\n"); 1008 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); 1009 ret = vb2_mmap(&ctx->vq_dst, vma); 1010 } 1011 mutex_unlock(&dev->mfc_mutex); 1012 return ret; 1013} 1014 1015/* v4l2 ops */ 1016static const struct v4l2_file_operations s5p_mfc_fops = { 1017 .owner = THIS_MODULE, 1018 .open = s5p_mfc_open, 1019 .release = s5p_mfc_release, 1020 .poll = s5p_mfc_poll, 1021 .unlocked_ioctl = video_ioctl2, 1022 .mmap = s5p_mfc_mmap, 1023}; 1024 1025static int match_child(struct device *dev, void *data) 1026{ 1027 if (!dev_name(dev)) 1028 return 0; 1029 return !strcmp(dev_name(dev), (char *)data); 1030} 1031 1032static void *mfc_get_drv_data(struct platform_device *pdev); 1033 1034/* MFC probe function */ 1035static int s5p_mfc_probe(struct platform_device *pdev) 1036{ 1037 struct s5p_mfc_dev *dev; 1038 struct video_device *vfd; 1039 struct resource *res; 1040 int ret; 1041 unsigned int mem_info[2]; 1042 1043 pr_debug("%s++\n", __func__); 1044 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1045 if (!dev) { 1046 dev_err(&pdev->dev, "Not enough memory for MFC device\n"); 1047 return -ENOMEM; 1048 } 1049 1050 spin_lock_init(&dev->irqlock); 1051 spin_lock_init(&dev->condlock); 1052 dev->plat_dev = pdev; 1053 if (!dev->plat_dev) { 1054 dev_err(&pdev->dev, "No platform data specified\n"); 1055 return -ENODEV; 1056 } 1057 1058 dev->variant = mfc_get_drv_data(pdev); 1059 1060 ret = s5p_mfc_init_pm(dev); 1061 if (ret < 0) { 1062 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 1063 return ret; 1064 } 1065 1066 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1067 1068 dev->regs_base = devm_request_and_ioremap(&pdev->dev, res); 1069 if (dev->regs_base == NULL) { 1070 dev_err(&pdev->dev, "Failed to obtain io memory\n"); 1071 return -ENOENT; 1072 } 1073 1074 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1075 if (res == NULL) { 1076 dev_err(&pdev->dev, "failed to get irq resource\n"); 1077 ret = -ENOENT; 1078 goto err_res; 1079 } 1080 dev->irq = res->start; 1081 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, 1082 IRQF_DISABLED, pdev->name, dev); 1083 if (ret) { 1084 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); 1085 goto err_res; 1086 } 1087 1088 if (pdev->dev.of_node) { 1089 dev->mem_dev_l = kzalloc(sizeof(struct device), GFP_KERNEL); 1090 if (!dev->mem_dev_l) { 1091 mfc_err("Not enough memory\n"); 1092 ret = -ENOMEM; 1093 goto err_res; 1094 } 1095 of_property_read_u32_array(pdev->dev.of_node, "samsung,mfc-l", 1096 mem_info, 2); 1097 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0], 1098 mem_info[0], mem_info[1], 1099 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1100 mfc_err("Failed to declare coherent memory for\n" 1101 "MFC device\n"); 1102 ret = -ENOMEM; 1103 goto err_res; 1104 } 1105 1106 dev->mem_dev_r = kzalloc(sizeof(struct device), GFP_KERNEL); 1107 if (!dev->mem_dev_r) { 1108 mfc_err("Not enough memory\n"); 1109 ret = -ENOMEM; 1110 goto err_res; 1111 } 1112 of_property_read_u32_array(pdev->dev.of_node, "samsung,mfc-r", 1113 mem_info, 2); 1114 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0], 1115 mem_info[0], mem_info[1], 1116 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1117 pr_err("Failed to declare coherent memory for\n" 1118 "MFC device\n"); 1119 ret = -ENOMEM; 1120 goto err_res; 1121 } 1122 } else { 1123 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, 1124 "s5p-mfc-l", match_child); 1125 if (!dev->mem_dev_l) { 1126 mfc_err("Mem child (L) device get failed\n"); 1127 ret = -ENODEV; 1128 goto err_res; 1129 } 1130 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, 1131 "s5p-mfc-r", match_child); 1132 if (!dev->mem_dev_r) { 1133 mfc_err("Mem child (R) device get failed\n"); 1134 ret = -ENODEV; 1135 goto err_res; 1136 } 1137 } 1138 1139 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); 1140 if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) { 1141 ret = PTR_ERR(dev->alloc_ctx[0]); 1142 goto err_res; 1143 } 1144 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); 1145 if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) { 1146 ret = PTR_ERR(dev->alloc_ctx[1]); 1147 goto err_mem_init_ctx_1; 1148 } 1149 1150 mutex_init(&dev->mfc_mutex); 1151 1152 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 1153 if (ret) 1154 goto err_v4l2_dev_reg; 1155 init_waitqueue_head(&dev->queue); 1156 1157 /* decoder */ 1158 vfd = video_device_alloc(); 1159 if (!vfd) { 1160 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1161 ret = -ENOMEM; 1162 goto err_dec_alloc; 1163 } 1164 vfd->fops = &s5p_mfc_fops, 1165 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); 1166 vfd->release = video_device_release, 1167 vfd->lock = &dev->mfc_mutex; 1168 vfd->v4l2_dev = &dev->v4l2_dev; 1169 vfd->vfl_dir = VFL_DIR_M2M; 1170 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); 1171 dev->vfd_dec = vfd; 1172 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1173 if (ret) { 1174 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1175 video_device_release(vfd); 1176 goto err_dec_reg; 1177 } 1178 v4l2_info(&dev->v4l2_dev, 1179 "decoder registered as /dev/video%d\n", vfd->num); 1180 video_set_drvdata(vfd, dev); 1181 1182 /* encoder */ 1183 vfd = video_device_alloc(); 1184 if (!vfd) { 1185 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1186 ret = -ENOMEM; 1187 goto err_enc_alloc; 1188 } 1189 vfd->fops = &s5p_mfc_fops, 1190 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); 1191 vfd->release = video_device_release, 1192 vfd->lock = &dev->mfc_mutex; 1193 vfd->v4l2_dev = &dev->v4l2_dev; 1194 vfd->vfl_dir = VFL_DIR_M2M; 1195 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); 1196 dev->vfd_enc = vfd; 1197 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1198 if (ret) { 1199 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1200 video_device_release(vfd); 1201 goto err_enc_reg; 1202 } 1203 v4l2_info(&dev->v4l2_dev, 1204 "encoder registered as /dev/video%d\n", vfd->num); 1205 video_set_drvdata(vfd, dev); 1206 platform_set_drvdata(pdev, dev); 1207 1208 dev->hw_lock = 0; 1209 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); 1210 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); 1211 atomic_set(&dev->watchdog_cnt, 0); 1212 init_timer(&dev->watchdog_timer); 1213 dev->watchdog_timer.data = (unsigned long)dev; 1214 dev->watchdog_timer.function = s5p_mfc_watchdog; 1215 1216 /* Initialize HW ops and commands based on MFC version */ 1217 s5p_mfc_init_hw_ops(dev); 1218 s5p_mfc_init_hw_cmds(dev); 1219 1220 pr_debug("%s--\n", __func__); 1221 return 0; 1222 1223/* Deinit MFC if probe had failed */ 1224err_enc_reg: 1225 video_device_release(dev->vfd_enc); 1226err_enc_alloc: 1227 video_unregister_device(dev->vfd_dec); 1228err_dec_reg: 1229 video_device_release(dev->vfd_dec); 1230err_dec_alloc: 1231 v4l2_device_unregister(&dev->v4l2_dev); 1232err_v4l2_dev_reg: 1233 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1234err_mem_init_ctx_1: 1235 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1236err_res: 1237 s5p_mfc_final_pm(dev); 1238 1239 pr_debug("%s-- with error\n", __func__); 1240 return ret; 1241 1242} 1243 1244/* Remove the driver */ 1245static int __devexit s5p_mfc_remove(struct platform_device *pdev) 1246{ 1247 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); 1248 1249 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); 1250 1251 del_timer_sync(&dev->watchdog_timer); 1252 flush_workqueue(dev->watchdog_workqueue); 1253 destroy_workqueue(dev->watchdog_workqueue); 1254 1255 video_unregister_device(dev->vfd_enc); 1256 video_unregister_device(dev->vfd_dec); 1257 v4l2_device_unregister(&dev->v4l2_dev); 1258 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1259 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1260 1261 s5p_mfc_final_pm(dev); 1262 return 0; 1263} 1264 1265#ifdef CONFIG_PM_SLEEP 1266 1267static int s5p_mfc_suspend(struct device *dev) 1268{ 1269 struct platform_device *pdev = to_platform_device(dev); 1270 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1271 int ret; 1272 1273 if (m_dev->num_inst == 0) 1274 return 0; 1275 1276 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { 1277 mfc_err("Error: going to suspend for a second time\n"); 1278 return -EIO; 1279 } 1280 1281 /* Check if we're processing then wait if it necessary. */ 1282 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { 1283 /* Try and lock the HW */ 1284 /* Wait on the interrupt waitqueue */ 1285 ret = wait_event_interruptible_timeout(m_dev->queue, 1286 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond, 1287 msecs_to_jiffies(MFC_INT_TIMEOUT)); 1288 1289 if (ret == 0) { 1290 mfc_err("Waiting for hardware to finish timed out\n"); 1291 return -EIO; 1292 } 1293 } 1294 1295 return s5p_mfc_sleep(m_dev); 1296} 1297 1298static int s5p_mfc_resume(struct device *dev) 1299{ 1300 struct platform_device *pdev = to_platform_device(dev); 1301 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1302 1303 if (m_dev->num_inst == 0) 1304 return 0; 1305 return s5p_mfc_wakeup(m_dev); 1306} 1307#endif 1308 1309#ifdef CONFIG_PM_RUNTIME 1310static int s5p_mfc_runtime_suspend(struct device *dev) 1311{ 1312 struct platform_device *pdev = to_platform_device(dev); 1313 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1314 1315 atomic_set(&m_dev->pm.power, 0); 1316 return 0; 1317} 1318 1319static int s5p_mfc_runtime_resume(struct device *dev) 1320{ 1321 struct platform_device *pdev = to_platform_device(dev); 1322 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1323 int pre_power; 1324 1325 if (!m_dev->alloc_ctx) 1326 return 0; 1327 pre_power = atomic_read(&m_dev->pm.power); 1328 atomic_set(&m_dev->pm.power, 1); 1329 return 0; 1330} 1331#endif 1332 1333/* Power management */ 1334static const struct dev_pm_ops s5p_mfc_pm_ops = { 1335 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) 1336 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, 1337 NULL) 1338}; 1339 1340struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { 1341 .h264_ctx = MFC_H264_CTX_BUF_SIZE, 1342 .non_h264_ctx = MFC_CTX_BUF_SIZE, 1343 .dsc = DESC_BUF_SIZE, 1344 .shm = SHARED_BUF_SIZE, 1345}; 1346 1347struct s5p_mfc_buf_size buf_size_v5 = { 1348 .fw = MAX_FW_SIZE, 1349 .cpb = MAX_CPB_SIZE, 1350 .priv = &mfc_buf_size_v5, 1351}; 1352 1353struct s5p_mfc_buf_align mfc_buf_align_v5 = { 1354 .base = MFC_BASE_ALIGN_ORDER, 1355}; 1356 1357static struct s5p_mfc_variant mfc_drvdata_v5 = { 1358 .version = MFC_VERSION, 1359 .port_num = MFC_NUM_PORTS, 1360 .buf_size = &buf_size_v5, 1361 .buf_align = &mfc_buf_align_v5, 1362 .mclk_name = "sclk_mfc", 1363 .fw_name = "s5p-mfc.fw", 1364}; 1365 1366struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { 1367 .dev_ctx = MFC_CTX_BUF_SIZE_V6, 1368 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, 1369 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, 1370 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, 1371 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, 1372}; 1373 1374struct s5p_mfc_buf_size buf_size_v6 = { 1375 .fw = MAX_FW_SIZE_V6, 1376 .cpb = MAX_CPB_SIZE_V6, 1377 .priv = &mfc_buf_size_v6, 1378}; 1379 1380struct s5p_mfc_buf_align mfc_buf_align_v6 = { 1381 .base = 0, 1382}; 1383 1384static struct s5p_mfc_variant mfc_drvdata_v6 = { 1385 .version = MFC_VERSION_V6, 1386 .port_num = MFC_NUM_PORTS_V6, 1387 .buf_size = &buf_size_v6, 1388 .buf_align = &mfc_buf_align_v6, 1389 .mclk_name = "aclk_333", 1390 .fw_name = "s5p-mfc-v6.fw", 1391}; 1392 1393static struct platform_device_id mfc_driver_ids[] = { 1394 { 1395 .name = "s5p-mfc", 1396 .driver_data = (unsigned long)&mfc_drvdata_v5, 1397 }, { 1398 .name = "s5p-mfc-v5", 1399 .driver_data = (unsigned long)&mfc_drvdata_v5, 1400 }, { 1401 .name = "s5p-mfc-v6", 1402 .driver_data = (unsigned long)&mfc_drvdata_v6, 1403 }, 1404 {}, 1405}; 1406MODULE_DEVICE_TABLE(platform, mfc_driver_ids); 1407 1408static const struct of_device_id exynos_mfc_match[] = { 1409 { 1410 .compatible = "samsung,mfc-v5", 1411 .data = &mfc_drvdata_v5, 1412 }, { 1413 .compatible = "samsung,mfc-v6", 1414 .data = &mfc_drvdata_v6, 1415 }, 1416 {}, 1417}; 1418MODULE_DEVICE_TABLE(of, exynos_mfc_match); 1419 1420static void *mfc_get_drv_data(struct platform_device *pdev) 1421{ 1422 struct s5p_mfc_variant *driver_data = NULL; 1423 1424 if (pdev->dev.of_node) { 1425 const struct of_device_id *match; 1426 match = of_match_node(of_match_ptr(exynos_mfc_match), 1427 pdev->dev.of_node); 1428 if (match) 1429 driver_data = (struct s5p_mfc_variant *)match->data; 1430 } else { 1431 driver_data = (struct s5p_mfc_variant *) 1432 platform_get_device_id(pdev)->driver_data; 1433 } 1434 return driver_data; 1435} 1436 1437static struct platform_driver s5p_mfc_driver = { 1438 .probe = s5p_mfc_probe, 1439 .remove = __devexit_p(s5p_mfc_remove), 1440 .id_table = mfc_driver_ids, 1441 .driver = { 1442 .name = S5P_MFC_NAME, 1443 .owner = THIS_MODULE, 1444 .pm = &s5p_mfc_pm_ops, 1445 .of_match_table = exynos_mfc_match, 1446 }, 1447}; 1448 1449module_platform_driver(s5p_mfc_driver); 1450 1451MODULE_LICENSE("GPL"); 1452MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); 1453MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); 1454 1455