s5p_mfc.c revision a0517f5d4d7e7366ae0354a9cecaadc3656a5f76
1/* 2 * Samsung S5P Multi Format Codec v 5.1 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Kamil Debski, <k.debski@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22#include <media/v4l2-event.h> 23#include <linux/workqueue.h> 24#include <linux/of.h> 25#include <media/videobuf2-core.h> 26#include "s5p_mfc_common.h" 27#include "s5p_mfc_ctrl.h" 28#include "s5p_mfc_debug.h" 29#include "s5p_mfc_dec.h" 30#include "s5p_mfc_enc.h" 31#include "s5p_mfc_intr.h" 32#include "s5p_mfc_opr.h" 33#include "s5p_mfc_cmd.h" 34#include "s5p_mfc_pm.h" 35 36#define S5P_MFC_NAME "s5p-mfc" 37#define S5P_MFC_DEC_NAME "s5p-mfc-dec" 38#define S5P_MFC_ENC_NAME "s5p-mfc-enc" 39 40int debug; 41module_param(debug, int, S_IRUGO | S_IWUSR); 42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); 43 44/* Helper functions for interrupt processing */ 45 46/* Remove from hw execution round robin */ 47void clear_work_bit(struct s5p_mfc_ctx *ctx) 48{ 49 struct s5p_mfc_dev *dev = ctx->dev; 50 51 spin_lock(&dev->condlock); 52 __clear_bit(ctx->num, &dev->ctx_work_bits); 53 spin_unlock(&dev->condlock); 54} 55 56/* Add to hw execution round robin */ 57void set_work_bit(struct s5p_mfc_ctx *ctx) 58{ 59 struct s5p_mfc_dev *dev = ctx->dev; 60 61 spin_lock(&dev->condlock); 62 __set_bit(ctx->num, &dev->ctx_work_bits); 63 spin_unlock(&dev->condlock); 64} 65 66/* Remove from hw execution round robin */ 67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 68{ 69 struct s5p_mfc_dev *dev = ctx->dev; 70 unsigned long flags; 71 72 spin_lock_irqsave(&dev->condlock, flags); 73 __clear_bit(ctx->num, &dev->ctx_work_bits); 74 spin_unlock_irqrestore(&dev->condlock, flags); 75} 76 77/* Add to hw execution round robin */ 78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 79{ 80 struct s5p_mfc_dev *dev = ctx->dev; 81 unsigned long flags; 82 83 spin_lock_irqsave(&dev->condlock, flags); 84 __set_bit(ctx->num, &dev->ctx_work_bits); 85 spin_unlock_irqrestore(&dev->condlock, flags); 86} 87 88/* Wake up context wait_queue */ 89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, 90 unsigned int err) 91{ 92 ctx->int_cond = 1; 93 ctx->int_type = reason; 94 ctx->int_err = err; 95 wake_up(&ctx->queue); 96} 97 98/* Wake up device wait_queue */ 99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, 100 unsigned int err) 101{ 102 dev->int_cond = 1; 103 dev->int_type = reason; 104 dev->int_err = err; 105 wake_up(&dev->queue); 106} 107 108static void s5p_mfc_watchdog(unsigned long arg) 109{ 110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; 111 112 if (test_bit(0, &dev->hw_lock)) 113 atomic_inc(&dev->watchdog_cnt); 114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { 115 /* This means that hw is busy and no interrupts were 116 * generated by hw for the Nth time of running this 117 * watchdog timer. This usually means a serious hw 118 * error. Now it is time to kill all instances and 119 * reset the MFC. */ 120 mfc_err("Time out during waiting for HW\n"); 121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work); 122 } 123 dev->watchdog_timer.expires = jiffies + 124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 125 add_timer(&dev->watchdog_timer); 126} 127 128static void s5p_mfc_watchdog_worker(struct work_struct *work) 129{ 130 struct s5p_mfc_dev *dev; 131 struct s5p_mfc_ctx *ctx; 132 unsigned long flags; 133 int mutex_locked; 134 int i, ret; 135 136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work); 137 138 mfc_err("Driver timeout error handling\n"); 139 /* Lock the mutex that protects open and release. 140 * This is necessary as they may load and unload firmware. */ 141 mutex_locked = mutex_trylock(&dev->mfc_mutex); 142 if (!mutex_locked) 143 mfc_err("Error: some instance may be closing/opening\n"); 144 spin_lock_irqsave(&dev->irqlock, flags); 145 146 s5p_mfc_clock_off(); 147 148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) { 149 ctx = dev->ctx[i]; 150 if (!ctx) 151 continue; 152 ctx->state = MFCINST_ERROR; 153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 154 &ctx->vq_dst); 155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 156 &ctx->vq_src); 157 clear_work_bit(ctx); 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); 159 } 160 clear_bit(0, &dev->hw_lock); 161 spin_unlock_irqrestore(&dev->irqlock, flags); 162 /* Double check if there is at least one instance running. 163 * If no instance is in memory than no firmware should be present */ 164 if (dev->num_inst > 0) { 165 ret = s5p_mfc_reload_firmware(dev); 166 if (ret) { 167 mfc_err("Failed to reload FW\n"); 168 goto unlock; 169 } 170 s5p_mfc_clock_on(); 171 ret = s5p_mfc_init_hw(dev); 172 if (ret) 173 mfc_err("Failed to reinit FW\n"); 174 } 175unlock: 176 if (mutex_locked) 177 mutex_unlock(&dev->mfc_mutex); 178} 179 180static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) 181{ 182 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 183 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 184 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 185} 186 187static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) 188{ 189 struct s5p_mfc_buf *dst_buf; 190 struct s5p_mfc_dev *dev = ctx->dev; 191 192 ctx->state = MFCINST_FINISHED; 193 ctx->sequence++; 194 while (!list_empty(&ctx->dst_queue)) { 195 dst_buf = list_entry(ctx->dst_queue.next, 196 struct s5p_mfc_buf, list); 197 mfc_debug(2, "Cleaning up buffer: %d\n", 198 dst_buf->b->v4l2_buf.index); 199 vb2_set_plane_payload(dst_buf->b, 0, 0); 200 vb2_set_plane_payload(dst_buf->b, 1, 0); 201 list_del(&dst_buf->list); 202 ctx->dst_queue_cnt--; 203 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); 204 205 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == 206 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) 207 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 208 else 209 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; 210 211 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); 212 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); 213 } 214} 215 216static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) 217{ 218 struct s5p_mfc_dev *dev = ctx->dev; 219 struct s5p_mfc_buf *dst_buf, *src_buf; 220 size_t dec_y_addr; 221 unsigned int frame_type; 222 223 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); 224 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 225 226 /* Copy timestamp / timecode from decoded src to dst and set 227 appropriate flags */ 228 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 229 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 230 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { 231 dst_buf->b->v4l2_buf.timecode = 232 src_buf->b->v4l2_buf.timecode; 233 dst_buf->b->v4l2_buf.timestamp = 234 src_buf->b->v4l2_buf.timestamp; 235 dst_buf->b->v4l2_buf.flags &= 236 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; 237 dst_buf->b->v4l2_buf.flags |= 238 src_buf->b->v4l2_buf.flags 239 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; 240 switch (frame_type) { 241 case S5P_FIMV_DECODE_FRAME_I_FRAME: 242 dst_buf->b->v4l2_buf.flags |= 243 V4L2_BUF_FLAG_KEYFRAME; 244 break; 245 case S5P_FIMV_DECODE_FRAME_P_FRAME: 246 dst_buf->b->v4l2_buf.flags |= 247 V4L2_BUF_FLAG_PFRAME; 248 break; 249 case S5P_FIMV_DECODE_FRAME_B_FRAME: 250 dst_buf->b->v4l2_buf.flags |= 251 V4L2_BUF_FLAG_BFRAME; 252 break; 253 } 254 break; 255 } 256 } 257} 258 259static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) 260{ 261 struct s5p_mfc_dev *dev = ctx->dev; 262 struct s5p_mfc_buf *dst_buf; 263 size_t dspl_y_addr; 264 unsigned int frame_type; 265 266 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); 267 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx); 268 269 /* If frame is same as previous then skip and do not dequeue */ 270 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { 271 if (!ctx->after_packed_pb) 272 ctx->sequence++; 273 ctx->after_packed_pb = 0; 274 return; 275 } 276 ctx->sequence++; 277 /* The MFC returns address of the buffer, now we have to 278 * check which videobuf does it correspond to */ 279 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 280 /* Check if this is the buffer we're looking for */ 281 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { 282 list_del(&dst_buf->list); 283 ctx->dst_queue_cnt--; 284 dst_buf->b->v4l2_buf.sequence = ctx->sequence; 285 if (s5p_mfc_hw_call(dev->mfc_ops, 286 get_pic_type_top, ctx) == 287 s5p_mfc_hw_call(dev->mfc_ops, 288 get_pic_type_bot, ctx)) 289 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 290 else 291 dst_buf->b->v4l2_buf.field = 292 V4L2_FIELD_INTERLACED; 293 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); 294 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); 295 clear_bit(dst_buf->b->v4l2_buf.index, 296 &ctx->dec_dst_flag); 297 298 vb2_buffer_done(dst_buf->b, 299 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 300 301 break; 302 } 303 } 304} 305 306/* Handle frame decoding interrupt */ 307static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, 308 unsigned int reason, unsigned int err) 309{ 310 struct s5p_mfc_dev *dev = ctx->dev; 311 unsigned int dst_frame_status; 312 unsigned int dec_frame_status; 313 struct s5p_mfc_buf *src_buf; 314 unsigned long flags; 315 unsigned int res_change; 316 317 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 318 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 319 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev) 320 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 321 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 322 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) 323 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; 324 mfc_debug(2, "Frame Status: %x\n", dst_frame_status); 325 if (ctx->state == MFCINST_RES_CHANGE_INIT) 326 ctx->state = MFCINST_RES_CHANGE_FLUSH; 327 if (res_change == S5P_FIMV_RES_INCREASE || 328 res_change == S5P_FIMV_RES_DECREASE) { 329 ctx->state = MFCINST_RES_CHANGE_INIT; 330 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 331 wake_up_ctx(ctx, reason, err); 332 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 333 BUG(); 334 s5p_mfc_clock_off(); 335 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 336 return; 337 } 338 if (ctx->dpb_flush_flag) 339 ctx->dpb_flush_flag = 0; 340 341 spin_lock_irqsave(&dev->irqlock, flags); 342 /* All frames remaining in the buffer have been extracted */ 343 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { 344 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { 345 s5p_mfc_handle_frame_all_extracted(ctx); 346 ctx->state = MFCINST_RES_CHANGE_END; 347 goto leave_handle_frame; 348 } else { 349 s5p_mfc_handle_frame_all_extracted(ctx); 350 } 351 } 352 353 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) 354 s5p_mfc_handle_frame_copy_time(ctx); 355 356 /* A frame has been decoded and is in the buffer */ 357 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || 358 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { 359 s5p_mfc_handle_frame_new(ctx, err); 360 } else { 361 mfc_debug(2, "No frame decode\n"); 362 } 363 /* Mark source buffer as complete */ 364 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 365 && !list_empty(&ctx->src_queue)) { 366 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 367 list); 368 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, 369 get_consumed_stream, dev); 370 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && 371 ctx->consumed_stream + STUFF_BYTE < 372 src_buf->b->v4l2_planes[0].bytesused) { 373 /* Run MFC again on the same buffer */ 374 mfc_debug(2, "Running again the same buffer\n"); 375 ctx->after_packed_pb = 1; 376 } else { 377 mfc_debug(2, "MFC needs next buffer\n"); 378 ctx->consumed_stream = 0; 379 if (src_buf->flags & MFC_BUF_FLAG_EOS) 380 ctx->state = MFCINST_FINISHING; 381 list_del(&src_buf->list); 382 ctx->src_queue_cnt--; 383 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) 384 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); 385 else 386 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); 387 } 388 } 389leave_handle_frame: 390 spin_unlock_irqrestore(&dev->irqlock, flags); 391 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 392 || ctx->dst_queue_cnt < ctx->pb_count) 393 clear_work_bit(ctx); 394 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 395 wake_up_ctx(ctx, reason, err); 396 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 397 BUG(); 398 s5p_mfc_clock_off(); 399 /* if suspending, wake up device and do not try_run again*/ 400 if (test_bit(0, &dev->enter_suspend)) 401 wake_up_dev(dev, reason, err); 402 else 403 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 404} 405 406/* Error handling for interrupt */ 407static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, 408 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) 409{ 410 unsigned long flags; 411 412 mfc_err("Interrupt Error: %08x\n", err); 413 414 if (ctx != NULL) { 415 /* Error recovery is dependent on the state of context */ 416 switch (ctx->state) { 417 case MFCINST_RES_CHANGE_INIT: 418 case MFCINST_RES_CHANGE_FLUSH: 419 case MFCINST_RES_CHANGE_END: 420 case MFCINST_FINISHING: 421 case MFCINST_FINISHED: 422 case MFCINST_RUNNING: 423 /* It is highly probable that an error occurred 424 * while decoding a frame */ 425 clear_work_bit(ctx); 426 ctx->state = MFCINST_ERROR; 427 /* Mark all dst buffers as having an error */ 428 spin_lock_irqsave(&dev->irqlock, flags); 429 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 430 &ctx->dst_queue, &ctx->vq_dst); 431 /* Mark all src buffers as having an error */ 432 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 433 &ctx->src_queue, &ctx->vq_src); 434 spin_unlock_irqrestore(&dev->irqlock, flags); 435 wake_up_ctx(ctx, reason, err); 436 break; 437 default: 438 clear_work_bit(ctx); 439 ctx->state = MFCINST_ERROR; 440 wake_up_ctx(ctx, reason, err); 441 break; 442 } 443 } 444 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 445 BUG(); 446 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 447 s5p_mfc_clock_off(); 448 wake_up_dev(dev, reason, err); 449 return; 450} 451 452/* Header parsing interrupt handling */ 453static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 454 unsigned int reason, unsigned int err) 455{ 456 struct s5p_mfc_dev *dev; 457 458 if (ctx == NULL) 459 return; 460 dev = ctx->dev; 461 if (ctx->c_ops->post_seq_start) { 462 if (ctx->c_ops->post_seq_start(ctx)) 463 mfc_err("post_seq_start() failed\n"); 464 } else { 465 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, 466 dev); 467 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 468 dev); 469 470 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); 471 472 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 473 dev); 474 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, 475 dev); 476 if (ctx->img_width == 0 || ctx->img_height == 0) 477 ctx->state = MFCINST_ERROR; 478 else 479 ctx->state = MFCINST_HEAD_PARSED; 480 481 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 482 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && 483 !list_empty(&ctx->src_queue)) { 484 struct s5p_mfc_buf *src_buf; 485 src_buf = list_entry(ctx->src_queue.next, 486 struct s5p_mfc_buf, list); 487 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, 488 dev) < 489 src_buf->b->v4l2_planes[0].bytesused) 490 ctx->head_processed = 0; 491 else 492 ctx->head_processed = 1; 493 } else { 494 ctx->head_processed = 1; 495 } 496 } 497 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 498 clear_work_bit(ctx); 499 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 500 BUG(); 501 s5p_mfc_clock_off(); 502 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 503 wake_up_ctx(ctx, reason, err); 504} 505 506/* Header parsing interrupt handling */ 507static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, 508 unsigned int reason, unsigned int err) 509{ 510 struct s5p_mfc_buf *src_buf; 511 struct s5p_mfc_dev *dev; 512 unsigned long flags; 513 514 if (ctx == NULL) 515 return; 516 dev = ctx->dev; 517 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 518 ctx->int_type = reason; 519 ctx->int_err = err; 520 ctx->int_cond = 1; 521 clear_work_bit(ctx); 522 if (err == 0) { 523 ctx->state = MFCINST_RUNNING; 524 if (!ctx->dpb_flush_flag && ctx->head_processed) { 525 spin_lock_irqsave(&dev->irqlock, flags); 526 if (!list_empty(&ctx->src_queue)) { 527 src_buf = list_entry(ctx->src_queue.next, 528 struct s5p_mfc_buf, list); 529 list_del(&src_buf->list); 530 ctx->src_queue_cnt--; 531 vb2_buffer_done(src_buf->b, 532 VB2_BUF_STATE_DONE); 533 } 534 spin_unlock_irqrestore(&dev->irqlock, flags); 535 } else { 536 ctx->dpb_flush_flag = 0; 537 } 538 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 539 BUG(); 540 541 s5p_mfc_clock_off(); 542 543 wake_up(&ctx->queue); 544 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 545 } else { 546 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 547 BUG(); 548 549 s5p_mfc_clock_off(); 550 551 wake_up(&ctx->queue); 552 } 553} 554 555static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, 556 unsigned int reason, unsigned int err) 557{ 558 struct s5p_mfc_dev *dev = ctx->dev; 559 struct s5p_mfc_buf *mb_entry; 560 561 mfc_debug(2, "Stream completed\n"); 562 563 s5p_mfc_clear_int_flags(dev); 564 ctx->int_type = reason; 565 ctx->int_err = err; 566 ctx->state = MFCINST_FINISHED; 567 568 spin_lock(&dev->irqlock); 569 if (!list_empty(&ctx->dst_queue)) { 570 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, 571 list); 572 list_del(&mb_entry->list); 573 ctx->dst_queue_cnt--; 574 vb2_set_plane_payload(mb_entry->b, 0, 0); 575 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE); 576 } 577 spin_unlock(&dev->irqlock); 578 579 clear_work_bit(ctx); 580 581 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); 582 583 s5p_mfc_clock_off(); 584 wake_up(&ctx->queue); 585 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 586} 587 588/* Interrupt processing */ 589static irqreturn_t s5p_mfc_irq(int irq, void *priv) 590{ 591 struct s5p_mfc_dev *dev = priv; 592 struct s5p_mfc_ctx *ctx; 593 unsigned int reason; 594 unsigned int err; 595 596 mfc_debug_enter(); 597 /* Reset the timeout watchdog */ 598 atomic_set(&dev->watchdog_cnt, 0); 599 ctx = dev->ctx[dev->curr_ctx]; 600 /* Get the reason of interrupt and the error code */ 601 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); 602 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); 603 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); 604 switch (reason) { 605 case S5P_MFC_R2H_CMD_ERR_RET: 606 /* An error has occurred */ 607 if (ctx->state == MFCINST_RUNNING && 608 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= 609 dev->warn_start) 610 s5p_mfc_handle_frame(ctx, reason, err); 611 else 612 s5p_mfc_handle_error(dev, ctx, reason, err); 613 clear_bit(0, &dev->enter_suspend); 614 break; 615 616 case S5P_MFC_R2H_CMD_SLICE_DONE_RET: 617 case S5P_MFC_R2H_CMD_FIELD_DONE_RET: 618 case S5P_MFC_R2H_CMD_FRAME_DONE_RET: 619 if (ctx->c_ops->post_frame_start) { 620 if (ctx->c_ops->post_frame_start(ctx)) 621 mfc_err("post_frame_start() failed\n"); 622 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 623 wake_up_ctx(ctx, reason, err); 624 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 625 BUG(); 626 s5p_mfc_clock_off(); 627 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 628 } else { 629 s5p_mfc_handle_frame(ctx, reason, err); 630 } 631 break; 632 633 case S5P_MFC_R2H_CMD_SEQ_DONE_RET: 634 s5p_mfc_handle_seq_done(ctx, reason, err); 635 break; 636 637 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: 638 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); 639 ctx->state = MFCINST_GOT_INST; 640 clear_work_bit(ctx); 641 wake_up(&ctx->queue); 642 goto irq_cleanup_hw; 643 644 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: 645 clear_work_bit(ctx); 646 ctx->state = MFCINST_FREE; 647 wake_up(&ctx->queue); 648 goto irq_cleanup_hw; 649 650 case S5P_MFC_R2H_CMD_SYS_INIT_RET: 651 case S5P_MFC_R2H_CMD_FW_STATUS_RET: 652 case S5P_MFC_R2H_CMD_SLEEP_RET: 653 case S5P_MFC_R2H_CMD_WAKEUP_RET: 654 if (ctx) 655 clear_work_bit(ctx); 656 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 657 wake_up_dev(dev, reason, err); 658 clear_bit(0, &dev->hw_lock); 659 clear_bit(0, &dev->enter_suspend); 660 break; 661 662 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: 663 s5p_mfc_handle_init_buffers(ctx, reason, err); 664 break; 665 666 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: 667 s5p_mfc_handle_stream_complete(ctx, reason, err); 668 break; 669 670 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET: 671 clear_work_bit(ctx); 672 ctx->state = MFCINST_RUNNING; 673 wake_up(&ctx->queue); 674 goto irq_cleanup_hw; 675 676 default: 677 mfc_debug(2, "Unknown int reason\n"); 678 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 679 } 680 mfc_debug_leave(); 681 return IRQ_HANDLED; 682irq_cleanup_hw: 683 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 684 ctx->int_type = reason; 685 ctx->int_err = err; 686 ctx->int_cond = 1; 687 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 688 mfc_err("Failed to unlock hw\n"); 689 690 s5p_mfc_clock_off(); 691 692 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 693 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 694 return IRQ_HANDLED; 695} 696 697/* Open an MFC node */ 698static int s5p_mfc_open(struct file *file) 699{ 700 struct video_device *vdev = video_devdata(file); 701 struct s5p_mfc_dev *dev = video_drvdata(file); 702 struct s5p_mfc_ctx *ctx = NULL; 703 struct vb2_queue *q; 704 int ret = 0; 705 706 mfc_debug_enter(); 707 if (mutex_lock_interruptible(&dev->mfc_mutex)) 708 return -ERESTARTSYS; 709 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ 710 /* Allocate memory for context */ 711 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 712 if (!ctx) { 713 mfc_err("Not enough memory\n"); 714 ret = -ENOMEM; 715 goto err_alloc; 716 } 717 v4l2_fh_init(&ctx->fh, video_devdata(file)); 718 file->private_data = &ctx->fh; 719 v4l2_fh_add(&ctx->fh); 720 ctx->dev = dev; 721 INIT_LIST_HEAD(&ctx->src_queue); 722 INIT_LIST_HEAD(&ctx->dst_queue); 723 ctx->src_queue_cnt = 0; 724 ctx->dst_queue_cnt = 0; 725 /* Get context number */ 726 ctx->num = 0; 727 while (dev->ctx[ctx->num]) { 728 ctx->num++; 729 if (ctx->num >= MFC_NUM_CONTEXTS) { 730 mfc_err("Too many open contexts\n"); 731 ret = -EBUSY; 732 goto err_no_ctx; 733 } 734 } 735 /* Mark context as idle */ 736 clear_work_bit_irqsave(ctx); 737 dev->ctx[ctx->num] = ctx; 738 if (vdev == dev->vfd_dec) { 739 ctx->type = MFCINST_DECODER; 740 ctx->c_ops = get_dec_codec_ops(); 741 s5p_mfc_dec_init(ctx); 742 /* Setup ctrl handler */ 743 ret = s5p_mfc_dec_ctrls_setup(ctx); 744 if (ret) { 745 mfc_err("Failed to setup mfc controls\n"); 746 goto err_ctrls_setup; 747 } 748 } else if (vdev == dev->vfd_enc) { 749 ctx->type = MFCINST_ENCODER; 750 ctx->c_ops = get_enc_codec_ops(); 751 /* only for encoder */ 752 INIT_LIST_HEAD(&ctx->ref_queue); 753 ctx->ref_queue_cnt = 0; 754 s5p_mfc_enc_init(ctx); 755 /* Setup ctrl handler */ 756 ret = s5p_mfc_enc_ctrls_setup(ctx); 757 if (ret) { 758 mfc_err("Failed to setup mfc controls\n"); 759 goto err_ctrls_setup; 760 } 761 } else { 762 ret = -ENOENT; 763 goto err_bad_node; 764 } 765 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 766 ctx->inst_no = -1; 767 /* Load firmware if this is the first instance */ 768 if (dev->num_inst == 1) { 769 dev->watchdog_timer.expires = jiffies + 770 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 771 add_timer(&dev->watchdog_timer); 772 ret = s5p_mfc_power_on(); 773 if (ret < 0) { 774 mfc_err("power on failed\n"); 775 goto err_pwr_enable; 776 } 777 s5p_mfc_clock_on(); 778 ret = s5p_mfc_load_firmware(dev); 779 if (ret) { 780 s5p_mfc_clock_off(); 781 goto err_load_fw; 782 } 783 /* Init the FW */ 784 ret = s5p_mfc_init_hw(dev); 785 s5p_mfc_clock_off(); 786 if (ret) 787 goto err_init_hw; 788 } 789 /* Init videobuf2 queue for CAPTURE */ 790 q = &ctx->vq_dst; 791 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 792 q->drv_priv = &ctx->fh; 793 if (vdev == dev->vfd_dec) { 794 q->io_modes = VB2_MMAP; 795 q->ops = get_dec_queue_ops(); 796 } else if (vdev == dev->vfd_enc) { 797 q->io_modes = VB2_MMAP | VB2_USERPTR; 798 q->ops = get_enc_queue_ops(); 799 } else { 800 ret = -ENOENT; 801 goto err_queue_init; 802 } 803 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 804 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 805 ret = vb2_queue_init(q); 806 if (ret) { 807 mfc_err("Failed to initialize videobuf2 queue(capture)\n"); 808 goto err_queue_init; 809 } 810 /* Init videobuf2 queue for OUTPUT */ 811 q = &ctx->vq_src; 812 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 813 q->io_modes = VB2_MMAP; 814 q->drv_priv = &ctx->fh; 815 if (vdev == dev->vfd_dec) { 816 q->io_modes = VB2_MMAP; 817 q->ops = get_dec_queue_ops(); 818 } else if (vdev == dev->vfd_enc) { 819 q->io_modes = VB2_MMAP | VB2_USERPTR; 820 q->ops = get_enc_queue_ops(); 821 } else { 822 ret = -ENOENT; 823 goto err_queue_init; 824 } 825 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 826 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 827 ret = vb2_queue_init(q); 828 if (ret) { 829 mfc_err("Failed to initialize videobuf2 queue(output)\n"); 830 goto err_queue_init; 831 } 832 init_waitqueue_head(&ctx->queue); 833 mutex_unlock(&dev->mfc_mutex); 834 mfc_debug_leave(); 835 return ret; 836 /* Deinit when failure occurred */ 837err_queue_init: 838 if (dev->num_inst == 1) 839 s5p_mfc_deinit_hw(dev); 840err_init_hw: 841err_load_fw: 842err_pwr_enable: 843 if (dev->num_inst == 1) { 844 if (s5p_mfc_power_off() < 0) 845 mfc_err("power off failed\n"); 846 del_timer_sync(&dev->watchdog_timer); 847 } 848err_ctrls_setup: 849 s5p_mfc_dec_ctrls_delete(ctx); 850err_bad_node: 851 dev->ctx[ctx->num] = NULL; 852err_no_ctx: 853 v4l2_fh_del(&ctx->fh); 854 v4l2_fh_exit(&ctx->fh); 855 kfree(ctx); 856err_alloc: 857 dev->num_inst--; 858 mutex_unlock(&dev->mfc_mutex); 859 mfc_debug_leave(); 860 return ret; 861} 862 863/* Release MFC context */ 864static int s5p_mfc_release(struct file *file) 865{ 866 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 867 struct s5p_mfc_dev *dev = ctx->dev; 868 869 mfc_debug_enter(); 870 mutex_lock(&dev->mfc_mutex); 871 s5p_mfc_clock_on(); 872 vb2_queue_release(&ctx->vq_src); 873 vb2_queue_release(&ctx->vq_dst); 874 /* Mark context as idle */ 875 clear_work_bit_irqsave(ctx); 876 /* If instance was initialised then 877 * return instance and free resources */ 878 if (ctx->inst_no != MFC_NO_INSTANCE_SET) { 879 mfc_debug(2, "Has to free instance\n"); 880 ctx->state = MFCINST_RETURN_INST; 881 set_work_bit_irqsave(ctx); 882 s5p_mfc_clean_ctx_int_flags(ctx); 883 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 884 /* Wait until instance is returned or timeout occurred */ 885 if (s5p_mfc_wait_for_done_ctx 886 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) { 887 s5p_mfc_clock_off(); 888 mfc_err("Err returning instance\n"); 889 } 890 mfc_debug(2, "After free instance\n"); 891 /* Free resources */ 892 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); 893 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); 894 if (ctx->type == MFCINST_DECODER) 895 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, 896 ctx); 897 898 ctx->inst_no = MFC_NO_INSTANCE_SET; 899 } 900 /* hardware locking scheme */ 901 if (dev->curr_ctx == ctx->num) 902 clear_bit(0, &dev->hw_lock); 903 dev->num_inst--; 904 if (dev->num_inst == 0) { 905 mfc_debug(2, "Last instance\n"); 906 s5p_mfc_deinit_hw(dev); 907 del_timer_sync(&dev->watchdog_timer); 908 if (s5p_mfc_power_off() < 0) 909 mfc_err("Power off failed\n"); 910 } 911 mfc_debug(2, "Shutting down clock\n"); 912 s5p_mfc_clock_off(); 913 dev->ctx[ctx->num] = NULL; 914 s5p_mfc_dec_ctrls_delete(ctx); 915 v4l2_fh_del(&ctx->fh); 916 v4l2_fh_exit(&ctx->fh); 917 kfree(ctx); 918 mfc_debug_leave(); 919 mutex_unlock(&dev->mfc_mutex); 920 return 0; 921} 922 923/* Poll */ 924static unsigned int s5p_mfc_poll(struct file *file, 925 struct poll_table_struct *wait) 926{ 927 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 928 struct s5p_mfc_dev *dev = ctx->dev; 929 struct vb2_queue *src_q, *dst_q; 930 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; 931 unsigned int rc = 0; 932 unsigned long flags; 933 934 mutex_lock(&dev->mfc_mutex); 935 src_q = &ctx->vq_src; 936 dst_q = &ctx->vq_dst; 937 /* 938 * There has to be at least one buffer queued on each queued_list, which 939 * means either in driver already or waiting for driver to claim it 940 * and start processing. 941 */ 942 if ((!src_q->streaming || list_empty(&src_q->queued_list)) 943 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { 944 rc = POLLERR; 945 goto end; 946 } 947 mutex_unlock(&dev->mfc_mutex); 948 poll_wait(file, &ctx->fh.wait, wait); 949 poll_wait(file, &src_q->done_wq, wait); 950 poll_wait(file, &dst_q->done_wq, wait); 951 mutex_lock(&dev->mfc_mutex); 952 if (v4l2_event_pending(&ctx->fh)) 953 rc |= POLLPRI; 954 spin_lock_irqsave(&src_q->done_lock, flags); 955 if (!list_empty(&src_q->done_list)) 956 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, 957 done_entry); 958 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE 959 || src_vb->state == VB2_BUF_STATE_ERROR)) 960 rc |= POLLOUT | POLLWRNORM; 961 spin_unlock_irqrestore(&src_q->done_lock, flags); 962 spin_lock_irqsave(&dst_q->done_lock, flags); 963 if (!list_empty(&dst_q->done_list)) 964 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, 965 done_entry); 966 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE 967 || dst_vb->state == VB2_BUF_STATE_ERROR)) 968 rc |= POLLIN | POLLRDNORM; 969 spin_unlock_irqrestore(&dst_q->done_lock, flags); 970end: 971 mutex_unlock(&dev->mfc_mutex); 972 return rc; 973} 974 975/* Mmap */ 976static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) 977{ 978 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 979 struct s5p_mfc_dev *dev = ctx->dev; 980 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 981 int ret; 982 983 if (mutex_lock_interruptible(&dev->mfc_mutex)) 984 return -ERESTARTSYS; 985 if (offset < DST_QUEUE_OFF_BASE) { 986 mfc_debug(2, "mmaping source\n"); 987 ret = vb2_mmap(&ctx->vq_src, vma); 988 } else { /* capture */ 989 mfc_debug(2, "mmaping destination\n"); 990 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); 991 ret = vb2_mmap(&ctx->vq_dst, vma); 992 } 993 mutex_unlock(&dev->mfc_mutex); 994 return ret; 995} 996 997/* v4l2 ops */ 998static const struct v4l2_file_operations s5p_mfc_fops = { 999 .owner = THIS_MODULE, 1000 .open = s5p_mfc_open, 1001 .release = s5p_mfc_release, 1002 .poll = s5p_mfc_poll, 1003 .unlocked_ioctl = video_ioctl2, 1004 .mmap = s5p_mfc_mmap, 1005}; 1006 1007static int match_child(struct device *dev, void *data) 1008{ 1009 if (!dev_name(dev)) 1010 return 0; 1011 return !strcmp(dev_name(dev), (char *)data); 1012} 1013 1014static void *mfc_get_drv_data(struct platform_device *pdev); 1015 1016static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev) 1017{ 1018 unsigned int mem_info[2] = { }; 1019 1020 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev, 1021 sizeof(struct device), GFP_KERNEL); 1022 if (!dev->mem_dev_l) { 1023 mfc_err("Not enough memory\n"); 1024 return -ENOMEM; 1025 } 1026 device_initialize(dev->mem_dev_l); 1027 of_property_read_u32_array(dev->plat_dev->dev.of_node, 1028 "samsung,mfc-l", mem_info, 2); 1029 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0], 1030 mem_info[0], mem_info[1], 1031 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1032 mfc_err("Failed to declare coherent memory for\n" 1033 "MFC device\n"); 1034 return -ENOMEM; 1035 } 1036 1037 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev, 1038 sizeof(struct device), GFP_KERNEL); 1039 if (!dev->mem_dev_r) { 1040 mfc_err("Not enough memory\n"); 1041 return -ENOMEM; 1042 } 1043 device_initialize(dev->mem_dev_r); 1044 of_property_read_u32_array(dev->plat_dev->dev.of_node, 1045 "samsung,mfc-r", mem_info, 2); 1046 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0], 1047 mem_info[0], mem_info[1], 1048 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1049 pr_err("Failed to declare coherent memory for\n" 1050 "MFC device\n"); 1051 return -ENOMEM; 1052 } 1053 return 0; 1054} 1055 1056/* MFC probe function */ 1057static int s5p_mfc_probe(struct platform_device *pdev) 1058{ 1059 struct s5p_mfc_dev *dev; 1060 struct video_device *vfd; 1061 struct resource *res; 1062 int ret; 1063 1064 pr_debug("%s++\n", __func__); 1065 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1066 if (!dev) { 1067 dev_err(&pdev->dev, "Not enough memory for MFC device\n"); 1068 return -ENOMEM; 1069 } 1070 1071 spin_lock_init(&dev->irqlock); 1072 spin_lock_init(&dev->condlock); 1073 dev->plat_dev = pdev; 1074 if (!dev->plat_dev) { 1075 dev_err(&pdev->dev, "No platform data specified\n"); 1076 return -ENODEV; 1077 } 1078 1079 dev->variant = mfc_get_drv_data(pdev); 1080 1081 ret = s5p_mfc_init_pm(dev); 1082 if (ret < 0) { 1083 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 1084 return ret; 1085 } 1086 1087 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1088 1089 dev->regs_base = devm_ioremap_resource(&pdev->dev, res); 1090 if (IS_ERR(dev->regs_base)) 1091 return PTR_ERR(dev->regs_base); 1092 1093 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1094 if (res == NULL) { 1095 dev_err(&pdev->dev, "failed to get irq resource\n"); 1096 ret = -ENOENT; 1097 goto err_res; 1098 } 1099 dev->irq = res->start; 1100 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, 1101 0, pdev->name, dev); 1102 if (ret) { 1103 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); 1104 goto err_res; 1105 } 1106 1107 if (pdev->dev.of_node) { 1108 ret = s5p_mfc_alloc_memdevs(dev); 1109 if (ret < 0) 1110 goto err_res; 1111 } else { 1112 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, 1113 "s5p-mfc-l", match_child); 1114 if (!dev->mem_dev_l) { 1115 mfc_err("Mem child (L) device get failed\n"); 1116 ret = -ENODEV; 1117 goto err_res; 1118 } 1119 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, 1120 "s5p-mfc-r", match_child); 1121 if (!dev->mem_dev_r) { 1122 mfc_err("Mem child (R) device get failed\n"); 1123 ret = -ENODEV; 1124 goto err_res; 1125 } 1126 } 1127 1128 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); 1129 if (IS_ERR(dev->alloc_ctx[0])) { 1130 ret = PTR_ERR(dev->alloc_ctx[0]); 1131 goto err_res; 1132 } 1133 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); 1134 if (IS_ERR(dev->alloc_ctx[1])) { 1135 ret = PTR_ERR(dev->alloc_ctx[1]); 1136 goto err_mem_init_ctx_1; 1137 } 1138 1139 mutex_init(&dev->mfc_mutex); 1140 1141 ret = s5p_mfc_alloc_firmware(dev); 1142 if (ret) 1143 goto err_alloc_fw; 1144 1145 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 1146 if (ret) 1147 goto err_v4l2_dev_reg; 1148 init_waitqueue_head(&dev->queue); 1149 1150 /* decoder */ 1151 vfd = video_device_alloc(); 1152 if (!vfd) { 1153 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1154 ret = -ENOMEM; 1155 goto err_dec_alloc; 1156 } 1157 vfd->fops = &s5p_mfc_fops; 1158 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); 1159 vfd->release = video_device_release; 1160 vfd->lock = &dev->mfc_mutex; 1161 vfd->v4l2_dev = &dev->v4l2_dev; 1162 vfd->vfl_dir = VFL_DIR_M2M; 1163 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); 1164 dev->vfd_dec = vfd; 1165 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1166 if (ret) { 1167 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1168 video_device_release(vfd); 1169 goto err_dec_reg; 1170 } 1171 v4l2_info(&dev->v4l2_dev, 1172 "decoder registered as /dev/video%d\n", vfd->num); 1173 video_set_drvdata(vfd, dev); 1174 1175 /* encoder */ 1176 vfd = video_device_alloc(); 1177 if (!vfd) { 1178 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1179 ret = -ENOMEM; 1180 goto err_enc_alloc; 1181 } 1182 vfd->fops = &s5p_mfc_fops; 1183 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); 1184 vfd->release = video_device_release; 1185 vfd->lock = &dev->mfc_mutex; 1186 vfd->v4l2_dev = &dev->v4l2_dev; 1187 vfd->vfl_dir = VFL_DIR_M2M; 1188 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); 1189 dev->vfd_enc = vfd; 1190 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1191 if (ret) { 1192 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1193 video_device_release(vfd); 1194 goto err_enc_reg; 1195 } 1196 v4l2_info(&dev->v4l2_dev, 1197 "encoder registered as /dev/video%d\n", vfd->num); 1198 video_set_drvdata(vfd, dev); 1199 platform_set_drvdata(pdev, dev); 1200 1201 dev->hw_lock = 0; 1202 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); 1203 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); 1204 atomic_set(&dev->watchdog_cnt, 0); 1205 init_timer(&dev->watchdog_timer); 1206 dev->watchdog_timer.data = (unsigned long)dev; 1207 dev->watchdog_timer.function = s5p_mfc_watchdog; 1208 1209 /* Initialize HW ops and commands based on MFC version */ 1210 s5p_mfc_init_hw_ops(dev); 1211 s5p_mfc_init_hw_cmds(dev); 1212 1213 pr_debug("%s--\n", __func__); 1214 return 0; 1215 1216/* Deinit MFC if probe had failed */ 1217err_enc_reg: 1218 video_device_release(dev->vfd_enc); 1219err_enc_alloc: 1220 video_unregister_device(dev->vfd_dec); 1221err_dec_reg: 1222 video_device_release(dev->vfd_dec); 1223err_dec_alloc: 1224 v4l2_device_unregister(&dev->v4l2_dev); 1225err_v4l2_dev_reg: 1226 s5p_mfc_release_firmware(dev); 1227err_alloc_fw: 1228 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1229err_mem_init_ctx_1: 1230 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1231err_res: 1232 s5p_mfc_final_pm(dev); 1233 1234 pr_debug("%s-- with error\n", __func__); 1235 return ret; 1236 1237} 1238 1239/* Remove the driver */ 1240static int s5p_mfc_remove(struct platform_device *pdev) 1241{ 1242 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); 1243 1244 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); 1245 1246 del_timer_sync(&dev->watchdog_timer); 1247 flush_workqueue(dev->watchdog_workqueue); 1248 destroy_workqueue(dev->watchdog_workqueue); 1249 1250 video_unregister_device(dev->vfd_enc); 1251 video_unregister_device(dev->vfd_dec); 1252 v4l2_device_unregister(&dev->v4l2_dev); 1253 s5p_mfc_release_firmware(dev); 1254 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1255 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1256 if (pdev->dev.of_node) { 1257 put_device(dev->mem_dev_l); 1258 put_device(dev->mem_dev_r); 1259 } 1260 1261 s5p_mfc_final_pm(dev); 1262 return 0; 1263} 1264 1265#ifdef CONFIG_PM_SLEEP 1266 1267static int s5p_mfc_suspend(struct device *dev) 1268{ 1269 struct platform_device *pdev = to_platform_device(dev); 1270 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1271 int ret; 1272 1273 if (m_dev->num_inst == 0) 1274 return 0; 1275 1276 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { 1277 mfc_err("Error: going to suspend for a second time\n"); 1278 return -EIO; 1279 } 1280 1281 /* Check if we're processing then wait if it necessary. */ 1282 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { 1283 /* Try and lock the HW */ 1284 /* Wait on the interrupt waitqueue */ 1285 ret = wait_event_interruptible_timeout(m_dev->queue, 1286 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT)); 1287 if (ret == 0) { 1288 mfc_err("Waiting for hardware to finish timed out\n"); 1289 return -EIO; 1290 } 1291 } 1292 1293 return s5p_mfc_sleep(m_dev); 1294} 1295 1296static int s5p_mfc_resume(struct device *dev) 1297{ 1298 struct platform_device *pdev = to_platform_device(dev); 1299 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1300 1301 if (m_dev->num_inst == 0) 1302 return 0; 1303 return s5p_mfc_wakeup(m_dev); 1304} 1305#endif 1306 1307#ifdef CONFIG_PM_RUNTIME 1308static int s5p_mfc_runtime_suspend(struct device *dev) 1309{ 1310 struct platform_device *pdev = to_platform_device(dev); 1311 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1312 1313 atomic_set(&m_dev->pm.power, 0); 1314 return 0; 1315} 1316 1317static int s5p_mfc_runtime_resume(struct device *dev) 1318{ 1319 struct platform_device *pdev = to_platform_device(dev); 1320 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1321 int pre_power; 1322 1323 if (!m_dev->alloc_ctx) 1324 return 0; 1325 pre_power = atomic_read(&m_dev->pm.power); 1326 atomic_set(&m_dev->pm.power, 1); 1327 return 0; 1328} 1329#endif 1330 1331/* Power management */ 1332static const struct dev_pm_ops s5p_mfc_pm_ops = { 1333 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) 1334 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, 1335 NULL) 1336}; 1337 1338struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { 1339 .h264_ctx = MFC_H264_CTX_BUF_SIZE, 1340 .non_h264_ctx = MFC_CTX_BUF_SIZE, 1341 .dsc = DESC_BUF_SIZE, 1342 .shm = SHARED_BUF_SIZE, 1343}; 1344 1345struct s5p_mfc_buf_size buf_size_v5 = { 1346 .fw = MAX_FW_SIZE, 1347 .cpb = MAX_CPB_SIZE, 1348 .priv = &mfc_buf_size_v5, 1349}; 1350 1351struct s5p_mfc_buf_align mfc_buf_align_v5 = { 1352 .base = MFC_BASE_ALIGN_ORDER, 1353}; 1354 1355static struct s5p_mfc_variant mfc_drvdata_v5 = { 1356 .version = MFC_VERSION, 1357 .port_num = MFC_NUM_PORTS, 1358 .buf_size = &buf_size_v5, 1359 .buf_align = &mfc_buf_align_v5, 1360 .fw_name = "s5p-mfc.fw", 1361}; 1362 1363struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { 1364 .dev_ctx = MFC_CTX_BUF_SIZE_V6, 1365 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, 1366 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, 1367 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, 1368 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, 1369}; 1370 1371struct s5p_mfc_buf_size buf_size_v6 = { 1372 .fw = MAX_FW_SIZE_V6, 1373 .cpb = MAX_CPB_SIZE_V6, 1374 .priv = &mfc_buf_size_v6, 1375}; 1376 1377struct s5p_mfc_buf_align mfc_buf_align_v6 = { 1378 .base = 0, 1379}; 1380 1381static struct s5p_mfc_variant mfc_drvdata_v6 = { 1382 .version = MFC_VERSION_V6, 1383 .port_num = MFC_NUM_PORTS_V6, 1384 .buf_size = &buf_size_v6, 1385 .buf_align = &mfc_buf_align_v6, 1386 .fw_name = "s5p-mfc-v6.fw", 1387}; 1388 1389struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = { 1390 .dev_ctx = MFC_CTX_BUF_SIZE_V7, 1391 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7, 1392 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7, 1393 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7, 1394 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7, 1395}; 1396 1397struct s5p_mfc_buf_size buf_size_v7 = { 1398 .fw = MAX_FW_SIZE_V7, 1399 .cpb = MAX_CPB_SIZE_V7, 1400 .priv = &mfc_buf_size_v7, 1401}; 1402 1403struct s5p_mfc_buf_align mfc_buf_align_v7 = { 1404 .base = 0, 1405}; 1406 1407static struct s5p_mfc_variant mfc_drvdata_v7 = { 1408 .version = MFC_VERSION_V7, 1409 .port_num = MFC_NUM_PORTS_V7, 1410 .buf_size = &buf_size_v7, 1411 .buf_align = &mfc_buf_align_v7, 1412 .fw_name = "s5p-mfc-v7.fw", 1413}; 1414 1415static struct platform_device_id mfc_driver_ids[] = { 1416 { 1417 .name = "s5p-mfc", 1418 .driver_data = (unsigned long)&mfc_drvdata_v5, 1419 }, { 1420 .name = "s5p-mfc-v5", 1421 .driver_data = (unsigned long)&mfc_drvdata_v5, 1422 }, { 1423 .name = "s5p-mfc-v6", 1424 .driver_data = (unsigned long)&mfc_drvdata_v6, 1425 }, { 1426 .name = "s5p-mfc-v7", 1427 .driver_data = (unsigned long)&mfc_drvdata_v7, 1428 }, 1429 {}, 1430}; 1431MODULE_DEVICE_TABLE(platform, mfc_driver_ids); 1432 1433static const struct of_device_id exynos_mfc_match[] = { 1434 { 1435 .compatible = "samsung,mfc-v5", 1436 .data = &mfc_drvdata_v5, 1437 }, { 1438 .compatible = "samsung,mfc-v6", 1439 .data = &mfc_drvdata_v6, 1440 }, { 1441 .compatible = "samsung,mfc-v7", 1442 .data = &mfc_drvdata_v7, 1443 }, 1444 {}, 1445}; 1446MODULE_DEVICE_TABLE(of, exynos_mfc_match); 1447 1448static void *mfc_get_drv_data(struct platform_device *pdev) 1449{ 1450 struct s5p_mfc_variant *driver_data = NULL; 1451 1452 if (pdev->dev.of_node) { 1453 const struct of_device_id *match; 1454 match = of_match_node(exynos_mfc_match, 1455 pdev->dev.of_node); 1456 if (match) 1457 driver_data = (struct s5p_mfc_variant *)match->data; 1458 } else { 1459 driver_data = (struct s5p_mfc_variant *) 1460 platform_get_device_id(pdev)->driver_data; 1461 } 1462 return driver_data; 1463} 1464 1465static struct platform_driver s5p_mfc_driver = { 1466 .probe = s5p_mfc_probe, 1467 .remove = s5p_mfc_remove, 1468 .id_table = mfc_driver_ids, 1469 .driver = { 1470 .name = S5P_MFC_NAME, 1471 .owner = THIS_MODULE, 1472 .pm = &s5p_mfc_pm_ops, 1473 .of_match_table = exynos_mfc_match, 1474 }, 1475}; 1476 1477module_platform_driver(s5p_mfc_driver); 1478 1479MODULE_LICENSE("GPL"); 1480MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); 1481MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); 1482 1483